1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "mt7620a.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/mtd/partitions/uimage.h>
10 compatible = "ralink,mt7620a-soc";
13 led-boot = &led_power;
14 led-failsafe = &led_power;
15 led-running = &led_power;
16 led-upgrade = &led_power;
20 compatible = "gpio-keys";
24 gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
25 linux,code = <KEY_RESTART>;
30 compatible = "gpio-leds";
33 label = "green:power";
34 gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
39 gpios = <&gpio2 26 GPIO_ACTIVE_LOW>;
44 gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
61 compatible = "jedec,spi-nor";
63 spi-max-frequency = <10000000>;
66 compatible = "fixed-partitions";
78 reg = <0x30000 0x10000>;
82 factory: partition@40000 {
84 reg = <0x40000 0x10000>;
90 reg = <0x50000 0x20000>;
95 compatible = "openwrt,uimage", "denx,uimage";
96 openwrt,offset = <FW_EDIMAX_OFFSET>;
97 openwrt,partition-magic = <FW_MAGIC_EDIMAX>;
99 reg = <0x00070000 0x00790000>;
107 groups = "i2c", "uartf", "nd_sd", "rgmii2";
113 phy_reset_pins: phy-reset {
115 groups = "spi refclk";
122 pinctrl-names = "default";
123 pinctrl-0 = <&rgmii1_pins &mdio_pins &phy_reset_pins>;
125 nvmem-cells = <&macaddr_factory_4>;
126 nvmem-cell-names = "mac-address";
128 phy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
129 phy-reset-duration = <30>;
133 mediatek,fixed-link = <1000 1 1 1>;
140 phy0: ethernet-phy@0 {
146 phy1: ethernet-phy@1 {
152 phy2: ethernet-phy@2 {
158 phy3: ethernet-phy@3 {
164 phy4: ethernet-phy@4 {
173 mediatek,ephy-base = /bits/ 8 <8>;
177 ralink,mtd-eeprom = <&factory 0x0>;
178 nvmem-cells = <&macaddr_factory_4>;
179 nvmem-cell-names = "mac-address";
188 reg = <0x0000 0 0 0 0>;
189 mediatek,mtd-eeprom = <&factory 0x8000>;
190 ieee80211-freq-limit = <5000000 6000000>;
191 nvmem-cells = <&macaddr_factory_4>;
192 nvmem-cell-names = "mac-address";
193 mac-address-increment = <2>;
198 compatible = "nvmem-cells";
199 #address-cells = <1>;
202 macaddr_factory_4: macaddr@4 {