1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "mt7620a.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
9 compatible = "ralink,mt7620a-soc";
12 led-boot = &led_power;
13 led-failsafe = &led_power;
14 led-running = &led_power;
15 led-upgrade = &led_power;
19 bootargs = "console=ttyS0,57600";
23 compatible = "gpio-keys";
27 gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
28 linux,code = <KEY_RESTART>;
32 label = "switch high";
33 gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
35 linux,input-type = <EV_SW>;
40 gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
42 linux,input-type = <EV_SW>;
59 compatible = "jedec,spi-nor";
61 spi-max-frequency = <10000000>;
64 compatible = "fixed-partitions";
76 reg = <0x30000 0x10000>;
80 factory: partition@40000 {
82 reg = <0x40000 0x10000>;
88 reg = <0x50000 0x20000>;
93 compatible = "edimax,uimage";
95 reg = <0x00070000 0x00790000>;
103 groups = "i2c", "uartf", "nd_sd", "rgmii2";
109 phy_reset_pins: phy-reset {
111 groups = "spi refclk";
120 mtd-mac-address = <&factory 0x4>;
122 pinctrl-names = "default";
123 pinctrl-0 = <&rgmii1_pins &mdio_pins &phy_reset_pins>;
125 mediatek,mdio-mode = <1>;
127 phy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
128 phy-reset-duration = <30>;
132 mediatek,fixed-link = <1000 1 1 1>;
139 phy0: ethernet-phy@0 {
145 phy1: ethernet-phy@1 {
151 phy2: ethernet-phy@2 {
157 phy3: ethernet-phy@3 {
163 phy4: ethernet-phy@4 {
172 mediatek,port5 = "gmac";
176 ralink,mtd-eeprom = <&factory 0x0>;
185 reg = <0x0000 0 0 0 0>;
186 mediatek,mtd-eeprom = <&factory 0x8000>;