1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include "mt7620a.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
9 compatible = "head-weblink,hdrm200", "ralink,mt7620a-soc";
10 model = "Head Weblink HDRM200";
13 led-boot = &led_system;
14 led-failsafe = &led_system;
15 led-running = &led_system;
16 led-upgrade = &led_system;
20 bootargs = "console=ttyS1,57600";
24 compatible = "gpio-leds";
28 gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
32 label = "green:system";
33 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
38 gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
43 compatible = "gpio-keys";
47 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
48 linux,code = <KEY_WPS_BUTTON>;
53 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
54 linux,code = <KEY_RESTART>;
63 compatible = "jedec,spi-nor";
65 spi-max-frequency = <10000000>;
68 compatible = "fixed-partitions";
80 reg = <0x30000 0x10000>;
84 factory: partition@40000 {
86 reg = <0x40000 0x10000>;
90 compatible = "fixed-layout";
94 eeprom_factory_0: eeprom@0 {
98 eeprom_factory_8000: eeprom@8000 {
102 macaddr_factory_4: macaddr@4 {
108 firmware: partition@50000 {
109 compatible = "denx,uimage";
111 reg = <0x50000 0xfb0000>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
141 nvmem-cells = <&macaddr_factory_4>;
142 nvmem-cell-names = "mac-address";
146 phy-handle = <&phy4>;
152 phy-handle = <&phy5>;
159 phy4: ethernet-phy@4 {
164 phy5: ethernet-phy@5 {
173 mediatek,ephy-base = /bits/ 8 <8>;
177 nvmem-cells = <&eeprom_factory_0>;
178 nvmem-cell-names = "eeprom";
183 groups = "i2c", "uartf", "pa", "spi refclk",
195 compatible = "mediatek,mt76";
196 reg = <0x0000 0 0 0 0>;
197 nvmem-cells = <&eeprom_factory_8000>;
198 nvmem-cell-names = "eeprom";
199 ieee80211-freq-limit = <5000000 6000000>;