f7a5aed064c445dad006d5160fb253975faf490b
[openwrt/staging/hauke.git] / target / linux / ramips / dts / mt7620a_lava_lr-25g001.dts
1 #include "mt7620a.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/mtd/partitions/uimage.h>
6
7 / {
8 compatible = "lava,lr-25g001", "ralink,mt7620a-soc";
9 model = "LAVA LR-25G001";
10
11 aliases {
12 led-boot = &led_status;
13 led-failsafe = &led_status;
14 led-running = &led_status;
15 led-upgrade = &led_status;
16 };
17
18 keys {
19 compatible = "gpio-keys";
20
21 wps {
22 label = "wps";
23 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
24 linux,code = <KEY_WPS_BUTTON>;
25 };
26
27 reset {
28 label = "reset";
29 gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
30 linux,code = <KEY_RESTART>;
31 };
32 };
33
34 leds {
35 compatible = "gpio-leds";
36
37 led_status: status {
38 label = "green:status";
39 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
40 };
41
42 wifi2g {
43 label = "green:wifi2g";
44 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
45 linux,default-trigger = "phy1tpt";
46 };
47
48 wifi5g {
49 label = "green:wifi5g";
50 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
51 linux,default-trigger = "phy0tpt";
52 };
53 };
54
55 gpio_export {
56 compatible = "gpio-export";
57 #size-cells = <0>;
58
59 usbpower {
60 gpio-export,name = "usbpower";
61 gpio-export,output = <1>;
62 gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
63 };
64 };
65 };
66
67 &spi0 {
68 status = "okay";
69
70 flash@0 {
71 compatible = "jedec,spi-nor";
72 reg = <0>;
73 spi-max-frequency = <10000000>;
74
75 partitions {
76 compatible = "fixed-partitions";
77 #address-cells = <1>;
78 #size-cells = <1>;
79
80 partition@0 {
81 label = "jboot";
82 reg = <0x0 0x10000>;
83 read-only;
84 };
85
86 partition@10000 {
87 compatible = "openwrt,uimage", "denx,uimage";
88 openwrt,ih-magic = <IH_MAGIC_OKLI>;
89 openwrt,offset = <0x10000>;
90 label = "firmware";
91 reg = <0x10000 0xfe0000>;
92 };
93
94 config: partition@ff0000 {
95 compatible = "nvmem-cells";
96 label = "config";
97 reg = <0xff0000 0x10000>;
98 #address-cells = <1>;
99 #size-cells = <1>;
100 read-only;
101
102 eeprom_config_e08a: eeprom@e08a {
103 reg = <0xe08a 0x200>;
104 };
105
106 macaddr_config_e07e: macaddr@e07e {
107 reg = <0xe07e 0x6>;
108 };
109 };
110 };
111 };
112 };
113
114 &ehci {
115 status = "okay";
116 };
117
118 &ohci {
119 status = "okay";
120 };
121
122 &ethernet {
123 pinctrl-names = "default";
124 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
125
126 port@5 {
127 status = "okay";
128 phy-mode = "rgmii";
129 mediatek,fixed-link = <1000 1 1 1>;
130 };
131
132 mdio-bus {
133 status = "okay";
134
135 ethernet-phy@0 {
136 reg = <0>;
137 phy-mode = "rgmii";
138 qca,ar8327-initvals = <
139 0x04 0x87300000 /* PORT0 PAD MODE CTRL */
140 0x0c 0x00000000 /* PORT6 PAD MODE CTRL */
141 0x7c 0x0000007e /* PORT0_STATUS */
142 0x80 0x00001200 /* PORT1_STATUS */
143 0x84 0x00001200 /* PORT2_STATUS */
144 0x88 0x00001200 /* PORT3_STATUS */
145 0x8c 0x00001200 /* PORT4_STATUS */
146 0x90 0x00001200 /* PORT5_STATUS */
147 0x94 0x00000000 /* PORT6_STATUS */
148 >;
149 };
150 };
151 };
152
153 &gsw {
154 mediatek,ephy-base = /bits/ 8 <8>;
155 };
156
157 &pcie {
158 status = "okay";
159 };
160
161 &pcie0 {
162 mt76x0e@0,0 {
163 reg = <0x0000 0 0 0 0>;
164 nvmem-cells = <&eeprom_config_e08a>, <&macaddr_config_e07e>;
165 nvmem-cell-names = "eeprom", "mac-address";
166 mac-address-increment = <2>;
167 };
168 };
169
170 &state_default {
171 gpio {
172 groups = "uartf", "i2c";
173 function = "gpio";
174 };
175 };