4 compatible = "mediatek,mtk7621-soc";
8 compatible = "mips,mips1004Kc";
12 compatible = "mips,mips1004Kc";
18 #interrupt-cells = <1>;
20 compatible = "mti,cpu-interrupt-controller";
24 compatible = "palmbus";
25 reg = <0x1E000000 0x100000>;
26 ranges = <0x0 0x1E000000 0x0FFFFF>;
32 compatible = "mtk,mt7621-sysc";
37 compatible = "mtk,mt7621-wdt";
45 compatible = "mtk,mt7621-gpio";
50 compatible = "mtk,mt7621-gpio-bank";
57 compatible = "mtk,mt7621-gpio-bank";
64 compatible = "mtk,mt7621-gpio-bank";
71 compatible = "mtk,mt7621-memc";
76 compatible = "ns16550a";
79 interrupt-parent = <&gic>;
80 interrupts = <0 26 4>;
90 compatible = "ralink,mt7621-spi";
93 resets = <&rstctrl 18>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&spi_pins>;
103 #address-cells = <1>;
106 spi-max-frequency = <10000000>;
107 m25p,chunked-io = <32>;
113 compatible = "ralink,rt2880-pinmux";
114 pinctrl-names = "default";
115 pinctrl-0 = <&state_default>;
117 state_default: pinctrl0 {
122 ralink,group = "spi";
123 ralink,function = "spi";
129 ralink,group = "i2c";
130 ralink,function = "i2c";
136 ralink,group = "uart1";
137 ralink,function = "uart1";
143 ralink,group = "uart2";
144 ralink,function = "uart2";
150 ralink,group = "uart3";
151 ralink,function = "uart3";
155 rgmii1_pins: rgmii1 {
157 ralink,group = "rgmii1";
158 ralink,function = "rgmii1";
162 rgmii2_pins: rgmii2 {
164 ralink,group = "rgmii2";
165 ralink,function = "rgmii2";
171 ralink,group = "mdio";
172 ralink,function = "mdio";
178 ralink,group = "pcie";
179 ralink,function = "pcie rst";
185 ralink,group = "spi";
186 ralink,function = "nand1";
190 ralink,group = "sdhci";
191 ralink,function = "nand2";
197 ralink,group = "sdhci";
198 ralink,function = "sdhci";
204 compatible = "ralink,rt2880-reset";
209 compatible = "ralink,mt7620-sdhci";
210 reg = <0x1E130000 4000>;
212 interrupt-parent = <&gic>;
213 interrupts = <0 20 4>;
219 compatible = "xhci-platform";
220 reg = <0x1E1C0000 4000>;
222 interrupt-parent = <&gic>;
223 interrupts = <0 22 4>;
226 gic: interrupt-controller@1fbc0000 {
227 compatible = "mti,gic";
228 reg = <0x1fbc0000 0x80>;
230 interrupt-controller;
231 #interrupt-cells = <3>;
233 mti,reserved-cpu-vectors = <7>;
237 compatible = "mtk,mt7621-nand";
239 reg = <0x1e003000 0x800
241 #address-cells = <1>;
246 reg = <0x00000 0x80000>; /* 64 KB */
251 reg = <0x80000 0x80000>; /* 64 KB */
256 reg = <0x100000 0x40000>;
261 reg = <0x140000 0xec0000>;
266 compatible = "ralink,mt7621-eth";
267 reg = <0x1e100000 10000>;
269 #address-cells = <1>;
272 resets = <&rstctrl 6 &rstctrl 23>;
273 reset-names = "fe", "eth";
275 interrupt-parent = <&gic>;
276 interrupts = <0 3 4>;
279 #address-cells = <1>;
282 phy1f: ethernet-phy@1f {
290 compatible = "ralink,mt7620a-gsw";
291 reg = <0x1e110000 8000>;
292 interrupt-parent = <&gic>;
293 interrupts = <0 23 4>;
297 compatible = "mediatek,mt7621-pci";
298 reg = <0x1e140000 0x100
301 #address-cells = <3>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&pcie_pins>;
311 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
312 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
315 interrupt-parent = <&gic>;
323 reg = <0x0000 0 0 0 0>;
325 #address-cells = <3>;
332 reg = <0x0800 0 0 0 0>;
334 #address-cells = <3>;
341 reg = <0x1000 0 0 0 0>;
343 #address-cells = <3>;