target/linux/ramips/dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2 #include <dt-bindings/clock/mt7621-clk.h>
   3
   4 / {
   5         #address-cells = <1>;
   6         #size-cells = <1>;
   7         compatible = "mediatek,mt7621-soc";
   8
   9         cpus {
  10                 #address-cells = <1>;
  11                 #size-cells = <0>;
  12
  13                 cpu@0 {
  14                         device_type = "cpu";
  15                         compatible = "mips,mips1004Kc";
  16                         reg = <0>;
  17                 };
  18
  19                 cpu@1 {
  20                         device_type = "cpu";
  21                         compatible = "mips,mips1004Kc";
  22                         reg = <1>;
  23                 };
  24         };
  25
  26         cpuintc: cpuintc {
  27                 #address-cells = <0>;
  28                 #interrupt-cells = <1>;
  29                 interrupt-controller;
  30                 compatible = "mti,cpu-interrupt-controller";
  31         };
  32
  33         aliases {
  34                 serial0 = &uartlite;
  35         };
  36
  37         pll: pll {
  38                 compatible = "mediatek,mt7621-pll", "syscon";
  39
  40                 #clock-cells = <1>;
  41                 clock-output-names = "cpu", "bus";
  42         };
  43
  44         sysclock: sysclock {
  45                 #clock-cells = <0>;
  46                 compatible = "fixed-clock";
  47
  48                 /* FIXME: there should be way to detect this */
  49                 clock-frequency = <50000000>;
  50         };
  51
  52         palmbus: palmbus@1E000000 {
  53                 compatible = "palmbus";
  54                 reg = <0x1E000000 0x100000>;
  55                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  56
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59
  60                 sysc: sysc@0 {
  61                         compatible = "mtk,mt7621-sysc";
  62                         reg = <0x0 0x100>;
  63                 };
  64
  65                 wdt: wdt@100 {
  66                         compatible = "mediatek,mt7621-wdt";
  67                         reg = <0x100 0x100>;
  68                 };
  69
  70                 gpio@600 {
  71                         #address-cells = <1>;
  72                         #size-cells = <0>;
  73
  74                         compatible = "mtk,mt7621-gpio";
  75                         reg = <0x600 0x100>;
  76
  77                         interrupt-parent = <&gic>;
  78                         interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
  79
  80                         gpio0: bank@0 {
  81                                 reg = <0>;
  82                                 compatible = "mtk,mt7621-gpio-bank";
  83                                 gpio-controller;
  84                                 #gpio-cells = <2>;
  85                         };
  86
  87                         gpio1: bank@1 {
  88                                 reg = <1>;
  89                                 compatible = "mtk,mt7621-gpio-bank";
  90                                 gpio-controller;
  91                                 #gpio-cells = <2>;
  92                         };
  93
  94                         gpio2: bank@2 {
  95                                 reg = <2>;
  96                                 compatible = "mtk,mt7621-gpio-bank";
  97                                 gpio-controller;
  98                                 #gpio-cells = <2>;
  99                         };
 100                 };
 101
 102                 i2c: i2c@900 {
 103                         compatible = "mediatek,mt7621-i2c";
 104                         reg = <0x900 0x100>;
 105
 106                         clocks = <&sysclock>;
 107
 108                         resets = <&rstctrl 16>;
 109                         reset-names = "i2c";
 110
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113
 114                         status = "disabled";
 115
 116                         pinctrl-names = "default";
 117                         pinctrl-0 = <&i2c_pins>;
 118                 };
 119
 120                 i2s: i2s@a00 {
 121                         compatible = "mediatek,mt7621-i2s";
 122                         reg = <0xa00 0x100>;
 123
 124                         clocks = <&sysclock>;
 125
 126                         resets = <&rstctrl 17>;
 127                         reset-names = "i2s";
 128
 129                         interrupt-parent = <&gic>;
 130                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 131
 132                         txdma-req = <2>;
 133                         rxdma-req = <3>;
 134
 135                         dmas = <&gdma 4>,
 136                                 <&gdma 6>;
 137                         dma-names = "tx", "rx";
 138
 139                         status = "disabled";
 140                 };
 141
 142                 systick: systick@500 {
 143                         compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
 144                         reg = <0x500 0x10>;
 145
 146                         resets = <&rstctrl 28>;
 147                         reset-names = "intc";
 148
 149                         interrupt-parent = <&gic>;
 150                         interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
 151                 };
 152
 153                 memc: memc@5000 {
 154                         compatible = "mtk,mt7621-memc";
 155                         reg = <0x5000 0x1000>;
 156                 };
 157
 158                 cpc: cpc@1fbf0000 {
 159                         compatible = "mtk,mt7621-cpc";
 160                         reg = <0x1fbf0000 0x8000>;
 161                 };
 162
 163                 mc: mc@1fbf8000 {
 164                         compatible = "mtk,mt7621-mc";
 165                         reg = <0x1fbf8000 0x8000>;
 166                 };
 167
 168                 uartlite: uartlite@c00 {
 169                         compatible = "ns16550a";
 170                         reg = <0xc00 0x100>;
 171
 172                         clock-frequency = <50000000>;
 173
 174                         interrupt-parent = <&gic>;
 175                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 176
 177                         reg-shift = <2>;
 178                         reg-io-width = <4>;
 179                         no-loopback-test;
 180                 };
 181
 182                 uartlite2: uartlite2@d00 {
 183                         compatible = "ns16550a";
 184                         reg = <0xd00 0x100>;
 185
 186                         clock-frequency = <50000000>;
 187
 188                         interrupt-parent = <&gic>;
 189                         interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
 190
 191                         reg-shift = <2>;
 192                         reg-io-width = <4>;
 193
 194                         pinctrl-names = "default";
 195                         pinctrl-0 = <&uart2_pins>;
 196
 197                         status = "disabled";
 198                 };
 199
 200                 uartlite3: uartlite3@e00 {
 201                         compatible = "ns16550a";
 202                         reg = <0xe00 0x100>;
 203
 204                         clock-frequency = <50000000>;
 205
 206                         interrupt-parent = <&gic>;
 207                         interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
 208
 209                         reg-shift = <2>;
 210                         reg-io-width = <4>;
 211
 212                         pinctrl-names = "default";
 213                         pinctrl-0 = <&uart3_pins>;
 214
 215                         status = "disabled";
 216                 };
 217
 218                 spi0: spi@b00 {
 219                         status = "disabled";
 220
 221                         compatible = "ralink,mt7621-spi";
 222                         reg = <0xb00 0x100>;
 223
 224                         clocks = <&pll MT7621_CLK_BUS>;
 225
 226                         resets = <&rstctrl 18>;
 227                         reset-names = "spi";
 228
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231
 232                         pinctrl-names = "default";
 233                         pinctrl-0 = <&spi_pins>;
 234                 };
 235
 236                 gdma: gdma@2800 {
 237                         compatible = "ralink,rt3883-gdma";
 238                         reg = <0x2800 0x800>;
 239
 240                         resets = <&rstctrl 14>;
 241                         reset-names = "dma";
 242
 243                         interrupt-parent = <&gic>;
 244                         interrupts = <0 13 4>;
 245
 246                         #dma-cells = <1>;
 247                         #dma-channels = <16>;
 248                         #dma-requests = <16>;
 249
 250                         status = "disabled";
 251                 };
 252
 253                 hsdma: hsdma@7000 {
 254                         compatible = "mediatek,mt7621-hsdma";
 255                         reg = <0x7000 0x1000>;
 256
 257                         resets = <&rstctrl 5>;
 258                         reset-names = "hsdma";
 259
 260                         interrupt-parent = <&gic>;
 261                         interrupts = <0 11 4>;
 262
 263                         #dma-cells = <1>;
 264                         #dma-channels = <1>;
 265                         #dma-requests = <1>;
 266
 267                         status = "disabled";
 268                 };
 269         };
 270
 271         pinctrl: pinctrl {
 272                 compatible = "ralink,rt2880-pinmux";
 273                 pinctrl-names = "default";
 274                 pinctrl-0 = <&state_default>;
 275
 276                 state_default: pinctrl0 {
 277                 };
 278
 279                 i2c_pins: i2c_pins {
 280                         i2c_pins {
 281                                 ralink,group = "i2c";
 282                                 ralink,function = "i2c";
 283                         };
 284                 };
 285
 286                 spi_pins: spi_pins {
 287                         spi_pins {
 288                                 ralink,group = "spi";
 289                                 ralink,function = "spi";
 290                         };
 291                 };
 292
 293                 uart1_pins: uart1 {
 294                         uart1 {
 295                                 ralink,group = "uart1";
 296                                 ralink,function = "uart1";
 297                         };
 298                 };
 299
 300                 uart2_pins: uart2 {
 301                         uart2 {
 302                                 ralink,group = "uart2";
 303                                 ralink,function = "uart2";
 304                         };
 305                 };
 306
 307                 uart3_pins: uart3 {
 308                         uart3 {
 309                                 ralink,group = "uart3";
 310                                 ralink,function = "uart3";
 311                         };
 312                 };
 313
 314                 rgmii1_pins: rgmii1 {
 315                         rgmii1 {
 316                                 ralink,group = "rgmii1";
 317                                 ralink,function = "rgmii1";
 318                         };
 319                 };
 320
 321                 rgmii2_pins: rgmii2 {
 322                         rgmii2 {
 323                                 ralink,group = "rgmii2";
 324                                 ralink,function = "rgmii2";
 325                         };
 326                 };
 327
 328                 mdio_pins: mdio {
 329                         mdio {
 330                                 ralink,group = "mdio";
 331                                 ralink,function = "mdio";
 332                         };
 333                 };
 334
 335                 pcie_pins: pcie {
 336                         pcie {
 337                                 ralink,group = "pcie";
 338                                 ralink,function = "pcie rst";
 339                         };
 340                 };
 341
 342                 nand_pins: nand {
 343                         spi-nand {
 344                                 ralink,group = "spi";
 345                                 ralink,function = "nand1";
 346                         };
 347
 348                         sdhci-nand {
 349                                 ralink,group = "sdhci";
 350                                 ralink,function = "nand2";
 351                         };
 352                 };
 353
 354                 sdhci_pins: sdhci {
 355                         sdhci {
 356                                 ralink,group = "sdhci";
 357                                 ralink,function = "sdhci";
 358                         };
 359                 };
 360         };
 361
 362         rstctrl: rstctrl {
 363                 compatible = "ralink,rt2880-reset";
 364                 #reset-cells = <1>;
 365         };
 366
 367         clkctrl: clkctrl {
 368                 compatible = "ralink,rt2880-clock";
 369                 #clock-cells = <1>;
 370         };
 371
 372         sdhci: sdhci@1E130000 {
 373                 status = "disabled";
 374
 375                 compatible = "ralink,mt7620-sdhci";
 376                 reg = <0x1E130000 0x4000>;
 377
 378                 interrupt-parent = <&gic>;
 379                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 380
 381                 pinctrl-names = "default";
 382                 pinctrl-0 = <&sdhci_pins>;
 383         };
 384
 385         xhci: xhci@1E1C0000 {
 386                 #address-cells = <1>;
 387                 #size-cells = <0>;
 388                 status = "okay";
 389
 390                 compatible = "mediatek,mt8173-xhci";
 391                 reg = <0x1e1c0000 0x1000
 392                        0x1e1d0700 0x0100>;
 393                 reg-names = "mac", "ippc";
 394
 395                 clocks = <&sysclock>;
 396                 clock-names = "sys_ck";
 397
 398                 interrupt-parent = <&gic>;
 399                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 400
 401                 /*
 402                  * Port 1 of both hubs is one usb slot and referenced here.
 403                  * The binding doesn't allow to address individual hubs.
 404                  * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
 405                  */
 406                 xhci_ehci_port1: port@1 {
 407                         reg = <1>;
 408                         #trigger-source-cells = <0>;
 409                 };
 410
 411                 /*
 412                  * Only the second usb hub has a second port. That port serves
 413                  * ehci and ohci.
 414                  */
 415                 ehci_port2: port@2 {
 416                         reg = <2>;
 417                         #trigger-source-cells = <0>;
 418                 };
 419         };
 420
 421         gic: interrupt-controller@1fbc0000 {
 422                 compatible = "mti,gic";
 423                 reg = <0x1fbc0000 0x2000>;
 424
 425                 interrupt-controller;
 426                 #interrupt-cells = <3>;
 427
 428                 mti,reserved-cpu-vectors = <7>;
 429
 430                 timer {
 431                         compatible = "mti,gic-timer";
 432                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 433                         clocks = <&pll MT7621_CLK_CPU>;
 434                 };
 435         };
 436
 437         nand: nand@1e003000 {
 438                 status = "disabled";
 439
 440                 compatible = "mtk,mt7621-nand";
 441                 bank-width = <2>;
 442                 reg = <0x1e003000 0x800
 443                         0x1e003800 0x800>;
 444         };
 445
 446         ethernet: ethernet@1e100000 {
 447                 compatible = "mediatek,mt7621-eth";
 448                 reg = <0x1e100000 0x10000>;
 449
 450                 #address-cells = <1>;
 451                 #size-cells = <1>;
 452
 453                 resets = <&rstctrl 6 &rstctrl 23>;
 454                 reset-names = "fe", "eth";
 455
 456                 interrupt-parent = <&gic>;
 457                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 458
 459                 mediatek,switch = <&gsw>;
 460
 461                 mdio-bus {
 462                         #address-cells = <1>;
 463                         #size-cells = <0>;
 464
 465                         phy1f: ethernet-phy@1f {
 466                                 reg = <0x1f>;
 467                                 phy-mode = "rgmii";
 468                         };
 469                 };
 470
 471                 hnat: hnat@0 {
 472                         compatible = "mediatek,mt7623-hnat";
 473                         reg = <0 0x10000>;
 474                         mtketh-ppd = "eth0";
 475                         mtketh-lan = "eth0";
 476                         mtketh-wan = "eth0";
 477                         resets = <&rstctrl 0>;
 478                         reset-names = "mtketh";
 479                 };
 480         };
 481
 482         gsw: gsw@1e110000 {
 483                 compatible = "mediatek,mt7621-gsw";
 484                 reg = <0x1e110000 0x8000>;
 485                 interrupt-parent = <&gic>;
 486                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 487         };
 488
 489         pcie: pcie@1e140000 {
 490                 compatible = "mediatek,mt7621-pci";
 491                 reg = <0x1e140000 0x100
 492                         0x1e142000 0x100>;
 493
 494                 #address-cells = <3>;
 495                 #size-cells = <2>;
 496
 497                 pinctrl-names = "default";
 498                 pinctrl-0 = <&pcie_pins>;
 499
 500                 device_type = "pci";
 501
 502                 bus-range = <0 255>;
 503                 ranges = <
 504                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 505                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 506                 >;
 507
 508                 interrupt-parent = <&gic>;
 509                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 510                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 511                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 512
 513                 status = "disabled";
 514
 515                 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
 516                 reset-names = "pcie0", "pcie1", "pcie2";
 517                 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
 518                 clock-names = "pcie0", "pcie1", "pcie2";
 519
 520                 pcie0: pcie@0,0 {
 521                         reg = <0x0000 0 0 0 0>;
 522
 523                         #address-cells = <3>;
 524                         #size-cells = <2>;
 525
 526                         ranges;
 527                 };
 528
 529                 pcie1: pcie@1,0 {
 530                         reg = <0x0800 0 0 0 0>;
 531
 532                         #address-cells = <3>;
 533                         #size-cells = <2>;
 534
 535                         ranges;
 536                 };
 537
 538                 pcie2: pcie@2,0 {
 539                         reg = <0x1000 0 0 0 0>;
 540
 541                         #address-cells = <3>;
 542                         #size-cells = <2>;
 543
 544                         ranges;
 545                 };
 546         };
 547 };