1 #include <dt-bindings/interrupt-controller/mips-gic.h>
6 compatible = "mediatek,mtk7621-soc";
10 compatible = "mips,mips1004Kc";
14 compatible = "mips,mips1004Kc";
20 #interrupt-cells = <1>;
22 compatible = "mti,cpu-interrupt-controller";
29 cpuclock: cpuclock@0 {
31 compatible = "fixed-clock";
33 /* FIXME: there should be way to detect this */
34 clock-frequency = <880000000>;
37 sysclock: sysclock@0 {
39 compatible = "fixed-clock";
41 /* FIXME: there should be way to detect this */
42 clock-frequency = <50000000>;
45 palmbus: palmbus@1E000000 {
46 compatible = "palmbus";
47 reg = <0x1E000000 0x100000>;
48 ranges = <0x0 0x1E000000 0x0FFFFF>;
54 compatible = "mtk,mt7621-sysc";
59 compatible = "mtk,mt7621-wdt";
67 compatible = "mtk,mt7621-gpio";
72 compatible = "mtk,mt7621-gpio-bank";
79 compatible = "mtk,mt7621-gpio-bank";
86 compatible = "mtk,mt7621-gpio-bank";
93 compatible = "mediatek,mt7621-i2c";
98 resets = <&rstctrl 16>;
101 #address-cells = <1>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&i2c_pins>;
111 compatible = "mtk,mt7621-memc";
116 compatible = "mtk,mt7621-cpc";
117 reg = <0x1fbf0000 0x8000>;
121 compatible = "mtk,mt7621-mc";
122 reg = <0x1fbf8000 0x8000>;
125 uartlite: uartlite@c00 {
126 compatible = "ns16550a";
129 clocks = <&sysclock>;
130 clock-frequency = <50000000>;
132 interrupt-parent = <&gic>;
133 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
143 compatible = "ralink,mt7621-spi";
146 clocks = <&sysclock>;
148 resets = <&rstctrl 18>;
151 #address-cells = <1>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&spi_pins>;
158 #address-cells = <1>;
161 spi-max-frequency = <10000000>;
162 m25p,chunked-io = <32>;
167 compatible = "ralink,rt3883-gdma";
168 reg = <0x2800 0x800>;
170 resets = <&rstctrl 14>;
173 interrupt-parent = <&gic>;
174 interrupts = <0 13 4>;
177 #dma-channels = <16>;
178 #dma-requests = <16>;
184 compatible = "mediatek,mt7621-hsdma";
185 reg = <0x7000 0x1000>;
187 resets = <&rstctrl 5>;
188 reset-names = "hsdma";
190 interrupt-parent = <&gic>;
191 interrupts = <0 11 4>;
202 compatible = "ralink,rt2880-pinmux";
203 pinctrl-names = "default";
204 pinctrl-0 = <&state_default>;
206 state_default: pinctrl0 {
211 ralink,group = "i2c";
212 ralink,function = "i2c";
218 ralink,group = "spi";
219 ralink,function = "spi";
225 ralink,group = "uart1";
226 ralink,function = "uart1";
232 ralink,group = "uart2";
233 ralink,function = "uart2";
239 ralink,group = "uart3";
240 ralink,function = "uart3";
244 rgmii1_pins: rgmii1 {
246 ralink,group = "rgmii1";
247 ralink,function = "rgmii1";
251 rgmii2_pins: rgmii2 {
253 ralink,group = "rgmii2";
254 ralink,function = "rgmii2";
260 ralink,group = "mdio";
261 ralink,function = "mdio";
267 ralink,group = "pcie";
268 ralink,function = "pcie rst";
274 ralink,group = "spi";
275 ralink,function = "nand1";
279 ralink,group = "sdhci";
280 ralink,function = "nand2";
286 ralink,group = "sdhci";
287 ralink,function = "sdhci";
293 compatible = "ralink,rt2880-reset";
298 compatible = "ralink,rt2880-clock";
302 sdhci: sdhci@1E130000 {
303 compatible = "ralink,mt7620-sdhci";
304 reg = <0x1E130000 0x4000>;
306 interrupt-parent = <&gic>;
307 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
310 xhci: xhci@1E1C0000 {
313 compatible = "mediatek,mt8173-xhci";
314 reg = <0x1e1c0000 0x1000
317 clocks = <&sysclock>;
318 clock-names = "sys_ck";
320 interrupt-parent = <&gic>;
321 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
324 gic: interrupt-controller@1fbc0000 {
325 compatible = "mti,gic";
326 reg = <0x1fbc0000 0x2000>;
328 interrupt-controller;
329 #interrupt-cells = <3>;
331 mti,reserved-cpu-vectors = <7>;
334 compatible = "mti,gic-timer";
335 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
336 clocks = <&cpuclock>;
340 nand: nand@1e003000 {
343 compatible = "mtk,mt7621-nand";
345 reg = <0x1e003000 0x800
347 #address-cells = <1>;
351 ethernet: ethernet@1e100000 {
352 compatible = "mediatek,mt7621-eth";
353 reg = <0x1e100000 0x10000>;
355 #address-cells = <1>;
358 resets = <&rstctrl 6 &rstctrl 23>;
359 reset-names = "fe", "eth";
361 interrupt-parent = <&gic>;
362 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
364 mediatek,switch = <&gsw>;
367 #address-cells = <1>;
370 phy1f: ethernet-phy@1f {
378 compatible = "mediatek,mt7621-gsw";
379 reg = <0x1e110000 0x8000>;
380 interrupt-parent = <&gic>;
381 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
384 pcie: pcie@1e140000 {
385 compatible = "mediatek,mt7621-pci";
386 reg = <0x1e140000 0x100
389 #address-cells = <3>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&pcie_pins>;
399 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
400 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
403 interrupt-parent = <&gic>;
404 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
405 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
406 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
410 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
411 reset-names = "pcie0", "pcie1", "pcie2";
412 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
413 clock-names = "pcie0", "pcie1", "pcie2";
416 reg = <0x0000 0 0 0 0>;
418 #address-cells = <3>;
425 reg = <0x0800 0 0 0 0>;
427 #address-cells = <3>;
434 reg = <0x1000 0 0 0 0>;
436 #address-cells = <3>;