1 #include <dt-bindings/interrupt-controller/mips-gic.h>
6 compatible = "mediatek,mt7621-soc";
14 compatible = "mips,mips1004Kc";
20 compatible = "mips,mips1004Kc";
27 #interrupt-cells = <1>;
29 compatible = "mti,cpu-interrupt-controller";
38 compatible = "fixed-clock";
40 /* FIXME: there should be way to detect this */
41 clock-frequency = <880000000>;
46 compatible = "fixed-clock";
48 /* FIXME: there should be way to detect this */
49 clock-frequency = <50000000>;
54 palmbus: palmbus@1E000000 {
55 compatible = "palmbus";
56 reg = <0x1E000000 0x100000>;
57 ranges = <0x0 0x1E000000 0x0FFFFF>;
63 compatible = "mtk,mt7621-sysc";
68 compatible = "mediatek,mt7621-wdt";
76 compatible = "mtk,mt7621-gpio";
81 compatible = "mtk,mt7621-gpio-bank";
88 compatible = "mtk,mt7621-gpio-bank";
95 compatible = "mtk,mt7621-gpio-bank";
102 compatible = "mediatek,mt7621-i2c";
105 clocks = <&sysclock>;
107 resets = <&rstctrl 16>;
110 #address-cells = <1>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&i2c_pins>;
120 compatible = "mediatek,mt7621-i2s";
123 clocks = <&sysclock>;
125 resets = <&rstctrl 17>;
128 interrupt-parent = <&gic>;
129 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
136 dma-names = "tx", "rx";
141 systick: systick@d00 {
142 compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
145 resets = <&rstctrl 28>;
146 reset-names = "intc";
148 interrupt-parent = <&gic>;
149 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
153 compatible = "mtk,mt7621-memc";
158 compatible = "mtk,mt7621-cpc";
159 reg = <0x1fbf0000 0x8000>;
163 compatible = "mtk,mt7621-mc";
164 reg = <0x1fbf8000 0x8000>;
167 uartlite: uartlite@c00 {
168 compatible = "ns16550a";
171 clocks = <&sysclock>;
172 clock-frequency = <50000000>;
174 interrupt-parent = <&gic>;
175 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
185 compatible = "ralink,mt7621-spi";
188 clocks = <&sysclock>;
190 resets = <&rstctrl 18>;
193 #address-cells = <1>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&spi_pins>;
201 compatible = "ralink,rt3883-gdma";
202 reg = <0x2800 0x800>;
204 resets = <&rstctrl 14>;
207 interrupt-parent = <&gic>;
208 interrupts = <0 13 4>;
211 #dma-channels = <16>;
212 #dma-requests = <16>;
218 compatible = "mediatek,mt7621-hsdma";
219 reg = <0x7000 0x1000>;
221 resets = <&rstctrl 5>;
222 reset-names = "hsdma";
224 interrupt-parent = <&gic>;
225 interrupts = <0 11 4>;
236 compatible = "ralink,rt2880-pinmux";
237 pinctrl-names = "default";
238 pinctrl-0 = <&state_default>;
240 state_default: pinctrl0 {
245 ralink,group = "i2c";
246 ralink,function = "i2c";
252 ralink,group = "spi";
253 ralink,function = "spi";
259 ralink,group = "uart1";
260 ralink,function = "uart1";
266 ralink,group = "uart2";
267 ralink,function = "uart2";
273 ralink,group = "uart3";
274 ralink,function = "uart3";
278 rgmii1_pins: rgmii1 {
280 ralink,group = "rgmii1";
281 ralink,function = "rgmii1";
285 rgmii2_pins: rgmii2 {
287 ralink,group = "rgmii2";
288 ralink,function = "rgmii2";
294 ralink,group = "mdio";
295 ralink,function = "mdio";
301 ralink,group = "pcie";
302 ralink,function = "pcie rst";
308 ralink,group = "spi";
309 ralink,function = "nand1";
313 ralink,group = "sdhci";
314 ralink,function = "nand2";
320 ralink,group = "sdhci";
321 ralink,function = "sdhci";
327 compatible = "ralink,rt2880-reset";
332 compatible = "ralink,rt2880-clock";
336 sdhci: sdhci@1E130000 {
339 compatible = "ralink,mt7620-sdhci";
340 reg = <0x1E130000 0x4000>;
342 interrupt-parent = <&gic>;
343 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
346 xhci: xhci@1E1C0000 {
349 compatible = "mediatek,mt8173-xhci";
350 reg = <0x1e1c0000 0x1000
352 reg-names = "mac", "ippc";
354 clocks = <&sysclock>;
355 clock-names = "sys_ck";
357 interrupt-parent = <&gic>;
358 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
361 gic: interrupt-controller@1fbc0000 {
362 compatible = "mti,gic";
363 reg = <0x1fbc0000 0x2000>;
365 interrupt-controller;
366 #interrupt-cells = <3>;
368 mti,reserved-cpu-vectors = <7>;
371 compatible = "mti,gic-timer";
372 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
373 clocks = <&cpuclock>;
377 nand: nand@1e003000 {
380 compatible = "mtk,mt7621-nand";
382 reg = <0x1e003000 0x800
386 ethernet: ethernet@1e100000 {
387 compatible = "mediatek,mt7621-eth";
388 reg = <0x1e100000 0x10000>;
390 #address-cells = <1>;
393 resets = <&rstctrl 6 &rstctrl 23>;
394 reset-names = "fe", "eth";
396 interrupt-parent = <&gic>;
397 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
399 mediatek,switch = <&gsw>;
402 #address-cells = <1>;
405 phy1f: ethernet-phy@1f {
412 compatible = "mediatek,mt7623-hnat";
417 resets = <&rstctrl 0>;
418 reset-names = "mtketh";
423 compatible = "mediatek,mt7621-gsw";
424 reg = <0x1e110000 0x8000>;
425 interrupt-parent = <&gic>;
426 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
429 pcie: pcie@1e140000 {
430 compatible = "mediatek,mt7621-pci";
431 reg = <0x1e140000 0x100
434 #address-cells = <3>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&pcie_pins>;
444 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
445 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
448 interrupt-parent = <&gic>;
449 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
450 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
451 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
455 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
456 reset-names = "pcie0", "pcie1", "pcie2";
457 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
458 clock-names = "pcie0", "pcie1", "pcie2";
461 reg = <0x0000 0 0 0 0>;
463 #address-cells = <3>;
470 reg = <0x0800 0 0 0 0>;
472 #address-cells = <3>;
479 reg = <0x1000 0 0 0 0>;
481 #address-cells = <3>;