treewide: convert mtd-mac-address-increment* to generic implementation
[openwrt/staging/chunkeey.git] / target / linux / ramips / dts / mt7621_ubnt_edgerouter-x.dtsi
1 #include "mt7621.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5
6 / {
7 aliases {
8 label-mac-device = &gmac0;
9 };
10
11 keys {
12 compatible = "gpio-keys";
13
14 reset {
15 label = "reset";
16 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
17 linux,code = <KEY_RESTART>;
18 };
19 };
20 };
21
22 &gmac0 {
23 mtd-mac-address = <&factory 0x22>;
24 label = "dsa";
25 };
26
27 &switch0 {
28 ports {
29 port@0 {
30 status = "okay";
31 label = "eth0";
32 };
33
34 port@1 {
35 status = "okay";
36 label = "eth1";
37 mtd-mac-address = <&factory 0x22>;
38 mac-address-increment = <1>;
39 };
40
41 port@2 {
42 status = "okay";
43 label = "eth2";
44 mtd-mac-address = <&factory 0x22>;
45 mac-address-increment = <2>;
46 };
47
48 port@3 {
49 status = "okay";
50 label = "eth3";
51 mtd-mac-address = <&factory 0x22>;
52 mac-address-increment = <3>;
53 };
54
55 port@4 {
56 status = "okay";
57 label = "eth4";
58 mtd-mac-address = <&factory 0x22>;
59 mac-address-increment = <4>;
60 };
61 };
62 };
63
64 &nand {
65 status = "okay";
66
67 partitions {
68 compatible = "fixed-partitions";
69 #address-cells = <1>;
70 #size-cells = <1>;
71
72 partition@0 {
73 label = "u-boot";
74 reg = <0x0 0x80000>;
75 read-only;
76 };
77
78 partition@80000 {
79 label = "u-boot-env";
80 reg = <0x80000 0x60000>;
81 read-only;
82 };
83
84 factory: partition@e0000 {
85 label = "factory";
86 reg = <0xe0000 0x60000>;
87 };
88
89 partition@140000 {
90 label = "kernel1";
91 reg = <0x140000 0x300000>;
92 };
93
94 partition@440000 {
95 label = "kernel2";
96 reg = <0x440000 0x300000>;
97 };
98
99 partition@740000 {
100 label = "ubi";
101 reg = <0x740000 0xf7c0000>;
102 };
103 };
104 };
105
106 &state_default {
107 gpio {
108 groups = "uart2", "uart3", "pcie", "rgmii2", "jtag";
109 function = "gpio";
110 };
111 };
112
113 &spi0 {
114 /*
115 * This board has 2Mb spi flash soldered in and visible
116 * from manufacturer's firmware.
117 * But this SoC shares spi and nand pins,
118 * and current driver doesn't handle this sharing well
119 */
120 status = "disabled";
121
122 flash@1 {
123 compatible = "jedec,spi-nor";
124 reg = <1>;
125 spi-max-frequency = <10000000>;
126
127 partitions {
128 compatible = "fixed-partitions";
129 #address-cells = <1>;
130 #size-cells = <1>;
131
132 partition@0 {
133 label = "spi";
134 reg = <0x0 0x200000>;
135 read-only;
136 };
137 };
138 };
139 };
140
141 &xhci {
142 status = "disabled";
143 };