ramips: gl-mt1300: downclock SPI to 50MHz
[openwrt/staging/stintel.git] / target / linux / ramips / dts / mt7621_youku_yk-l2.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2
3 #include "mt7621.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "youku,yk-l2", "mediatek,mt7621-soc";
10 model = "Youku YK-L2";
11
12 aliases {
13 led-boot = &led_power;
14 led-failsafe = &led_power;
15 led-running = &led_power;
16 led-upgrade = &led_wps;
17 };
18
19 chosen {
20 bootargs = "console=ttyS0,115200";
21 };
22
23 leds {
24 compatible = "gpio-leds";
25
26 led_power: power {
27 label = "blue:power";
28 gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
29 default-state = "on";
30 };
31
32 led_wps: wps {
33 label = "blue:wps";
34 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
35 };
36
37 usb {
38 label = "blue:usb";
39 gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
40 trigger-sources = <&xhci_ehci_port1>, <&ehci_port2>;
41 linux,default-trigger = "usbport";
42 };
43 };
44
45 keys {
46 compatible = "gpio-keys";
47
48 reset {
49 label = "reset";
50 gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
51 linux,code = <KEY_RESTART>;
52 };
53
54 wps {
55 label = "wps";
56 gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
57 linux,code = <KEY_WPS_BUTTON>;
58 };
59 };
60 };
61
62 &sdhci {
63 status = "okay";
64 };
65
66 &spi0 {
67 status = "okay";
68
69 flash@0 {
70 compatible = "jedec,spi-nor";
71 reg = <0>;
72 spi-max-frequency = <10000000>;
73
74 partitions {
75 compatible = "fixed-partitions";
76 #address-cells = <1>;
77 #size-cells = <1>;
78
79 partition@0 {
80 label = "u-boot";
81 reg = <0x0 0x30000>;
82 read-only;
83 };
84
85 partition@30000 {
86 label = "u-boot-env";
87 reg = <0x30000 0x10000>;
88 read-only;
89 };
90
91 factory: partition@40000 {
92 label = "factory";
93 reg = <0x40000 0x10000>;
94 read-only;
95 };
96
97 partition@50000 {
98 compatible = "openwrt,uimage", "denx,uimage";
99 label = "firmware";
100 openwrt,ih-magic = <0x12291000>;
101 reg = <0x50000 0xfb0000>;
102 };
103 };
104 };
105 };
106
107 &pcie {
108 status = "okay";
109 };
110
111 &pcie0 {
112 wifi@0,0 {
113 compatible = "pci14c3,7603";
114 reg = <0x0000 0 0 0 0>;
115 mediatek,mtd-eeprom = <&factory 0x0000>;
116 ieee80211-freq-limit = <2400000 2500000>;
117 led {
118 led-active-low;
119 };
120 };
121 };
122
123 &pcie1 {
124 wifi@0,0 {
125 compatible = "pci14c3,7662";
126 reg = <0x0000 0 0 0 0>;
127 mediatek,mtd-eeprom = <&factory 0x8000>;
128 ieee80211-freq-limit = <5000000 6000000>;
129 led {
130 led-sources = <2>;
131 led-active-low;
132 };
133 };
134 };
135
136 &gmac0 {
137 nvmem-cells = <&macaddr_factory_e000>;
138 nvmem-cell-names = "mac-address";
139 };
140
141 &gmac1 {
142 status = "okay";
143 label = "wan";
144 phy-handle = <&ethphy4>;
145
146 nvmem-cells = <&macaddr_factory_e006>;
147 nvmem-cell-names = "mac-address";
148 };
149
150 &mdio {
151 ethphy4: ethernet-phy@4 {
152 reg = <4>;
153 };
154 };
155
156 &switch0 {
157 ports {
158 port@0 {
159 status = "okay";
160 label = "lan1";
161 };
162
163 port@1 {
164 status = "okay";
165 label = "lan2";
166 };
167
168 port@2 {
169 status = "okay";
170 label = "lan3";
171 };
172
173 port@3 {
174 status = "okay";
175 label = "lan4";
176 };
177 };
178 };
179
180 &state_default {
181 gpio {
182 groups = "jtag", "wdt";
183 function = "gpio";
184 };
185 };
186
187 &factory {
188 compatible = "nvmem-cells";
189 #address-cells = <1>;
190 #size-cells = <1>;
191
192 macaddr_factory_e000: macaddr@e000 {
193 reg = <0xe000 0x6>;
194 };
195
196 macaddr_factory_e006: macaddr@e006 {
197 reg = <0xe006 0x6>;
198 };
199 };