target/linux/ramips/dts/mt7621_zbtlink_zbt-wg1608.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "mt7621.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7 #include <dt-bindings/leds/common.h>
   8
   9 / {
  10         compatible = "zbtlink,zbt-wg1608", "mediatek,mt7621-soc";
  11
  12         aliases {
  13                 led-boot = &led_internet;
  14                 led-failsafe = &led_internet;
  15                 led-running = &led_internet;
  16                 led-upgrade = &led_internet;
  17                 label-mac-device = &gmac0;
  18         };
  19
  20         chosen {
  21                 bootargs = "console=ttyS0,115200";
  22         };
  23
  24         keys {
  25                 compatible = "gpio-keys";
  26
  27                 reset {
  28                         label = "reset";
  29                         gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
  30                         linux,code = <KEY_RESTART>;
  31                 };
  32         };
  33
  34         leds {
  35                 compatible = "gpio-leds";
  36
  37                 led_internet: internet {
  38                         label = "green:internet";
  39                         gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
  40                 };
  41
  42                 wwan {
  43                         label = "green:wwan";
  44                         gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
  45                         linux,default-trigger = "usbport";
  46                         trigger-sources = <&hub_port2>;
  47                 };
  48
  49                 wifi5g {
  50                         label = "green:wifi5g";
  51                         gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
  52                         linux,default-trigger = "phy1tpt";
  53                 };
  54         };
  55 };
  56
  57 &sdhci {
  58         status = "okay";
  59 };
  60
  61 &spi0 {
  62         status = "okay";
  63
  64         flash0: flash@0 {
  65                 compatible = "jedec,spi-nor";
  66                 reg = <0>;
  67                 spi-max-frequency = <50000000>;
  68
  69                 partitions {
  70                         compatible = "fixed-partitions";
  71                         #address-cells = <1>;
  72                         #size-cells = <1>;
  73
  74                         partition@0 {
  75                                 label = "u-boot";
  76                                 reg = <0x0 0x30000>;
  77                                 read-only;
  78                         };
  79
  80                         partition@30000 {
  81                                 label = "u-boot-env";
  82                                 reg = <0x30000 0x10000>;
  83                                 read-only;
  84                         };
  85
  86                         factory: partition@40000 {
  87                                 compatible = "nvmem-cells";
  88                                 label = "factory";
  89                                 reg = <0x40000 0x10000>;
  90                                 #address-cells = <1>;
  91                                 #size-cells = <1>;
  92                                 read-only;
  93
  94                                 eeprom_factory_0: eeprom@0 {
  95                                         reg = <0x0 0x400>;
  96                                 };
  97
  98                                 macaddr_factory_e000: macaddr@e000 {
  99                                         reg = <0xe000 0x6>;
 100                                 };
 101
 102                                 macaddr_factory_e006: macaddr@e006 {
 103                                         reg = <0xe006 0x6>;
 104                                 };
 105
 106                         };
 107
 108                         firmware: partition@50000 {
 109                                 compatible = "denx,uimage";
 110                                 label = "firmware";
 111                         };
 112                 };
 113         };
 114 };
 115
 116 &pcie {
 117         status = "okay";
 118 };
 119
 120 &pcie0 {
 121         wifi@0,0 {
 122                 compatible = "mediatek,mt76";
 123                 reg = <0x0000 0 0 0 0>;
 124                 nvmem-cells = <&eeprom_factory_0>;
 125                 nvmem-cell-names = "eeprom";
 126         };
 127 };
 128
 129 &pcie1 {
 130         wifi@0,0 {
 131                 compatible = "mediatek,mt76";
 132                 reg = <0x0000 0 0 0 0>;
 133                 mediatek,mtd-eeprom = <&factory 0x8000>;
 134                 ieee80211-freq-limit = <5000000 6000000>;
 135         };
 136 };
 137
 138 &gmac0 {
 139         nvmem-cells = <&macaddr_factory_e000>;
 140         nvmem-cell-names = "mac-address";
 141 };
 142
 143 &gmac1 {
 144         status = "okay";
 145         label = "wan";
 146         phy-handle = <&ethphy4>;
 147
 148         nvmem-cells = <&macaddr_factory_e006>;
 149         nvmem-cell-names = "mac-address";
 150 };
 151
 152 &mdio {
 153         ethphy4: ethernet-phy@4 {
 154                 reg = <4>;
 155         };
 156 };
 157
 158 &switch0 {
 159         ports {
 160                 port@0 {
 161                         status = "okay";
 162                         label = "lan1";
 163                 };
 164
 165                 port@1 {
 166                         status = "okay";
 167                         label = "lan2";
 168                 };
 169
 170                 port@2 {
 171                         status = "okay";
 172                         label = "lan3";
 173                 };
 174
 175                 port@3 {
 176                         status = "okay";
 177                         label = "lan4";
 178                 };
 179         };
 180 };
 181
 182 &state_default {
 183         gpio {
 184                 groups = "wdt", "uart2", "jtag";
 185                 function = "gpio";
 186         };
 187 };
 188
 189 &xhci_ehci_port1 {
 190         #address-cells = <1>;
 191         #size-cells = <0>;
 192
 193         hub_port2: port@2 {
 194                 reg = <2>;
 195                 #trigger-source-cells = <0>;
 196         };
 197
 198         port@4 {
 199                 reg = <4>;
 200                 #trigger-source-cells = <0>;
 201         };
 202 };
 203