ramips: add proper system clock and reset driver support for legacy SoCs
[openwrt/staging/stintel.git] / target / linux / ramips / dts / rt3352.dtsi
1 /dts-v1/;
2
3 / {
4 #address-cells = <1>;
5 #size-cells = <1>;
6 compatible = "ralink,rt3352-soc";
7
8 aliases {
9 spi0 = &spi0;
10 spi1 = &spi1;
11 serial0 = &uartlite;
12 };
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 compatible = "mips,mips24KEc";
20 reg = <0>;
21 };
22 };
23
24 chosen {
25 bootargs = "console=ttyS0,57600";
26 };
27
28 cpuintc: cpuintc {
29 #address-cells = <0>;
30 #interrupt-cells = <1>;
31 interrupt-controller;
32 compatible = "mti,cpu-interrupt-controller";
33 };
34
35 palmbus: palmbus@10000000 {
36 compatible = "palmbus";
37 reg = <0x10000000 0x200000>;
38 ranges = <0x0 0x10000000 0x1FFFFF>;
39
40 #address-cells = <1>;
41 #size-cells = <1>;
42
43 sysc: syscon@0 {
44 compatible = "ralink,rt3352-sysc", "syscon";
45 reg = <0x0 0x100>;
46 #clock-cells = <1>;
47 #reset-cells = <1>;
48 };
49
50 timer: timer@100 {
51 compatible = "ralink,rt3352-timer", "ralink,rt2880-timer";
52 reg = <0x100 0x20>;
53
54 clocks = <&sysc 4>;
55
56 interrupt-parent = <&intc>;
57 interrupts = <1>;
58 };
59
60 watchdog: watchdog@120 {
61 compatible = "ralink,rt3352-wdt", "ralink,rt2880-wdt";
62 reg = <0x120 0x10>;
63
64 clocks = <&sysc 5>;
65
66 resets = <&sysc 8>;
67 reset-names = "wdt";
68
69 interrupt-parent = <&intc>;
70 interrupts = <1>;
71 };
72
73 intc: intc@200 {
74 compatible = "ralink,rt3352-intc", "ralink,rt2880-intc";
75 reg = <0x200 0x100>;
76
77 interrupt-controller;
78 #interrupt-cells = <1>;
79
80 interrupt-parent = <&cpuintc>;
81 interrupts = <2>;
82 };
83
84 memc: memc@300 {
85 compatible = "ralink,rt3352-memc", "ralink,rt3050-memc";
86 reg = <0x300 0x100>;
87
88 resets = <&sysc 20>;
89 reset-names = "mc";
90
91 interrupt-parent = <&intc>;
92 interrupts = <3>;
93 };
94
95 uart: uart@500 {
96 compatible = "ralink,rt3352-uart", "ralink,rt2880-uart", "ns16550a";
97 reg = <0x500 0x100>;
98
99 clocks = <&sysc 6>;
100
101 resets = <&sysc 12>;
102
103 interrupt-parent = <&intc>;
104 interrupts = <5>;
105
106 reg-shift = <2>;
107
108 status = "disabled";
109 };
110
111 gpio0: gpio@600 {
112 compatible = "ralink,rt3352-gpio", "ralink,rt2880-gpio";
113 reg = <0x600 0x34>;
114
115 gpio-controller;
116 #gpio-cells = <2>;
117
118 ngpios = <24>;
119 ralink,gpio-base = <0>;
120 ralink,register-map = [ 00 04 08 0c
121 20 24 28 2c
122 30 34 ];
123 resets = <&sysc 13>;
124 reset-names = "pio";
125
126 interrupt-parent = <&intc>;
127 interrupts = <6>;
128 };
129
130 gpio1: gpio@638 {
131 compatible = "ralink,rt3352-gpio", "ralink,rt2880-gpio";
132 reg = <0x638 0x24>;
133
134 gpio-controller;
135 #gpio-cells = <2>;
136
137 ngpios = <16>;
138 ralink,gpio-base = <24>;
139 ralink,register-map = [ 00 04 08 0c
140 10 14 18 1c
141 20 24 ];
142
143 status = "disabled";
144 };
145
146 gpio2: gpio@660 {
147 compatible = "ralink,rt3352-gpio", "ralink,rt2880-gpio";
148 reg = <0x660 0x24>;
149
150 gpio-controller;
151 #gpio-cells = <2>;
152
153 ngpios = <6>;
154 ralink,gpio-base = <40>;
155 ralink,register-map = [ 00 04 08 0c
156 10 14 18 1c
157 20 24 ];
158
159 status = "disabled";
160 };
161
162 i2c@900 {
163 compatible = "ralink,rt2880-i2c";
164 reg = <0x900 0x100>;
165
166 clocks = <&sysc 7>;
167
168 resets = <&sysc 16>;
169 reset-names = "i2c";
170
171 #address-cells = <1>;
172 #size-cells = <0>;
173
174 status = "disabled";
175
176 pinctrl-names = "default";
177 pinctrl-0 = <&i2c_pins>;
178 };
179
180 i2s@a00 {
181 compatible = "ralink,rt3352-i2s";
182 reg = <0xa00 0x100>;
183
184 clocks = <&sysc 8>;
185
186 resets = <&sysc 17>;
187 reset-names = "i2s";
188
189 interrupt-parent = <&intc>;
190 interrupts = <10>;
191
192 txdma-req = <2>;
193 rxdma-req = <3>;
194
195 dmas = <&gdma 4>,
196 <&gdma 6>;
197 dma-names = "tx", "rx";
198
199 status = "disabled";
200 };
201
202 spi0: spi@b00 {
203 compatible = "ralink,rt3352-spi", "ralink,rt2880-spi";
204 reg = <0xb00 0x40>;
205 #address-cells = <1>;
206 #size-cells = <0>;
207
208 clocks = <&sysc 9>;
209
210 resets = <&sysc 18>;
211 reset-names = "spi";
212
213 pinctrl-names = "default";
214 pinctrl-0 = <&spi_pins>;
215
216 status = "disabled";
217 };
218
219 spi1: spi@b40 {
220 compatible = "ralink,rt3352-spi", "ralink,rt2880-spi";
221 reg = <0xb40 0x60>;
222 #address-cells = <1>;
223 #size-cells = <0>;
224
225 resets = <&sysc 18>;
226 reset-names = "spi";
227
228 pinctrl-names = "default";
229 pinctrl-0 = <&spi_cs1>;
230
231 status = "disabled";
232 };
233
234 uartlite: uartlite@c00 {
235 compatible = "ralink,rt3352-uart", "ralink,rt2880-uart", "ns16550a";
236 reg = <0xc00 0x100>;
237
238 clocks = <&sysc 11>;
239
240 resets = <&sysc 19>;
241
242 interrupt-parent = <&intc>;
243 interrupts = <12>;
244
245 reg-shift = <2>;
246
247 pinctrl-names = "default";
248 pinctrl-0 = <&uartlite_pins>;
249 };
250
251 gdma: gdma@2800 {
252 compatible = "ralink,rt3883-gdma";
253 reg = <0x2800 0x800>;
254
255 resets = <&sysc 14>;
256 reset-names = "dma";
257
258 interrupt-parent = <&intc>;
259 interrupts = <7>;
260
261 #dma-cells = <1>;
262 #dma-channels = <16>;
263 #dma-requests = <16>;
264
265 status = "disabled";
266 };
267 };
268
269 pinctrl: pinctrl {
270 compatible = "ralink,rt2880-pinmux";
271
272 pinctrl-names = "default";
273 pinctrl-0 = <&state_default>;
274
275 state_default: pinctrl0 {
276 };
277
278 i2c_pins: i2c_pins {
279 i2c_pins {
280 groups = "i2c";
281 function = "i2c";
282 };
283 };
284
285 mdio_pins: mdio {
286 mdio {
287 groups = "mdio";
288 function = "mdio";
289 };
290 };
291
292 rgmii_pins: rgmii {
293 rgmii {
294 groups = "rgmii";
295 function = "rgmii";
296 };
297 };
298
299 spi_pins: spi_pins {
300 spi_pins {
301 groups = "spi";
302 function = "spi";
303 };
304 };
305
306 spi_cs1: spi1 {
307 spi1 {
308 groups = "spi_cs1";
309 function = "spi_cs1";
310 };
311 };
312
313 uartlite_pins: uartlite {
314 uart {
315 groups = "uartlite";
316 function = "uartlite";
317 };
318 };
319 };
320
321 ethernet: ethernet@10100000 {
322 compatible = "ralink,rt3352-eth", "ralink,rt3050-eth";
323 reg = <0x10100000 0x10000>;
324
325 clocks = <&sysc 12>;
326
327 resets = <&sysc 21>;
328 reset-names = "fe";
329
330 interrupt-parent = <&cpuintc>;
331 interrupts = <5>;
332
333 mediatek,switch = <&esw>;
334 };
335
336 esw: esw@10110000 {
337 compatible = "ralink,rt3352-esw", "ralink,rt3050-esw";
338 reg = <0x10110000 0x8000>;
339
340 resets = <&sysc 23>, <&sysc 24>;
341 reset-names = "esw", "ephy";
342
343 interrupt-parent = <&intc>;
344 interrupts = <17>;
345 };
346
347 usbphy: usbphy {
348 compatible = "ralink,rt3352-usbphy";
349 #phy-cells = <0>;
350
351 ralink,sysctl = <&sysc>;
352 resets = <&sysc 22>, <&sysc 25>;
353 reset-names = "host", "device";
354 };
355
356 wmac: wmac@10180000 {
357 compatible = "ralink,rt3352-wmac", "ralink,rt2880-wmac";
358 reg = <0x10180000 0x40000>;
359
360 clocks = <&sysc 13>;
361
362 interrupt-parent = <&cpuintc>;
363 interrupts = <6>;
364
365 ralink,eeprom = "soc_wmac.eeprom";
366 };
367
368 ehci: ehci@101c0000 {
369 #address-cells = <1>;
370 #size-cells = <0>;
371 compatible = "generic-ehci";
372 reg = <0x101c0000 0x1000>;
373
374 phys = <&usbphy>;
375 phy-names = "usb";
376
377 interrupt-parent = <&intc>;
378 interrupts = <18>;
379
380 status = "disabled";
381
382 ehci_port1: port@1 {
383 reg = <1>;
384 #trigger-source-cells = <0>;
385 };
386 };
387
388 ohci: ohci@101c1000 {
389 #address-cells = <1>;
390 #size-cells = <0>;
391 compatible = "generic-ohci";
392 reg = <0x101c1000 0x1000>;
393
394 phys = <&usbphy>;
395 phy-names = "usb";
396
397 interrupt-parent = <&intc>;
398 interrupts = <18>;
399
400 status = "disabled";
401
402 ohci_port1: port@1 {
403 reg = <1>;
404 #trigger-source-cells = <0>;
405 };
406 };
407 };