2 * Ralink RT305x SoC specific definitions
4 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
6 * Parts of this file are based on Ralink's 2.6.21 BSP
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
16 #include <linux/init.h>
19 enum rt305x_soc_type
{
20 RT305X_SOC_UNKNOWN
= 0,
28 extern enum rt305x_soc_type rt305x_soc
;
30 static inline int soc_is_rt3050(void)
32 return rt305x_soc
== RT305X_SOC_RT3050
;
35 static inline int soc_is_rt3052(void)
37 return rt305x_soc
== RT305X_SOC_RT3052
;
40 static inline int soc_is_rt305x(void)
42 return soc_is_rt3050() || soc_is_rt3052();
45 static inline int soc_is_rt3350(void)
47 return rt305x_soc
== RT305X_SOC_RT3350
;
50 static inline int soc_is_rt3352(void)
52 return rt305x_soc
== RT305X_SOC_RT3352
;
55 static inline int soc_is_rt5350(void)
57 return rt305x_soc
== RT305X_SOC_RT5350
;
60 #define RT305X_MEM_SIZE_MIN (2 * 1024 * 1024)
61 #define RT305X_MEM_SIZE_MAX (64 * 1024 * 1024)
63 #define RT3352_MEM_SIZE_MIN (2 * 1024 * 1024)
64 #define RT3352_MEM_SIZE_MAX (256 * 1024 * 1024)
66 #define RT305X_CPU_IRQ_BASE 0
67 #define RT305X_INTC_IRQ_BASE 8
68 #define RT305X_INTC_IRQ_COUNT 32
69 #define RT305X_GPIO_IRQ_BASE 40
71 #define RT305X_CPU_IRQ_INTC (RT305X_CPU_IRQ_BASE + 2)
72 #define RT305X_CPU_IRQ_FE (RT305X_CPU_IRQ_BASE + 5)
73 #define RT305X_CPU_IRQ_WNIC (RT305X_CPU_IRQ_BASE + 6)
74 #define RT305X_CPU_IRQ_COUNTER (RT305X_CPU_IRQ_BASE + 7)
76 #define RT305X_INTC_IRQ_SYSCTL (RT305X_INTC_IRQ_BASE + 0)
77 #define RT305X_INTC_IRQ_TIMER0 (RT305X_INTC_IRQ_BASE + 1)
78 #define RT305X_INTC_IRQ_TIMER1 (RT305X_INTC_IRQ_BASE + 2)
79 #define RT305X_INTC_IRQ_IA (RT305X_INTC_IRQ_BASE + 3)
80 #define RT305X_INTC_IRQ_PCM (RT305X_INTC_IRQ_BASE + 4)
81 #define RT305X_INTC_IRQ_UART0 (RT305X_INTC_IRQ_BASE + 5)
82 #define RT305X_INTC_IRQ_PIO (RT305X_INTC_IRQ_BASE + 6)
83 #define RT305X_INTC_IRQ_DMA (RT305X_INTC_IRQ_BASE + 7)
84 #define RT305X_INTC_IRQ_NAND (RT305X_INTC_IRQ_BASE + 8)
85 #define RT305X_INTC_IRQ_PERFC (RT305X_INTC_IRQ_BASE + 9)
86 #define RT305X_INTC_IRQ_I2S (RT305X_INTC_IRQ_BASE + 10)
87 #define RT305X_INTC_IRQ_UART1 (RT305X_INTC_IRQ_BASE + 12)
88 #define RT305X_INTC_IRQ_ESW (RT305X_INTC_IRQ_BASE + 17)
89 #define RT305X_INTC_IRQ_OTG (RT305X_INTC_IRQ_BASE + 18)
91 extern void __iomem
*rt305x_sysc_base
;
92 extern void __iomem
*rt305x_memc_base
;
94 static inline void rt305x_sysc_wr(u32 val
, unsigned reg
)
96 __raw_writel(val
, rt305x_sysc_base
+ reg
);
99 static inline u32
rt305x_sysc_rr(unsigned reg
)
101 return __raw_readl(rt305x_sysc_base
+ reg
);
104 static inline void rt305x_memc_wr(u32 val
, unsigned reg
)
106 __raw_writel(val
, rt305x_memc_base
+ reg
);
109 static inline u32
rt305x_memc_rr(unsigned reg
)
111 return __raw_readl(rt305x_memc_base
+ reg
);
114 #define RT305X_GPIO_I2C_SD 1
115 #define RT305X_GPIO_I2C_SCLK 2
116 #define RT305X_GPIO_SPI_EN 3
117 #define RT305X_GPIO_SPI_CLK 4
118 #define RT305X_GPIO_SPI_DOUT 5
119 #define RT305X_GPIO_SPI_DIN 6
120 /* GPIO 7-14 is shared between UART0, PCM and I2S interfaces */
121 #define RT305X_GPIO_7 7
122 #define RT305X_GPIO_8 8
123 #define RT305X_GPIO_9 9
124 #define RT305X_GPIO_10 10
125 #define RT305X_GPIO_11 11
126 #define RT305X_GPIO_12 12
127 #define RT305X_GPIO_13 13
128 #define RT305X_GPIO_14 14
129 #define RT305X_GPIO_UART1_TXD 15
130 #define RT305X_GPIO_UART1_RXD 16
131 #define RT305X_GPIO_JTAG_TDO 17
132 #define RT305X_GPIO_JTAG_TDI 18
133 #define RT305X_GPIO_JTAG_TMS 19
134 #define RT305X_GPIO_JTAG_TCLK 20
135 #define RT305X_GPIO_JTAG_TRST_N 21
136 #define RT305X_GPIO_MDIO_MDC 22
137 #define RT305X_GPIO_MDIO_MDIO 23
138 #define RT305X_GPIO_SDRAM_MD16 24
139 #define RT305X_GPIO_SDRAM_MD17 25
140 #define RT305X_GPIO_SDRAM_MD18 26
141 #define RT305X_GPIO_SDRAM_MD19 27
142 #define RT305X_GPIO_SDRAM_MD20 28
143 #define RT305X_GPIO_SDRAM_MD21 29
144 #define RT305X_GPIO_SDRAM_MD22 30
145 #define RT305X_GPIO_SDRAM_MD23 31
146 #define RT305X_GPIO_SDRAM_MD24 32
147 #define RT305X_GPIO_SDRAM_MD25 33
148 #define RT305X_GPIO_SDRAM_MD26 34
149 #define RT305X_GPIO_SDRAM_MD27 35
150 #define RT305X_GPIO_SDRAM_MD28 36
151 #define RT305X_GPIO_SDRAM_MD29 37
152 #define RT305X_GPIO_SDRAM_MD30 38
153 #define RT305X_GPIO_SDRAM_MD31 39
154 #define RT305X_GPIO_GE0_TXD0 40
155 #define RT305X_GPIO_GE0_TXD1 41
156 #define RT305X_GPIO_GE0_TXD2 42
157 #define RT305X_GPIO_GE0_TXD3 43
158 #define RT305X_GPIO_GE0_TXEN 44
159 #define RT305X_GPIO_GE0_TXCLK 45
160 #define RT305X_GPIO_GE0_RXD0 46
161 #define RT305X_GPIO_GE0_RXD1 47
162 #define RT305X_GPIO_GE0_RXD2 48
163 #define RT305X_GPIO_GE0_RXD3 49
164 #define RT305X_GPIO_GE0_RXDV 50
165 #define RT305X_GPIO_GE0_RXCLK 51
167 void rt305x_gpio_init(u32 mode
);
169 #endif /* _RT305X_H_ */