target/linux/ramips/files/arch/mips/pci/pci-rt288x.c

   1 #include <linux/types.h>
   2 #include <linux/pci.h>
   3 #include <linux/io.h>
   4 #include <linux/init.h>
   5
   6 #include <asm/mach-ralink/rt288x.h>
   7 #include <asm/mach-ralink/rt288x_pci.h>
   8
   9 extern int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
  10 extern int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
  11
  12 struct pci_ops rt2880_pci_ops = {
  13         .read =  pci_config_read,
  14         .write = pci_config_write,
  15 };
  16
  17 static struct resource pci_io_resource = {
  18         .name = "pci MEM space",
  19         .start = 0x20000000,
  20         .end = 0x2FFFFFFF,
  21         .flags = IORESOURCE_MEM,
  22 };
  23
  24 static struct resource pci_mem_resource = {
  25         .name = "pci IO space",
  26         .start = 0x00460000,
  27         .end = 0x0046FFFF,
  28         .flags = IORESOURCE_IO,
  29 };
  30
  31 struct pci_controller rt2880_controller = {
  32         .pci_ops = &rt2880_pci_ops,
  33         .mem_resource = &pci_io_resource,
  34         .io_resource = &pci_mem_resource,
  35         .mem_offset = 0x00000000UL,
  36         .io_offset = 0x00000000UL,
  37 };
  38
  39 void inline
  40 read_config(unsigned long bus, unsigned long dev, unsigned long func,
  41         unsigned long reg, unsigned long *val)
  42 {
  43         unsigned long address =
  44                 (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000;
  45         writel(address, RT2880_PCI_CONFIG_ADDR);
  46         *val = readl(RT2880_PCI_CONFIG_DATA);
  47 }
  48
  49 void inline
  50 write_config(unsigned long bus, unsigned long dev, unsigned long func,
  51         unsigned long reg, unsigned long val)
  52 {
  53         unsigned long address =
  54                 (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000;
  55         writel(address, RT2880_PCI_CONFIG_ADDR);
  56         writel(val, RT2880_PCI_CONFIG_DATA);
  57 }
  58
  59 int __init
  60 pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  61 {
  62         u16 cmd;
  63         unsigned long val;
  64         int irq = -1;
  65         if (dev->bus->number != 0)
  66                 return 0;
  67
  68         switch(PCI_SLOT(dev->devfn))
  69         {
  70         case 0x00:
  71                 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
  72                 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
  73                 break;
  74         case 0x11:
  75                 irq = RT288X_CPU_IRQ_PCI;
  76                 break;
  77         default:
  78                 printk("%s:%s[%d] trying to alloc unknown pci irq\n", __FILE__, __func__, __LINE__);
  79                 BUG();
  80                 break;
  81         }
  82
  83         pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
  84         pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
  85         pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
  86         cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  87                 PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK | PCI_COMMAND_SERR |
  88                 PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
  89         pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
  90         pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE, dev->irq);
  91         return irq;
  92 }
  93
  94 int
  95 init_rt2880pci(void)
  96 {
  97         unsigned long val = 0;
  98         int i;
  99         writel(0, RT2880_PCI_PCICFG_ADDR);
 100         for(i = 0; i < 0xfffff; i++) {}
 101         writel(0x79, RT2880_PCI_ARBCTL);
 102         writel(0x07FF0001, RT2880_PCI_BAR0SETUP_ADDR);
 103         writel(RT2880_PCI_SLOT1_BASE, RT2880_PCI_MEMBASE);
 104         writel(0x00460000, RT2880_PCI_IOBASE);
 105         writel(0x08000000, RT2880_PCI_IMBASEBAR0_ADDR);
 106         writel(0x08021814, RT2880_PCI_ID);
 107         writel(0x00800001, RT2880_PCI_CLASS);
 108         writel(0x28801814, RT2880_PCI_SUBID);
 109         writel(0x000c0000, RT2880_PCI_PCIMSK_ADDR);
 110         write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
 111         read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
 112         register_pci_controller(&rt2880_controller);
 113         return 0;
 114 }
 115
 116 int
 117 pcibios_plat_dev_init(struct pci_dev *dev)
 118 {
 119         return 0;
 120 }
 121
 122 struct pci_fixup pcibios_fixups[] = {
 123         {0}
 124 };
 125
 126 arch_initcall(init_rt2880pci);