target/linux/ramips/files/arch/mips/pci/pci-rt288x.c

   1 #include <linux/types.h>
   2 #include <linux/pci.h>
   3 #include <linux/kernel.h>
   4 #include <linux/slab.h>
   5 #include <linux/version.h>
   6 #include <asm/pci.h>
   7 #include <asm/io.h>
   8 #include <asm/mach-rt288x/rt288x.h>
   9 #include <asm/mach-rt288x/rt288x_pci.h>
  10 #include <linux/init.h>
  11 #include <linux/mod_devicetable.h>
  12
  13 #ifdef CONFIG_PCI
  14
  15 extern int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
  16 extern int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
  17
  18 struct pci_ops rt2880_pci_ops = {
  19         .read =  pci_config_read,
  20         .write = pci_config_write,
  21 };
  22
  23 static struct resource pci_io_resource = {
  24         .name = "pci MEM space",
  25         .start = 0x20000000,
  26         .end = 0x2FFFFFFF,
  27         .flags = IORESOURCE_MEM,
  28 };
  29
  30 static struct resource pci_mem_resource = {
  31         .name = "pci IO space",
  32         .start = 0x00460000,
  33         .end = 0x0046FFFF,
  34         .flags = IORESOURCE_IO,
  35 };
  36
  37 struct pci_controller rt2880_controller = {
  38         .pci_ops = &rt2880_pci_ops,
  39         .mem_resource = &pci_io_resource,
  40         .io_resource = &pci_mem_resource,
  41         .mem_offset = 0x00000000UL,
  42         .io_offset = 0x00000000UL,
  43 };
  44
  45 void inline
  46 read_config(unsigned long bus, unsigned long dev, unsigned long func,
  47         unsigned long reg, unsigned long *val)
  48 {
  49         unsigned long address =
  50                 (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000;
  51         writel(address, RT2880_PCI_CONFIG_ADDR);
  52         *val = readl(RT2880_PCI_CONFIG_DATA);
  53 }
  54
  55 void inline
  56 write_config(unsigned long bus, unsigned long dev, unsigned long func,
  57         unsigned long reg, unsigned long val)
  58 {
  59         unsigned long address =
  60                 (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000;
  61         writel(address, RT2880_PCI_CONFIG_ADDR);
  62         writel(val, RT2880_PCI_CONFIG_DATA);
  63 }
  64
  65 int __init
  66 pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  67 {
  68         u16 cmd;
  69         unsigned long val;
  70         int irq = -1;
  71         if (dev->bus->number != 0)
  72                 return 0;
  73
  74         switch(PCI_SLOT(dev->devfn))
  75         {
  76         case 0x00:
  77                 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
  78                 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
  79                 break;
  80         case 0x11:
  81                 irq = RT288X_CPU_IRQ_PCI;
  82                 break;
  83         default:
  84                 printk("%s:%s[%d] trying to alloc unknown pci irq\n", __FILE__, __func__, __LINE__);
  85                 BUG();
  86                 break;
  87         }
  88
  89         pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
  90         pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
  91         pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
  92         cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  93                 PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK | PCI_COMMAND_SERR |
  94                 PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
  95         pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
  96         pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE, dev->irq);
  97         return irq;
  98 }
  99
 100 int
 101 init_rt2880pci(void)
 102 {
 103         unsigned long val = 0;
 104         int i;
 105         writel(0, RT2880_PCI_PCICFG_ADDR);
 106         for(i = 0; i < 0xfffff; i++) {}
 107         writel(0x79, RT2880_PCI_ARBCTL);
 108         writel(0x07FF0001, RT2880_PCI_BAR0SETUP_ADDR);
 109         writel(RT2880_PCI_SLOT1_BASE, RT2880_PCI_MEMBASE);
 110         writel(0x00460000, RT2880_PCI_IOBASE);
 111         writel(0x08000000, RT2880_PCI_IMBASEBAR0_ADDR);
 112         writel(0x08021814, RT2880_PCI_ID);
 113         writel(0x00800001, RT2880_PCI_CLASS);
 114         writel(0x28801814, RT2880_PCI_SUBID);
 115         writel(0x000c0000, RT2880_PCI_PCIMSK_ADDR);
 116         write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
 117         read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
 118         register_pci_controller(&rt2880_controller);
 119         return 0;
 120 }
 121
 122 int
 123 pcibios_plat_dev_init(struct pci_dev *dev)
 124 {
 125         return 0;
 126 }
 127
 128 struct pci_fixup pcibios_fixups[] = {
 129         {0}
 130 };
 131
 132 arch_initcall(init_rt2880pci);
 133
 134 #endif