target/linux/ramips/files/arch/mips/ralink/common/gpio.c

   1 /*
   2  * Ralink SoC specific GPIO support
   3  *
   4  * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/io.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/gpio.h>
  15
  16 #include <ralink_soc.h>
  17
  18 #define GPIO0_REG_INT           0x00
  19 #define GPIO0_REG_EDGE          0x04
  20 #define GPIO0_REG_RENA          0x08
  21 #define GPIO0_REG_FENA          0x0c
  22 #define GPIO0_REG_DATA          0x20
  23 #define GPIO0_REG_DIR           0x24
  24 #define GPIO0_REG_POL           0x28
  25 #define GPIO0_REG_SET           0x2c
  26 #define GPIO0_REG_RESET         0x30
  27 #define GPIO0_REG_TOGGLE        0x34
  28
  29 #define GPIO1_REG_INT           0x38
  30 #define GPIO1_REG_EDGE          0x3c
  31 #define GPIO1_REG_RENA          0x40
  32 #define GPIO1_REG_FENA          0x44
  33 #define GPIO1_REG_DATA          0x48
  34 #define GPIO1_REG_DIR           0x4c
  35 #define GPIO1_REG_POL           0x50
  36 #define GPIO1_REG_SET           0x54
  37 #define GPIO1_REG_RESET         0x58
  38 #define GPIO1_REG_TOGGLE        0x5c
  39
  40 #define GPIO2_REG_INT           0x60
  41 #define GPIO2_REG_EDGE          0x64
  42 #define GPIO2_REG_RENA          0x68
  43 #define GPIO2_REG_FENA          0x6c
  44 #define GPIO2_REG_DATA          0x70
  45 #define GPIO2_REG_DIR           0x74
  46 #define GPIO2_REG_POL           0x78
  47 #define GPIO2_REG_SET           0x7c
  48 #define GPIO2_REG_RESET         0x80
  49 #define GPIO2_REG_TOGGLE        0x84
  50
  51 enum ramips_pio_reg {
  52         RAMIPS_GPIO_REG_INT,            /* Interrupt status */
  53         RAMIPS_GPIO_REG_EDGE,
  54         RAMIPS_GPIO_REG_RENA,
  55         RAMIPS_GPIO_REG_FENA,
  56         RAMIPS_GPIO_REG_DATA,
  57         RAMIPS_GPIO_REG_DIR,            /* Direction, 0:in, 1: out */
  58         RAMIPS_GPIO_REG_POL,            /* Polarity, 0: normal, 1: invert */
  59         RAMIPS_GPIO_REG_SET,
  60         RAMIPS_GPIO_REG_RESET,
  61         RAMIPS_GPIO_REG_TOGGLE,
  62         RAMIPS_GPIO_REG_MAX
  63 };
  64
  65 struct ramips_gpio_chip {
  66         struct gpio_chip        chip;
  67         spinlock_t              lock;
  68         u8                      regs[RAMIPS_GPIO_REG_MAX];
  69 };
  70
  71 static void __iomem *ramips_gpio_base;
  72
  73 static inline struct ramips_gpio_chip *to_ramips_gpio(struct gpio_chip *chip)
  74 {
  75         struct ramips_gpio_chip *rg;
  76
  77         rg = container_of(chip, struct ramips_gpio_chip, chip);
  78         return rg;
  79 }
  80
  81 static inline void ramips_gpio_wr(struct ramips_gpio_chip *rg, u8 reg, u32 val)
  82 {
  83         __raw_writel(val, ramips_gpio_base + rg->regs[reg]);
  84 }
  85
  86 static inline u32 ramips_gpio_rr(struct ramips_gpio_chip *rg, u8 reg)
  87 {
  88         return __raw_readl(ramips_gpio_base + rg->regs[reg]);
  89 }
  90
  91 static int ramips_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  92 {
  93         struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
  94         unsigned long flags;
  95         u32 t;
  96
  97         spin_lock_irqsave(&rg->lock, flags);
  98         t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
  99         t &= ~(1 << offset);
 100         ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
 101         spin_unlock_irqrestore(&rg->lock, flags);
 102
 103         return 0;
 104 }
 105
 106 static int ramips_gpio_direction_output(struct gpio_chip *chip,
 107                                         unsigned offset, int value)
 108 {
 109         struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
 110         unsigned long flags;
 111         u32 reg;
 112         u32 t;
 113
 114         reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
 115
 116         spin_lock_irqsave(&rg->lock, flags);
 117         ramips_gpio_wr(rg, reg, 1 << offset);
 118
 119         t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
 120         t |= 1 << offset;
 121         ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
 122         spin_unlock_irqrestore(&rg->lock, flags);
 123
 124         return 0;
 125 }
 126
 127 static void ramips_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 128 {
 129         struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
 130         u32 reg;
 131
 132         reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
 133         ramips_gpio_wr(rg, reg, 1 << offset);
 134 }
 135
 136 static int ramips_gpio_get(struct gpio_chip *chip, unsigned offset)
 137 {
 138         struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
 139         u32 t;
 140
 141         t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DATA);
 142         return !!(t & (1 << offset));
 143 }
 144
 145 static struct ramips_gpio_chip ramips_gpio_chip0 = {
 146         .chip = {
 147                 .label                  = "ramips-gpio0",
 148                 .direction_input        = ramips_gpio_direction_input,
 149                 .direction_output       = ramips_gpio_direction_output,
 150                 .get                    = ramips_gpio_get,
 151                 .set                    = ramips_gpio_set,
 152                 .base                   = 0,
 153                 .ngpio                  = RALINK_SOC_GPIO0_COUNT,
 154         },
 155         .regs = {
 156                 [RAMIPS_GPIO_REG_INT]   = GPIO0_REG_INT,
 157                 [RAMIPS_GPIO_REG_EDGE]  = GPIO0_REG_EDGE,
 158                 [RAMIPS_GPIO_REG_RENA]  = GPIO0_REG_RENA,
 159                 [RAMIPS_GPIO_REG_FENA]  = GPIO0_REG_FENA,
 160                 [RAMIPS_GPIO_REG_DATA]  = GPIO0_REG_DATA,
 161                 [RAMIPS_GPIO_REG_DIR]   = GPIO0_REG_DIR,
 162                 [RAMIPS_GPIO_REG_POL]   = GPIO0_REG_POL,
 163                 [RAMIPS_GPIO_REG_SET]   = GPIO0_REG_SET,
 164                 [RAMIPS_GPIO_REG_RESET] = GPIO0_REG_RESET,
 165                 [RAMIPS_GPIO_REG_TOGGLE] = GPIO0_REG_TOGGLE,
 166         },
 167 };
 168
 169 static struct ramips_gpio_chip ramips_gpio_chip1 = {
 170         .chip = {
 171                 .label                  = "ramips-gpio1",
 172                 .direction_input        = ramips_gpio_direction_input,
 173                 .direction_output       = ramips_gpio_direction_output,
 174                 .get                    = ramips_gpio_get,
 175                 .set                    = ramips_gpio_set,
 176                 .base                   = 32,
 177                 .ngpio                  = RALINK_SOC_GPIO1_COUNT,
 178         },
 179         .regs = {
 180                 [RAMIPS_GPIO_REG_INT]   = GPIO1_REG_INT,
 181                 [RAMIPS_GPIO_REG_EDGE]  = GPIO1_REG_EDGE,
 182                 [RAMIPS_GPIO_REG_RENA]  = GPIO1_REG_RENA,
 183                 [RAMIPS_GPIO_REG_FENA]  = GPIO1_REG_FENA,
 184                 [RAMIPS_GPIO_REG_DATA]  = GPIO1_REG_DATA,
 185                 [RAMIPS_GPIO_REG_DIR]   = GPIO1_REG_DIR,
 186                 [RAMIPS_GPIO_REG_POL]   = GPIO1_REG_POL,
 187                 [RAMIPS_GPIO_REG_SET]   = GPIO1_REG_SET,
 188                 [RAMIPS_GPIO_REG_RESET] = GPIO1_REG_RESET,
 189                 [RAMIPS_GPIO_REG_TOGGLE] = GPIO1_REG_TOGGLE,
 190         },
 191 };
 192
 193 static struct ramips_gpio_chip ramips_gpio_chip2 = {
 194         .chip = {
 195                 .label                  = "ramips-gpio2",
 196                 .direction_input        = ramips_gpio_direction_input,
 197                 .direction_output       = ramips_gpio_direction_output,
 198                 .get                    = ramips_gpio_get,
 199                 .set                    = ramips_gpio_set,
 200                 .base                   = 64,
 201                 .ngpio                  = RALINK_SOC_GPIO2_COUNT,
 202         },
 203         .regs = {
 204                 [RAMIPS_GPIO_REG_INT]   = GPIO2_REG_INT,
 205                 [RAMIPS_GPIO_REG_EDGE]  = GPIO2_REG_EDGE,
 206                 [RAMIPS_GPIO_REG_RENA]  = GPIO2_REG_RENA,
 207                 [RAMIPS_GPIO_REG_FENA]  = GPIO2_REG_FENA,
 208                 [RAMIPS_GPIO_REG_DATA]  = GPIO2_REG_DATA,
 209                 [RAMIPS_GPIO_REG_DIR]   = GPIO2_REG_DIR,
 210                 [RAMIPS_GPIO_REG_POL]   = GPIO2_REG_POL,
 211                 [RAMIPS_GPIO_REG_SET]   = GPIO2_REG_SET,
 212                 [RAMIPS_GPIO_REG_RESET] = GPIO2_REG_RESET,
 213                 [RAMIPS_GPIO_REG_TOGGLE] = GPIO2_REG_TOGGLE,
 214         },
 215 };
 216
 217 static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg)
 218 {
 219         spin_lock_init(&rg->lock);
 220
 221         /* set polarity to low for all lines */
 222         ramips_gpio_wr(rg, RAMIPS_GPIO_REG_POL, 0);
 223
 224         gpiochip_add(&rg->chip);
 225 }
 226
 227 __init int ramips_gpio_init(void)
 228 {
 229         ramips_gpio_base = ioremap_nocache(RALINK_SOC_GPIO_BASE, PAGE_SIZE);
 230
 231         ramips_gpio_chip_add(&ramips_gpio_chip0);
 232         ramips_gpio_chip_add(&ramips_gpio_chip1);
 233         ramips_gpio_chip_add(&ramips_gpio_chip2);
 234
 235         return 0;
 236 }