1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek MT7621 NAND Flash Controller driver
5 * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
7 * Author: Weijie Gao <weijie.gao@mediatek.com>
11 #include <linux/clk.h>
12 #include <linux/init.h>
13 #include <linux/errno.h>
14 #include <linux/sizes.h>
15 #include <linux/iopoll.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/rawnand.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/platform_device.h>
22 #include <asm/addrspace.h>
24 /* NFI core registers */
25 #define NFI_CNFG 0x000
26 #define CNFG_OP_MODE_S 12
27 #define CNFG_OP_MODE_M GENMASK(14, 12)
28 #define CNFG_OP_CUSTOM 6
29 #define CNFG_AUTO_FMT_EN BIT(9)
30 #define CNFG_HW_ECC_EN BIT(8)
31 #define CNFG_BYTE_RW BIT(6)
32 #define CNFG_READ_MODE BIT(1)
34 #define NFI_PAGEFMT 0x004
35 #define PAGEFMT_FDM_ECC_S 12
36 #define PAGEFMT_FDM_ECC_M GENMASK(15, 12)
37 #define PAGEFMT_FDM_S 8
38 #define PAGEFMT_FDM_M GENMASK(11, 8)
39 #define PAGEFMT_SPARE_S 4
40 #define PAGEFMT_SPARE_M GENMASK(5, 4)
41 #define PAGEFMT_PAGE_S 0
42 #define PAGEFMT_PAGE_M GENMASK(1, 0)
45 #define CON_NFI_SEC_S 12
46 #define CON_NFI_SEC_M GENMASK(15, 12)
47 #define CON_NFI_BWR BIT(9)
48 #define CON_NFI_BRD BIT(8)
49 #define CON_NFI_RST BIT(1)
50 #define CON_FIFO_FLUSH BIT(0)
52 #define NFI_ACCCON 0x00c
53 #define ACCCON_POECS_S 28
54 #define ACCCON_POECS_MAX 0x0f
55 #define ACCCON_POECS_DEF 3
56 #define ACCCON_PRECS_S 22
57 #define ACCCON_PRECS_MAX 0x3f
58 #define ACCCON_PRECS_DEF 3
59 #define ACCCON_C2R_S 16
60 #define ACCCON_C2R_MAX 0x3f
61 #define ACCCON_C2R_DEF 7
62 #define ACCCON_W2R_S 12
63 #define ACCCON_W2R_MAX 0x0f
64 #define ACCCON_W2R_DEF 7
66 #define ACCCON_WH_MAX 0x0f
67 #define ACCCON_WH_DEF 15
68 #define ACCCON_WST_S 4
69 #define ACCCON_WST_MAX 0x0f
70 #define ACCCON_WST_DEF 15
71 #define ACCCON_WST_MIN 3
72 #define ACCCON_RLT_S 0
73 #define ACCCON_RLT_MAX 0x0f
74 #define ACCCON_RLT_DEF 15
75 #define ACCCON_RLT_MIN 3
79 #define NFI_ADDRNOB 0x030
80 #define ADDR_ROW_NOB_S 4
81 #define ADDR_ROW_NOB_M GENMASK(6, 4)
82 #define ADDR_COL_NOB_S 0
83 #define ADDR_COL_NOB_M GENMASK(2, 0)
85 #define NFI_COLADDR 0x034
86 #define NFI_ROWADDR 0x038
88 #define NFI_STRDATA 0x040
89 #define STR_DATA BIT(0)
91 #define NFI_CNRNB 0x044
93 #define CB2R_TIME_M GENMASK(7, 4)
94 #define STR_CNRNB BIT(0)
96 #define NFI_DATAW 0x050
97 #define NFI_DATAR 0x054
99 #define NFI_PIO_DIRDY 0x058
100 #define PIO_DIRDY BIT(0)
102 #define NFI_STA 0x060
103 #define STA_NFI_FSM_S 16
104 #define STA_NFI_FSM_M GENMASK(19, 16)
105 #define STA_FSM_CUSTOM_DATA 14
106 #define STA_BUSY BIT(8)
107 #define STA_ADDR BIT(1)
108 #define STA_CMD BIT(0)
110 #define NFI_ADDRCNTR 0x070
111 #define SEC_CNTR_S 12
112 #define SEC_CNTR_M GENMASK(15, 12)
114 #define SEC_ADDR_M GENMASK(9, 0)
116 #define NFI_CSEL 0x090
118 #define CSEL_M GENMASK(1, 0)
120 #define NFI_FDM0L 0x0a0
121 #define NFI_FDML(n) (0x0a0 + ((n) << 3))
123 #define NFI_FDM0M 0x0a4
124 #define NFI_FDMM(n) (0x0a4 + ((n) << 3))
126 #define NFI_MASTER_STA 0x210
127 #define MAS_ADDR GENMASK(11, 9)
128 #define MAS_RD GENMASK(8, 6)
129 #define MAS_WR GENMASK(5, 3)
130 #define MAS_RDDLY GENMASK(2, 0)
132 /* ECC engine registers */
133 #define ECC_ENCCON 0x000
134 #define ENC_EN BIT(0)
136 #define ECC_ENCCNFG 0x004
137 #define ENC_CNFG_MSG_S 16
138 #define ENC_CNFG_MSG_M GENMASK(28, 16)
140 #define ENC_MODE_M GENMASK(5, 4)
141 #define ENC_MODE_NFI 1
143 #define ENC_TNUM_M GENMASK(2, 0)
145 #define ECC_ENCIDLE 0x00c
146 #define ENC_IDLE BIT(0)
148 #define ECC_DECCON 0x100
149 #define DEC_EN BIT(0)
151 #define ECC_DECCNFG 0x104
152 #define DEC_EMPTY_EN BIT(31)
154 #define DEC_CS_M GENMASK(28, 16)
156 #define DEC_CON_M GENMASK(13, 12)
159 #define DEC_MODE_M GENMASK(5, 4)
160 #define DEC_MODE_NFI 1
162 #define DEC_TNUM_M GENMASK(2, 0)
164 #define ECC_DECIDLE 0x10c
165 #define DEC_IDLE BIT(1)
167 #define ECC_DECENUM 0x114
169 #define ERRNUM_M GENMASK(3, 0)
171 #define ECC_DECDONE 0x118
172 #define DEC_DONE7 BIT(7)
173 #define DEC_DONE6 BIT(6)
174 #define DEC_DONE5 BIT(5)
175 #define DEC_DONE4 BIT(4)
176 #define DEC_DONE3 BIT(3)
177 #define DEC_DONE2 BIT(2)
178 #define DEC_DONE1 BIT(1)
179 #define DEC_DONE0 BIT(0)
181 #define ECC_DECEL(n) (0x11c + (n) * 4)
182 #define DEC_EL_ODD_S 16
183 #define DEC_EL_EVEN_S 0
184 #define DEC_EL_M 0x1fff
185 #define DEC_EL_BYTE_POS_S 3
186 #define DEC_EL_BIT_POS_M GENMASK(2, 0)
188 #define ECC_FDMADDR 0x13c
190 /* ENCIDLE and DECIDLE */
191 #define ECC_IDLE BIT(0)
193 #define ACCTIMING(tpoecs, tprecs, tc2r, tw2r, twh, twst, trlt) \
194 ((tpoecs) << ACCCON_POECS_S | (tprecs) << ACCCON_PRECS_S | \
195 (tc2r) << ACCCON_C2R_S | (tw2r) << ACCCON_W2R_S | \
196 (twh) << ACCCON_WH_S | (twst) << ACCCON_WST_S | (trlt))
198 #define MASTER_STA_MASK (MAS_ADDR | MAS_RD | MAS_WR | \
200 #define NFI_RESET_TIMEOUT 1000000
201 #define NFI_CORE_TIMEOUT 500000
202 #define ECC_ENGINE_TIMEOUT 500000
204 #define ECC_SECTOR_SIZE 512
205 #define ECC_PARITY_BITS 13
207 #define NFI_FDM_SIZE 8
209 #define MT7621_NFC_NAME "mt7621-nand"
212 struct nand_controller controller
;
213 struct nand_chip nand
;
217 void __iomem
*nfi_regs
;
218 void __iomem
*ecc_regs
;
220 u32 spare_per_sector
;
223 static const u16 mt7621_nfi_page_size
[] = { SZ_512
, SZ_2K
, SZ_4K
};
224 static const u8 mt7621_nfi_spare_size
[] = { 16, 26, 27, 28 };
225 static const u8 mt7621_ecc_strength
[] = { 4, 6, 8, 10, 12 };
227 static inline u32
nfi_read32(struct mt7621_nfc
*nfc
, u32 reg
)
229 return readl(nfc
->nfi_regs
+ reg
);
232 static inline void nfi_write32(struct mt7621_nfc
*nfc
, u32 reg
, u32 val
)
234 writel(val
, nfc
->nfi_regs
+ reg
);
237 static inline u16
nfi_read16(struct mt7621_nfc
*nfc
, u32 reg
)
239 return readw(nfc
->nfi_regs
+ reg
);
242 static inline void nfi_write16(struct mt7621_nfc
*nfc
, u32 reg
, u16 val
)
244 writew(val
, nfc
->nfi_regs
+ reg
);
247 static inline void ecc_write16(struct mt7621_nfc
*nfc
, u32 reg
, u16 val
)
249 writew(val
, nfc
->ecc_regs
+ reg
);
252 static inline u32
ecc_read32(struct mt7621_nfc
*nfc
, u32 reg
)
254 return readl(nfc
->ecc_regs
+ reg
);
257 static inline void ecc_write32(struct mt7621_nfc
*nfc
, u32 reg
, u32 val
)
259 return writel(val
, nfc
->ecc_regs
+ reg
);
262 static inline u8
*oob_fdm_ptr(struct nand_chip
*nand
, int sect
)
264 return nand
->oob_poi
+ sect
* NFI_FDM_SIZE
;
267 static inline u8
*oob_ecc_ptr(struct mt7621_nfc
*nfc
, int sect
)
269 struct nand_chip
*nand
= &nfc
->nand
;
271 return nand
->oob_poi
+ nand
->ecc
.steps
* NFI_FDM_SIZE
+
272 sect
* (nfc
->spare_per_sector
- NFI_FDM_SIZE
);
275 static inline u8
*page_data_ptr(struct nand_chip
*nand
, const u8
*buf
,
278 return (u8
*)buf
+ sect
* nand
->ecc
.size
;
281 static int mt7621_ecc_wait_idle(struct mt7621_nfc
*nfc
, u32 reg
)
283 struct device
*dev
= nfc
->dev
;
287 ret
= readw_poll_timeout_atomic(nfc
->ecc_regs
+ reg
, val
,
291 dev_warn(dev
, "ECC engine timed out entering idle mode\n");
298 static int mt7621_ecc_decoder_wait_done(struct mt7621_nfc
*nfc
, u32 sect
)
300 struct device
*dev
= nfc
->dev
;
304 ret
= readw_poll_timeout_atomic(nfc
->ecc_regs
+ ECC_DECDONE
, val
,
305 val
& (1 << sect
), 10,
309 dev_warn(dev
, "ECC decoder for sector %d timed out\n",
317 static void mt7621_ecc_encoder_op(struct mt7621_nfc
*nfc
, bool enable
)
319 mt7621_ecc_wait_idle(nfc
, ECC_ENCIDLE
);
320 ecc_write16(nfc
, ECC_ENCCON
, enable
? ENC_EN
: 0);
323 static void mt7621_ecc_decoder_op(struct mt7621_nfc
*nfc
, bool enable
)
325 mt7621_ecc_wait_idle(nfc
, ECC_DECIDLE
);
326 ecc_write16(nfc
, ECC_DECCON
, enable
? DEC_EN
: 0);
329 static int mt7621_ecc_correct_check(struct mt7621_nfc
*nfc
, u8
*sector_buf
,
330 u8
*fdm_buf
, u32 sect
)
332 struct nand_chip
*nand
= &nfc
->nand
;
333 u32 decnum
, num_error_bits
, fdm_end_bits
;
334 u32 error_locations
, error_bit_loc
;
335 u32 error_byte_pos
, error_bit_pos
;
339 decnum
= ecc_read32(nfc
, ECC_DECENUM
);
340 num_error_bits
= (decnum
>> (sect
<< ERRNUM_S
)) & ERRNUM_M
;
341 fdm_end_bits
= (nand
->ecc
.size
+ NFI_FDM_SIZE
) << 3;
346 if (num_error_bits
== ERRNUM_M
)
349 for (i
= 0; i
< num_error_bits
; i
++) {
350 error_locations
= ecc_read32(nfc
, ECC_DECEL(i
/ 2));
351 error_bit_loc
= (error_locations
>> ((i
% 2) * DEC_EL_ODD_S
)) &
353 error_byte_pos
= error_bit_loc
>> DEC_EL_BYTE_POS_S
;
354 error_bit_pos
= error_bit_loc
& DEC_EL_BIT_POS_M
;
356 if (error_bit_loc
< (nand
->ecc
.size
<< 3)) {
358 sector_buf
[error_byte_pos
] ^=
359 (1 << error_bit_pos
);
361 } else if (error_bit_loc
< fdm_end_bits
) {
363 fdm_buf
[error_byte_pos
- nand
->ecc
.size
] ^=
364 (1 << error_bit_pos
);
374 static int mt7621_nfc_wait_write_completion(struct mt7621_nfc
*nfc
,
375 struct nand_chip
*nand
)
377 struct device
*dev
= nfc
->dev
;
381 ret
= readw_poll_timeout_atomic(nfc
->nfi_regs
+ NFI_ADDRCNTR
, val
,
382 ((val
& SEC_CNTR_M
) >> SEC_CNTR_S
) >= nand
->ecc
.steps
, 10,
386 dev_warn(dev
, "NFI core write operation timed out\n");
393 static void mt7621_nfc_hw_reset(struct mt7621_nfc
*nfc
)
398 /* reset all registers and force the NFI master to terminate */
399 nfi_write16(nfc
, NFI_CON
, CON_FIFO_FLUSH
| CON_NFI_RST
);
401 /* wait for the master to finish the last transaction */
402 ret
= readw_poll_timeout(nfc
->nfi_regs
+ NFI_MASTER_STA
, val
,
403 !(val
& MASTER_STA_MASK
), 50,
406 dev_warn(nfc
->dev
, "Failed to reset NFI master in %dms\n",
410 /* ensure any status register affected by the NFI master is reset */
411 nfi_write16(nfc
, NFI_CON
, CON_FIFO_FLUSH
| CON_NFI_RST
);
412 nfi_write16(nfc
, NFI_STRDATA
, 0);
415 static inline void mt7621_nfc_hw_init(struct mt7621_nfc
*nfc
)
420 * CNRNB: nand ready/busy register
421 * -------------------------------
422 * 7:4: timeout register for polling the NAND busy/ready signal
423 * 0 : poll the status of the busy/ready signal after [7:4]*16 cycles.
425 nfi_write16(nfc
, NFI_CNRNB
, CB2R_TIME_M
| STR_CNRNB
);
427 mt7621_nfc_hw_reset(nfc
);
429 /* Apply default access timing */
430 acccon
= ACCTIMING(ACCCON_POECS_DEF
, ACCCON_PRECS_DEF
, ACCCON_C2R_DEF
,
431 ACCCON_W2R_DEF
, ACCCON_WH_DEF
, ACCCON_WST_DEF
,
434 nfi_write32(nfc
, NFI_ACCCON
, acccon
);
437 static int mt7621_nfc_send_command(struct mt7621_nfc
*nfc
, u8 command
)
439 struct device
*dev
= nfc
->dev
;
443 nfi_write32(nfc
, NFI_CMD
, command
);
445 ret
= readl_poll_timeout_atomic(nfc
->nfi_regs
+ NFI_STA
, val
,
446 !(val
& STA_CMD
), 10,
449 dev_warn(dev
, "NFI core timed out entering command mode\n");
456 static int mt7621_nfc_send_address_byte(struct mt7621_nfc
*nfc
, int addr
)
458 struct device
*dev
= nfc
->dev
;
462 nfi_write32(nfc
, NFI_COLADDR
, addr
);
463 nfi_write32(nfc
, NFI_ROWADDR
, 0);
464 nfi_write16(nfc
, NFI_ADDRNOB
, 1);
466 ret
= readl_poll_timeout_atomic(nfc
->nfi_regs
+ NFI_STA
, val
,
467 !(val
& STA_ADDR
), 10,
470 dev_warn(dev
, "NFI core timed out entering address mode\n");
477 static int mt7621_nfc_send_address(struct mt7621_nfc
*nfc
, const u8
*addr
,
483 ret
= mt7621_nfc_send_address_byte(nfc
, *addr
);
494 static void mt7621_nfc_wait_pio_ready(struct mt7621_nfc
*nfc
)
496 struct device
*dev
= nfc
->dev
;
500 ret
= readw_poll_timeout_atomic(nfc
->nfi_regs
+ NFI_PIO_DIRDY
, val
,
504 dev_err(dev
, "NFI core PIO mode not ready\n");
507 static u32
mt7621_nfc_pio_read(struct mt7621_nfc
*nfc
, bool br
)
511 /* after each byte read, the NFI_STA reg is reset by the hardware */
512 reg
= (nfi_read32(nfc
, NFI_STA
) & STA_NFI_FSM_M
) >> STA_NFI_FSM_S
;
513 if (reg
!= STA_FSM_CUSTOM_DATA
) {
514 reg
= nfi_read16(nfc
, NFI_CNFG
);
515 reg
|= CNFG_READ_MODE
| CNFG_BYTE_RW
;
517 reg
&= ~CNFG_BYTE_RW
;
518 nfi_write16(nfc
, NFI_CNFG
, reg
);
521 * set to max sector to allow the HW to continue reading over
524 nfi_write16(nfc
, NFI_CON
, CON_NFI_SEC_M
| CON_NFI_BRD
);
526 /* trigger to fetch data */
527 nfi_write16(nfc
, NFI_STRDATA
, STR_DATA
);
530 mt7621_nfc_wait_pio_ready(nfc
);
532 return nfi_read32(nfc
, NFI_DATAR
);
535 static void mt7621_nfc_read_data(struct mt7621_nfc
*nfc
, u8
*buf
, u32 len
)
537 while (((uintptr_t)buf
& 3) && len
) {
538 *buf
= mt7621_nfc_pio_read(nfc
, true);
544 *(u32
*)buf
= mt7621_nfc_pio_read(nfc
, false);
550 *buf
= mt7621_nfc_pio_read(nfc
, true);
556 static void mt7621_nfc_read_data_discard(struct mt7621_nfc
*nfc
, u32 len
)
559 mt7621_nfc_pio_read(nfc
, false);
564 mt7621_nfc_pio_read(nfc
, true);
569 static void mt7621_nfc_pio_write(struct mt7621_nfc
*nfc
, u32 val
, bool bw
)
573 reg
= (nfi_read32(nfc
, NFI_STA
) & STA_NFI_FSM_M
) >> STA_NFI_FSM_S
;
574 if (reg
!= STA_FSM_CUSTOM_DATA
) {
575 reg
= nfi_read16(nfc
, NFI_CNFG
);
576 reg
&= ~(CNFG_READ_MODE
| CNFG_BYTE_RW
);
579 nfi_write16(nfc
, NFI_CNFG
, reg
);
581 nfi_write16(nfc
, NFI_CON
, CON_NFI_SEC_M
| CON_NFI_BWR
);
582 nfi_write16(nfc
, NFI_STRDATA
, STR_DATA
);
585 mt7621_nfc_wait_pio_ready(nfc
);
586 nfi_write32(nfc
, NFI_DATAW
, val
);
589 static void mt7621_nfc_write_data(struct mt7621_nfc
*nfc
, const u8
*buf
,
592 while (((uintptr_t)buf
& 3) && len
) {
593 mt7621_nfc_pio_write(nfc
, *buf
, true);
599 mt7621_nfc_pio_write(nfc
, *(const u32
*)buf
, false);
605 mt7621_nfc_pio_write(nfc
, *buf
, true);
611 static void mt7621_nfc_write_data_empty(struct mt7621_nfc
*nfc
, u32 len
)
614 mt7621_nfc_pio_write(nfc
, 0xffffffff, false);
619 mt7621_nfc_pio_write(nfc
, 0xff, true);
624 static int mt7621_nfc_dev_ready(struct mt7621_nfc
*nfc
,
625 unsigned int timeout_ms
)
629 return readl_poll_timeout_atomic(nfc
->nfi_regs
+ NFI_STA
, val
,
630 !(val
& STA_BUSY
), 10,
634 static int mt7621_nfc_exec_instr(struct nand_chip
*nand
,
635 const struct nand_op_instr
*instr
)
637 struct mt7621_nfc
*nfc
= nand_get_controller_data(nand
);
639 switch (instr
->type
) {
640 case NAND_OP_CMD_INSTR
:
641 mt7621_nfc_hw_reset(nfc
);
642 nfi_write16(nfc
, NFI_CNFG
, CNFG_OP_CUSTOM
<< CNFG_OP_MODE_S
);
643 return mt7621_nfc_send_command(nfc
, instr
->ctx
.cmd
.opcode
);
644 case NAND_OP_ADDR_INSTR
:
645 return mt7621_nfc_send_address(nfc
, instr
->ctx
.addr
.addrs
,
646 instr
->ctx
.addr
.naddrs
);
647 case NAND_OP_DATA_IN_INSTR
:
648 mt7621_nfc_read_data(nfc
, instr
->ctx
.data
.buf
.in
,
649 instr
->ctx
.data
.len
);
651 case NAND_OP_DATA_OUT_INSTR
:
652 mt7621_nfc_write_data(nfc
, instr
->ctx
.data
.buf
.out
,
653 instr
->ctx
.data
.len
);
655 case NAND_OP_WAITRDY_INSTR
:
656 return mt7621_nfc_dev_ready(nfc
,
657 instr
->ctx
.waitrdy
.timeout_ms
);
659 WARN_ONCE(1, "unsupported NAND instruction type: %d\n",
666 static int mt7621_nfc_exec_op(struct nand_chip
*nand
,
667 const struct nand_operation
*op
, bool check_only
)
669 struct mt7621_nfc
*nfc
= nand_get_controller_data(nand
);
675 /* Only CS0 available */
676 nfi_write16(nfc
, NFI_CSEL
, 0);
678 for (i
= 0; i
< op
->ninstrs
; i
++) {
679 ret
= mt7621_nfc_exec_instr(nand
, &op
->instrs
[i
]);
687 static int mt7621_nfc_setup_interface(struct nand_chip
*nand
, int csline
,
688 const struct nand_interface_config
*conf
)
690 struct mt7621_nfc
*nfc
= nand_get_controller_data(nand
);
691 const struct nand_sdr_timings
*timings
;
692 u32 acccon
, temp
, rate
, tpoecs
, tprecs
, tc2r
, tw2r
, twh
, twst
, trlt
;
697 timings
= nand_get_sdr_timings(conf
);
701 rate
= clk_get_rate(nfc
->nfi_clk
);
703 /* turn clock rate into KHZ */
706 tpoecs
= max(timings
->tALH_min
, timings
->tCLH_min
) / 1000;
707 tpoecs
= DIV_ROUND_UP(tpoecs
* rate
, 1000000);
708 tpoecs
= min_t(u32
, tpoecs
, ACCCON_POECS_MAX
);
710 tprecs
= max(timings
->tCLS_min
, timings
->tALS_min
) / 1000;
711 tprecs
= DIV_ROUND_UP(tprecs
* rate
, 1000000);
712 tprecs
= min_t(u32
, tprecs
, ACCCON_PRECS_MAX
);
714 /* sdr interface has no tCR which means CE# low to RE# low */
717 tw2r
= timings
->tWHR_min
/ 1000;
718 tw2r
= DIV_ROUND_UP(tw2r
* rate
, 1000000);
719 tw2r
= DIV_ROUND_UP(tw2r
- 1, 2);
720 tw2r
= min_t(u32
, tw2r
, ACCCON_W2R_MAX
);
722 twh
= max(timings
->tREH_min
, timings
->tWH_min
) / 1000;
723 twh
= DIV_ROUND_UP(twh
* rate
, 1000000) - 1;
724 twh
= min_t(u32
, twh
, ACCCON_WH_MAX
);
726 /* Calculate real WE#/RE# hold time in nanosecond */
727 temp
= (twh
+ 1) * 1000000 / rate
;
728 /* nanosecond to picosecond */
732 * WE# low level time should be expaned to meet WE# pulse time
733 * and WE# cycle time at the same time.
735 if (temp
< timings
->tWC_min
)
736 twst
= timings
->tWC_min
- temp
;
739 twst
= max(timings
->tWP_min
, twst
) / 1000;
740 twst
= DIV_ROUND_UP(twst
* rate
, 1000000) - 1;
741 twst
= min_t(u32
, twst
, ACCCON_WST_MAX
);
744 * RE# low level time should be expaned to meet RE# pulse time
745 * and RE# cycle time at the same time.
747 if (temp
< timings
->tRC_min
)
748 trlt
= timings
->tRC_min
- temp
;
751 trlt
= max(trlt
, timings
->tRP_min
) / 1000;
752 trlt
= DIV_ROUND_UP(trlt
* rate
, 1000000) - 1;
753 trlt
= min_t(u32
, trlt
, ACCCON_RLT_MAX
);
755 if (csline
== NAND_DATA_IFACE_CHECK_ONLY
) {
756 if (twst
< ACCCON_WST_MIN
|| trlt
< ACCCON_RLT_MIN
)
760 acccon
= ACCTIMING(tpoecs
, tprecs
, tc2r
, tw2r
, twh
, twst
, trlt
);
762 dev_info(nfc
->dev
, "Using programmed access timing: %08x\n", acccon
);
764 nfi_write32(nfc
, NFI_ACCCON
, acccon
);
769 static int mt7621_nfc_calc_ecc_strength(struct mt7621_nfc
*nfc
,
772 struct nand_chip
*nand
= &nfc
->nand
;
773 struct mtd_info
*mtd
= nand_to_mtd(nand
);
777 strength
= avail_ecc_bytes
* 8 / ECC_PARITY_BITS
;
779 /* Find the closest supported ecc strength */
780 for (i
= ARRAY_SIZE(mt7621_ecc_strength
) - 1; i
>= 0; i
--) {
781 if (mt7621_ecc_strength
[i
] <= strength
)
785 if (unlikely(i
< 0)) {
786 dev_err(nfc
->dev
, "OOB size (%u) is not supported\n",
791 nand
->ecc
.strength
= mt7621_ecc_strength
[i
];
793 DIV_ROUND_UP(nand
->ecc
.strength
* ECC_PARITY_BITS
, 8);
795 dev_info(nfc
->dev
, "ECC strength adjusted to %u bits\n",
801 static int mt7621_nfc_set_spare_per_sector(struct mt7621_nfc
*nfc
)
803 struct nand_chip
*nand
= &nfc
->nand
;
804 struct mtd_info
*mtd
= nand_to_mtd(nand
);
808 size
= nand
->ecc
.bytes
+ NFI_FDM_SIZE
;
810 /* Find the closest supported spare size */
811 for (i
= 0; i
< ARRAY_SIZE(mt7621_nfi_spare_size
); i
++) {
812 if (mt7621_nfi_spare_size
[i
] >= size
)
816 if (unlikely(i
>= ARRAY_SIZE(mt7621_nfi_spare_size
))) {
817 dev_err(nfc
->dev
, "OOB size (%u) is not supported\n",
822 nfc
->spare_per_sector
= mt7621_nfi_spare_size
[i
];
827 static int mt7621_nfc_ecc_init(struct mt7621_nfc
*nfc
)
829 struct nand_chip
*nand
= &nfc
->nand
;
830 struct mtd_info
*mtd
= nand_to_mtd(nand
);
831 u32 spare_per_sector
, encode_block_size
, decode_block_size
;
832 u32 ecc_enccfg
, ecc_deccfg
;
835 /* Only hardware ECC mode is supported */
836 if (nand
->ecc
.engine_type
!= NAND_ECC_ENGINE_TYPE_ON_HOST
) {
837 dev_err(nfc
->dev
, "Only hardware ECC mode is supported\n");
841 nand
->ecc
.size
= ECC_SECTOR_SIZE
;
842 nand
->ecc
.steps
= mtd
->writesize
/ nand
->ecc
.size
;
844 spare_per_sector
= mtd
->oobsize
/ nand
->ecc
.steps
;
846 ecc_cap
= mt7621_nfc_calc_ecc_strength(nfc
,
847 spare_per_sector
- NFI_FDM_SIZE
);
852 encode_block_size
= (nand
->ecc
.size
+ NFI_FDM_SIZE
) * 8;
853 ecc_enccfg
= ecc_cap
| (ENC_MODE_NFI
<< ENC_MODE_S
) |
854 (encode_block_size
<< ENC_CNFG_MSG_S
);
856 /* Sector + FDM + ECC parity bits */
857 decode_block_size
= ((nand
->ecc
.size
+ NFI_FDM_SIZE
) * 8) +
858 nand
->ecc
.strength
* ECC_PARITY_BITS
;
859 ecc_deccfg
= ecc_cap
| (DEC_MODE_NFI
<< DEC_MODE_S
) |
860 (decode_block_size
<< DEC_CS_S
) |
861 (DEC_CON_EL
<< DEC_CON_S
) | DEC_EMPTY_EN
;
863 mt7621_ecc_encoder_op(nfc
, false);
864 ecc_write32(nfc
, ECC_ENCCNFG
, ecc_enccfg
);
866 mt7621_ecc_decoder_op(nfc
, false);
867 ecc_write32(nfc
, ECC_DECCNFG
, ecc_deccfg
);
872 static int mt7621_nfc_set_page_format(struct mt7621_nfc
*nfc
)
874 struct nand_chip
*nand
= &nfc
->nand
;
875 struct mtd_info
*mtd
= nand_to_mtd(nand
);
879 spare_size
= mt7621_nfc_set_spare_per_sector(nfc
);
883 for (i
= 0; i
< ARRAY_SIZE(mt7621_nfi_page_size
); i
++) {
884 if (mt7621_nfi_page_size
[i
] == mtd
->writesize
)
888 if (unlikely(i
>= ARRAY_SIZE(mt7621_nfi_page_size
))) {
889 dev_err(nfc
->dev
, "Page size (%u) is not supported\n",
894 pagefmt
= i
| (spare_size
<< PAGEFMT_SPARE_S
) |
895 (NFI_FDM_SIZE
<< PAGEFMT_FDM_S
) |
896 (NFI_FDM_SIZE
<< PAGEFMT_FDM_ECC_S
);
898 nfi_write16(nfc
, NFI_PAGEFMT
, pagefmt
);
903 static int mt7621_nfc_attach_chip(struct nand_chip
*nand
)
905 struct mt7621_nfc
*nfc
= nand_get_controller_data(nand
);
908 if (nand
->options
& NAND_BUSWIDTH_16
) {
909 dev_err(nfc
->dev
, "16-bit buswidth is not supported");
913 ret
= mt7621_nfc_ecc_init(nfc
);
917 return mt7621_nfc_set_page_format(nfc
);
920 static const struct nand_controller_ops mt7621_nfc_controller_ops
= {
921 .attach_chip
= mt7621_nfc_attach_chip
,
922 .exec_op
= mt7621_nfc_exec_op
,
923 .setup_interface
= mt7621_nfc_setup_interface
,
926 static int mt7621_nfc_ooblayout_free(struct mtd_info
*mtd
, int section
,
927 struct mtd_oob_region
*oob_region
)
929 struct nand_chip
*nand
= mtd_to_nand(mtd
);
931 if (section
>= nand
->ecc
.steps
)
934 oob_region
->length
= NFI_FDM_SIZE
- 1;
935 oob_region
->offset
= section
* NFI_FDM_SIZE
+ 1;
940 static int mt7621_nfc_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
941 struct mtd_oob_region
*oob_region
)
943 struct nand_chip
*nand
= mtd_to_nand(mtd
);
948 oob_region
->offset
= NFI_FDM_SIZE
* nand
->ecc
.steps
;
949 oob_region
->length
= mtd
->oobsize
- oob_region
->offset
;
954 static const struct mtd_ooblayout_ops mt7621_nfc_ooblayout_ops
= {
955 .free
= mt7621_nfc_ooblayout_free
,
956 .ecc
= mt7621_nfc_ooblayout_ecc
,
959 static void mt7621_nfc_write_fdm(struct mt7621_nfc
*nfc
)
961 struct nand_chip
*nand
= &nfc
->nand
;
966 for (i
= 0; i
< nand
->ecc
.steps
; i
++) {
969 oobptr
= oob_fdm_ptr(nand
, i
);
971 for (j
= 0; j
< 4; j
++)
972 vall
|= (u32
)oobptr
[j
] << (j
* 8);
974 for (j
= 0; j
< 4; j
++)
975 valm
|= (u32
)oobptr
[j
+ 4] << (j
* 8);
977 nfi_write32(nfc
, NFI_FDML(i
), vall
);
978 nfi_write32(nfc
, NFI_FDMM(i
), valm
);
982 static void mt7621_nfc_read_sector_fdm(struct mt7621_nfc
*nfc
, u32 sect
)
984 struct nand_chip
*nand
= &nfc
->nand
;
989 vall
= nfi_read32(nfc
, NFI_FDML(sect
));
990 valm
= nfi_read32(nfc
, NFI_FDMM(sect
));
991 oobptr
= oob_fdm_ptr(nand
, sect
);
993 for (i
= 0; i
< 4; i
++)
994 oobptr
[i
] = (vall
>> (i
* 8)) & 0xff;
996 for (i
= 0; i
< 4; i
++)
997 oobptr
[i
+ 4] = (valm
>> (i
* 8)) & 0xff;
1000 static int mt7621_nfc_read_page_hwecc(struct nand_chip
*nand
, uint8_t *buf
,
1001 int oob_required
, int page
)
1003 struct mt7621_nfc
*nfc
= nand_get_controller_data(nand
);
1004 struct mtd_info
*mtd
= nand_to_mtd(nand
);
1008 nand_read_page_op(nand
, page
, 0, NULL
, 0);
1010 nfi_write16(nfc
, NFI_CNFG
, (CNFG_OP_CUSTOM
<< CNFG_OP_MODE_S
) |
1011 CNFG_READ_MODE
| CNFG_AUTO_FMT_EN
| CNFG_HW_ECC_EN
);
1013 mt7621_ecc_decoder_op(nfc
, true);
1015 nfi_write16(nfc
, NFI_CON
,
1016 CON_NFI_BRD
| (nand
->ecc
.steps
<< CON_NFI_SEC_S
));
1018 for (i
= 0; i
< nand
->ecc
.steps
; i
++) {
1020 mt7621_nfc_read_data(nfc
, page_data_ptr(nand
, buf
, i
),
1023 mt7621_nfc_read_data_discard(nfc
, nand
->ecc
.size
);
1025 rc
= mt7621_ecc_decoder_wait_done(nfc
, i
);
1027 mt7621_nfc_read_sector_fdm(nfc
, i
);
1034 rc
= mt7621_ecc_correct_check(nfc
,
1035 buf
? page_data_ptr(nand
, buf
, i
) : NULL
,
1036 oob_fdm_ptr(nand
, i
), i
);
1040 "Uncorrectable ECC error at page %d.%d\n",
1042 bitflips
= -EBADMSG
;
1043 mtd
->ecc_stats
.failed
++;
1044 } else if (bitflips
>= 0) {
1046 mtd
->ecc_stats
.corrected
+= rc
;
1050 mt7621_ecc_decoder_op(nfc
, false);
1052 nfi_write16(nfc
, NFI_CON
, 0);
1057 static int mt7621_nfc_read_page_raw(struct nand_chip
*nand
, uint8_t *buf
,
1058 int oob_required
, int page
)
1060 struct mt7621_nfc
*nfc
= nand_get_controller_data(nand
);
1063 nand_read_page_op(nand
, page
, 0, NULL
, 0);
1065 nfi_write16(nfc
, NFI_CNFG
, (CNFG_OP_CUSTOM
<< CNFG_OP_MODE_S
) |
1068 nfi_write16(nfc
, NFI_CON
,
1069 CON_NFI_BRD
| (nand
->ecc
.steps
<< CON_NFI_SEC_S
));
1071 for (i
= 0; i
< nand
->ecc
.steps
; i
++) {
1074 mt7621_nfc_read_data(nfc
, page_data_ptr(nand
, buf
, i
),
1077 mt7621_nfc_read_data_discard(nfc
, nand
->ecc
.size
);
1080 mt7621_nfc_read_data(nfc
, oob_fdm_ptr(nand
, i
), NFI_FDM_SIZE
);
1082 /* Read ECC parity data */
1083 mt7621_nfc_read_data(nfc
, oob_ecc_ptr(nfc
, i
),
1084 nfc
->spare_per_sector
- NFI_FDM_SIZE
);
1087 nfi_write16(nfc
, NFI_CON
, 0);
1092 static int mt7621_nfc_read_oob_hwecc(struct nand_chip
*nand
, int page
)
1094 return mt7621_nfc_read_page_hwecc(nand
, NULL
, 1, page
);
1097 static int mt7621_nfc_read_oob_raw(struct nand_chip
*nand
, int page
)
1099 return mt7621_nfc_read_page_raw(nand
, NULL
, 1, page
);
1102 static int mt7621_nfc_check_empty_page(struct nand_chip
*nand
, const u8
*buf
)
1104 struct mtd_info
*mtd
= nand_to_mtd(nand
);
1109 for (i
= 0; i
< mtd
->writesize
; i
++)
1114 for (i
= 0; i
< nand
->ecc
.steps
; i
++) {
1115 oobptr
= oob_fdm_ptr(nand
, i
);
1116 for (j
= 0; j
< NFI_FDM_SIZE
; j
++)
1117 if (oobptr
[j
] != 0xff)
1124 static int mt7621_nfc_write_page_hwecc(struct nand_chip
*nand
,
1125 const uint8_t *buf
, int oob_required
,
1128 struct mt7621_nfc
*nfc
= nand_get_controller_data(nand
);
1129 struct mtd_info
*mtd
= nand_to_mtd(nand
);
1131 if (mt7621_nfc_check_empty_page(nand
, buf
)) {
1133 * MT7621 ECC engine always generates parity code for input
1134 * pages, even for empty pages. Doing so will write back ECC
1135 * parity code to the oob region, which means such pages will
1136 * no longer be empty pages.
1138 * To avoid this, stop write operation if current page is an
1144 nand_prog_page_begin_op(nand
, page
, 0, NULL
, 0);
1146 nfi_write16(nfc
, NFI_CNFG
, (CNFG_OP_CUSTOM
<< CNFG_OP_MODE_S
) |
1147 CNFG_AUTO_FMT_EN
| CNFG_HW_ECC_EN
);
1149 mt7621_ecc_encoder_op(nfc
, true);
1151 mt7621_nfc_write_fdm(nfc
);
1153 nfi_write16(nfc
, NFI_CON
,
1154 CON_NFI_BWR
| (nand
->ecc
.steps
<< CON_NFI_SEC_S
));
1157 mt7621_nfc_write_data(nfc
, buf
, mtd
->writesize
);
1159 mt7621_nfc_write_data_empty(nfc
, mtd
->writesize
);
1161 mt7621_nfc_wait_write_completion(nfc
, nand
);
1163 mt7621_ecc_encoder_op(nfc
, false);
1165 nfi_write16(nfc
, NFI_CON
, 0);
1167 return nand_prog_page_end_op(nand
);
1170 static int mt7621_nfc_write_page_raw(struct nand_chip
*nand
,
1171 const uint8_t *buf
, int oob_required
,
1174 struct mt7621_nfc
*nfc
= nand_get_controller_data(nand
);
1177 nand_prog_page_begin_op(nand
, page
, 0, NULL
, 0);
1179 nfi_write16(nfc
, NFI_CNFG
, (CNFG_OP_CUSTOM
<< CNFG_OP_MODE_S
));
1181 nfi_write16(nfc
, NFI_CON
,
1182 CON_NFI_BWR
| (nand
->ecc
.steps
<< CON_NFI_SEC_S
));
1184 for (i
= 0; i
< nand
->ecc
.steps
; i
++) {
1187 mt7621_nfc_write_data(nfc
, page_data_ptr(nand
, buf
, i
),
1190 mt7621_nfc_write_data_empty(nfc
, nand
->ecc
.size
);
1193 mt7621_nfc_write_data(nfc
, oob_fdm_ptr(nand
, i
),
1196 /* Write dummy ECC parity data */
1197 mt7621_nfc_write_data_empty(nfc
, nfc
->spare_per_sector
-
1201 mt7621_nfc_wait_write_completion(nfc
, nand
);
1203 nfi_write16(nfc
, NFI_CON
, 0);
1205 return nand_prog_page_end_op(nand
);
1208 static int mt7621_nfc_write_oob_hwecc(struct nand_chip
*nand
, int page
)
1210 return mt7621_nfc_write_page_hwecc(nand
, NULL
, 1, page
);
1213 static int mt7621_nfc_write_oob_raw(struct nand_chip
*nand
, int page
)
1215 return mt7621_nfc_write_page_raw(nand
, NULL
, 1, page
);
1218 static int mt7621_nfc_init_chip(struct mt7621_nfc
*nfc
)
1220 struct nand_chip
*nand
= &nfc
->nand
;
1221 struct mtd_info
*mtd
;
1224 nand
->controller
= &nfc
->controller
;
1225 nand_set_controller_data(nand
, (void *)nfc
);
1226 nand_set_flash_node(nand
, nfc
->dev
->of_node
);
1228 nand
->options
|= NAND_USES_DMA
| NAND_NO_SUBPAGE_WRITE
;
1230 nand
->options
|= NAND_KEEP_TIMINGS
;
1232 nand
->ecc
.engine_type
= NAND_ECC_ENGINE_TYPE_ON_HOST
;
1233 nand
->ecc
.read_page
= mt7621_nfc_read_page_hwecc
;
1234 nand
->ecc
.read_page_raw
= mt7621_nfc_read_page_raw
;
1235 nand
->ecc
.write_page
= mt7621_nfc_write_page_hwecc
;
1236 nand
->ecc
.write_page_raw
= mt7621_nfc_write_page_raw
;
1237 nand
->ecc
.read_oob
= mt7621_nfc_read_oob_hwecc
;
1238 nand
->ecc
.read_oob_raw
= mt7621_nfc_read_oob_raw
;
1239 nand
->ecc
.write_oob
= mt7621_nfc_write_oob_hwecc
;
1240 nand
->ecc
.write_oob_raw
= mt7621_nfc_write_oob_raw
;
1242 mtd
= nand_to_mtd(nand
);
1243 mtd
->owner
= THIS_MODULE
;
1244 mtd
->dev
.parent
= nfc
->dev
;
1245 mtd
->name
= MT7621_NFC_NAME
;
1246 mtd_set_ooblayout(mtd
, &mt7621_nfc_ooblayout_ops
);
1248 mt7621_nfc_hw_init(nfc
);
1250 ret
= nand_scan(nand
, 1);
1254 ret
= mtd_device_register(mtd
, NULL
, 0);
1256 dev_err(nfc
->dev
, "Failed to register MTD: %d\n", ret
);
1264 static int mt7621_nfc_probe(struct platform_device
*pdev
)
1266 struct device
*dev
= &pdev
->dev
;
1267 struct mt7621_nfc
*nfc
;
1268 struct resource
*res
;
1271 nfc
= devm_kzalloc(dev
, sizeof(*nfc
), GFP_KERNEL
);
1275 nand_controller_init(&nfc
->controller
);
1276 nfc
->controller
.ops
= &mt7621_nfc_controller_ops
;
1279 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "nfi");
1280 nfc
->nfi_regs
= devm_ioremap_resource(dev
, res
);
1281 if (IS_ERR(nfc
->nfi_regs
)) {
1282 ret
= PTR_ERR(nfc
->nfi_regs
);
1286 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "ecc");
1287 nfc
->ecc_regs
= devm_ioremap_resource(dev
, res
);
1288 if (IS_ERR(nfc
->ecc_regs
)) {
1289 ret
= PTR_ERR(nfc
->ecc_regs
);
1293 nfc
->nfi_clk
= devm_clk_get(dev
, "nfi_clk");
1294 if (IS_ERR(nfc
->nfi_clk
)) {
1295 dev_warn(dev
, "nfi clk not provided\n");
1296 nfc
->nfi_clk
= NULL
;
1298 ret
= clk_prepare_enable(nfc
->nfi_clk
);
1300 dev_err(dev
, "Failed to enable nfi core clock\n");
1305 platform_set_drvdata(pdev
, nfc
);
1307 ret
= mt7621_nfc_init_chip(nfc
);
1309 dev_err(dev
, "Failed to initialize nand chip\n");
1316 clk_disable_unprepare(nfc
->nfi_clk
);
1321 static int mt7621_nfc_remove(struct platform_device
*pdev
)
1323 struct mt7621_nfc
*nfc
= platform_get_drvdata(pdev
);
1324 struct nand_chip
*nand
= &nfc
->nand
;
1325 struct mtd_info
*mtd
= nand_to_mtd(nand
);
1327 mtd_device_unregister(mtd
);
1329 clk_disable_unprepare(nfc
->nfi_clk
);
1334 static const struct of_device_id mt7621_nfc_id_table
[] = {
1335 { .compatible
= "mediatek,mt7621-nfc" },
1338 MODULE_DEVICE_TABLE(of
, match
);
1340 static struct platform_driver mt7621_nfc_driver
= {
1341 .probe
= mt7621_nfc_probe
,
1342 .remove
= mt7621_nfc_remove
,
1344 .name
= MT7621_NFC_NAME
,
1345 .owner
= THIS_MODULE
,
1346 .of_match_table
= mt7621_nfc_id_table
,
1349 module_platform_driver(mt7621_nfc_driver
);
1351 MODULE_LICENSE("GPL");
1352 MODULE_AUTHOR("Weijie Gao <weijie.gao@mediatek.com>");
1353 MODULE_DESCRIPTION("MediaTek MT7621 NAND Flash Controller driver");