1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 * Copyright (C) 2016 Vittorio Gambaletta <openwrt@vittgam.net>
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/platform_device.h>
19 #include <asm/mach-ralink/ralink_regs.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
23 #include <linux/switch.h>
24 #include <linux/reset.h>
26 #include "mtk_eth_soc.h"
27 #include "esw_rt3050.h"
29 /* HW limitations for this switch:
30 * - No large frame support (PKT_MAX_LEN at most 1536)
31 * - Can't have untagged vlan and tagged vlan on one port at the same time,
32 * though this might be possible using the undocumented PPE.
35 #define RT305X_ESW_REG_ISR 0x00
36 #define RT305X_ESW_REG_IMR 0x04
37 #define RT305X_ESW_REG_FCT0 0x08
38 #define RT305X_ESW_REG_PFC1 0x14
39 #define RT305X_ESW_REG_ATS 0x24
40 #define RT305X_ESW_REG_ATS0 0x28
41 #define RT305X_ESW_REG_ATS1 0x2c
42 #define RT305X_ESW_REG_ATS2 0x30
43 #define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
44 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
45 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
46 #define RT305X_ESW_REG_POA 0x80
47 #define RT305X_ESW_REG_FPA 0x84
48 #define RT305X_ESW_REG_SOCPC 0x8c
49 #define RT305X_ESW_REG_POC0 0x90
50 #define RT305X_ESW_REG_POC1 0x94
51 #define RT305X_ESW_REG_POC2 0x98
52 #define RT305X_ESW_REG_SGC 0x9c
53 #define RT305X_ESW_REG_STRT 0xa0
54 #define RT305X_ESW_REG_PCR0 0xc0
55 #define RT305X_ESW_REG_PCR1 0xc4
56 #define RT305X_ESW_REG_FPA2 0xc8
57 #define RT305X_ESW_REG_FCT2 0xcc
58 #define RT305X_ESW_REG_SGC2 0xe4
59 #define RT305X_ESW_REG_P0LED 0xa4
60 #define RT305X_ESW_REG_P1LED 0xa8
61 #define RT305X_ESW_REG_P2LED 0xac
62 #define RT305X_ESW_REG_P3LED 0xb0
63 #define RT305X_ESW_REG_P4LED 0xb4
64 #define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
65 #define RT305X_ESW_REG_P1PC 0xec
66 #define RT305X_ESW_REG_P2PC 0xf0
67 #define RT305X_ESW_REG_P3PC 0xf4
68 #define RT305X_ESW_REG_P4PC 0xf8
69 #define RT305X_ESW_REG_P5PC 0xfc
71 #define RT305X_ESW_LED_LINK 0
72 #define RT305X_ESW_LED_100M 1
73 #define RT305X_ESW_LED_DUPLEX 2
74 #define RT305X_ESW_LED_ACTIVITY 3
75 #define RT305X_ESW_LED_COLLISION 4
76 #define RT305X_ESW_LED_LINKACT 5
77 #define RT305X_ESW_LED_DUPLCOLL 6
78 #define RT305X_ESW_LED_10MACT 7
79 #define RT305X_ESW_LED_100MACT 8
80 /* Additional led states not in datasheet: */
81 #define RT305X_ESW_LED_BLINK 10
82 #define RT305X_ESW_LED_OFF 11
83 #define RT305X_ESW_LED_ON 12
85 #define RT305X_ESW_LINK_S 25
86 #define RT305X_ESW_DUPLEX_S 9
87 #define RT305X_ESW_SPD_S 0
89 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
90 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
91 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
93 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
95 #define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
96 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
98 #define RT305X_ESW_PVIDC_PVID_M 0xfff
99 #define RT305X_ESW_PVIDC_PVID_S 12
101 #define RT305X_ESW_VLANI_VID_M 0xfff
102 #define RT305X_ESW_VLANI_VID_S 12
104 #define RT305X_ESW_VMSC_MSC_M 0xff
105 #define RT305X_ESW_VMSC_MSC_S 8
107 #define RT305X_ESW_SOCPC_DISUN2CPU_S 0
108 #define RT305X_ESW_SOCPC_DISMC2CPU_S 8
109 #define RT305X_ESW_SOCPC_DISBC2CPU_S 16
110 #define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
112 #define RT305X_ESW_POC0_EN_BP_S 0
113 #define RT305X_ESW_POC0_EN_FC_S 8
114 #define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
115 #define RT305X_ESW_POC0_DIS_PORT_M 0x7f
116 #define RT305X_ESW_POC0_DIS_PORT_S 23
118 #define RT305X_ESW_POC2_UNTAG_EN_M 0xff
119 #define RT305X_ESW_POC2_UNTAG_EN_S 0
120 #define RT305X_ESW_POC2_ENAGING_S 8
121 #define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
123 #define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
124 #define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
125 #define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
126 #define RT305X_ESW_SGC2_LAN_PMAP_S 24
128 #define RT305X_ESW_PFC1_EN_VLAN_M 0xff
129 #define RT305X_ESW_PFC1_EN_VLAN_S 16
130 #define RT305X_ESW_PFC1_EN_TOS_S 24
132 #define RT305X_ESW_VLAN_NONE 0xfff
134 #define RT305X_ESW_GSC_BC_STROM_MASK 0x3
135 #define RT305X_ESW_GSC_BC_STROM_SHIFT 4
137 #define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
138 #define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
140 #define RT305X_ESW_POA_LINK_MASK 0x1f
141 #define RT305X_ESW_POA_LINK_SHIFT 25
143 #define RT305X_ESW_PORT_ST_CHG BIT(26)
144 #define RT305X_ESW_PORT0 0
145 #define RT305X_ESW_PORT1 1
146 #define RT305X_ESW_PORT2 2
147 #define RT305X_ESW_PORT3 3
148 #define RT305X_ESW_PORT4 4
149 #define RT305X_ESW_PORT5 5
150 #define RT305X_ESW_PORT6 6
152 #define RT305X_ESW_PORTS_NONE 0
154 #define RT305X_ESW_PMAP_LLLLLL 0x3f
155 #define RT305X_ESW_PMAP_LLLLWL 0x2f
156 #define RT305X_ESW_PMAP_WLLLLL 0x3e
158 #define RT305X_ESW_PORTS_INTERNAL \
159 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
160 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
161 BIT(RT305X_ESW_PORT4))
163 #define RT305X_ESW_PORTS_NOCPU \
164 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
166 #define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
168 #define RT305X_ESW_PORTS_ALL \
169 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
171 #define RT305X_ESW_NUM_VLANS 16
172 #define RT305X_ESW_NUM_VIDS 4096
173 #define RT305X_ESW_NUM_PORTS 7
174 #define RT305X_ESW_NUM_LANWAN 6
175 #define RT305X_ESW_NUM_LEDS 5
177 #define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
178 #define RT5350_EWS_REG_LED_CONTROL 0x168
181 /* Global attributes. */
182 RT305X_ESW_ATTR_ENABLE_VLAN
,
183 RT305X_ESW_ATTR_ALT_VLAN_DISABLE
,
184 RT305X_ESW_ATTR_BC_STATUS
,
185 RT305X_ESW_ATTR_LED_FREQ
,
186 /* Port attributes. */
187 RT305X_ESW_ATTR_PORT_DISABLE
,
188 RT305X_ESW_ATTR_PORT_DOUBLETAG
,
189 RT305X_ESW_ATTR_PORT_UNTAG
,
190 RT305X_ESW_ATTR_PORT_LED
,
191 RT305X_ESW_ATTR_PORT_LAN
,
192 RT305X_ESW_ATTR_PORT_RECV_BAD
,
193 RT305X_ESW_ATTR_PORT_RECV_GOOD
,
194 RT5350_ESW_ATTR_PORT_TR_BAD
,
195 RT5350_ESW_ATTR_PORT_TR_GOOD
,
212 RT305X_ESW_VLAN_CONFIG_NONE
= 0,
213 RT305X_ESW_VLAN_CONFIG_LLLLW
,
214 RT305X_ESW_VLAN_CONFIG_WLLLL
,
221 struct fe_priv
*priv
;
223 /* Protects against concurrent register r/w operations. */
224 spinlock_t reg_rw_lock
;
226 unsigned char port_map
;
227 unsigned char port_disable
;
228 unsigned int reg_initval_fct2
;
229 unsigned int reg_initval_fpa2
;
230 unsigned int reg_led_polarity
;
231 unsigned int reg_led_source
;
233 struct switch_dev swdev
;
234 bool global_vlan_enable
;
235 bool alt_vlan_disable
;
236 int bc_storm_protect
;
238 struct esw_vlan vlans
[RT305X_ESW_NUM_VLANS
];
239 struct esw_port ports
[RT305X_ESW_NUM_PORTS
];
240 struct reset_control
*rst_esw
;
241 struct reset_control
*rst_ephy
;
245 static inline void esw_w32(struct rt305x_esw
*esw
, u32 val
, unsigned reg
)
247 __raw_writel(val
, esw
->base
+ reg
);
250 static inline u32
esw_r32(struct rt305x_esw
*esw
, unsigned reg
)
252 return __raw_readl(esw
->base
+ reg
);
255 static inline void esw_rmw_raw(struct rt305x_esw
*esw
, unsigned reg
,
256 unsigned long mask
, unsigned long val
)
260 t
= __raw_readl(esw
->base
+ reg
) & ~mask
;
261 __raw_writel(t
| val
, esw
->base
+ reg
);
264 static void esw_reset(struct rt305x_esw
*esw
)
269 reset_control_assert(esw
->rst_esw
);
270 usleep_range(60, 120);
271 reset_control_deassert(esw
->rst_esw
);
272 /* the esw takes long to reset otherwise the board hang */
276 static void esw_reset_ephy(struct rt305x_esw
*esw
)
281 reset_control_assert(esw
->rst_ephy
);
282 usleep_range(60, 120);
283 reset_control_deassert(esw
->rst_ephy
);
284 usleep_range(60, 120);
287 static void esw_rmw(struct rt305x_esw
*esw
, unsigned reg
,
288 unsigned long mask
, unsigned long val
)
292 spin_lock_irqsave(&esw
->reg_rw_lock
, flags
);
293 esw_rmw_raw(esw
, reg
, mask
, val
);
294 spin_unlock_irqrestore(&esw
->reg_rw_lock
, flags
);
297 static u32
rt305x_mii_write(struct rt305x_esw
*esw
, u32 phy_addr
,
298 u32 phy_register
, u32 write_data
)
300 unsigned long t_start
= jiffies
;
304 if (!(esw_r32(esw
, RT305X_ESW_REG_PCR1
) &
305 RT305X_ESW_PCR1_WT_DONE
))
307 if (time_after(jiffies
, t_start
+ RT305X_ESW_PHY_TIMEOUT
)) {
313 write_data
&= 0xffff;
314 esw_w32(esw
, (write_data
<< RT305X_ESW_PCR0_WT_NWAY_DATA_S
) |
315 (phy_register
<< RT305X_ESW_PCR0_CPU_PHY_REG_S
) |
316 (phy_addr
) | RT305X_ESW_PCR0_WT_PHY_CMD
,
317 RT305X_ESW_REG_PCR0
);
321 if (esw_r32(esw
, RT305X_ESW_REG_PCR1
) &
322 RT305X_ESW_PCR1_WT_DONE
)
325 if (time_after(jiffies
, t_start
+ RT305X_ESW_PHY_TIMEOUT
)) {
332 dev_err(esw
->dev
, "ramips_eth: MDIO timeout\n");
336 static unsigned esw_get_vlan_id(struct rt305x_esw
*esw
, unsigned vlan
)
341 s
= RT305X_ESW_VLANI_VID_S
* (vlan
% 2);
342 val
= esw_r32(esw
, RT305X_ESW_REG_VLANI(vlan
/ 2));
343 val
= (val
>> s
) & RT305X_ESW_VLANI_VID_M
;
348 static void esw_set_vlan_id(struct rt305x_esw
*esw
, unsigned vlan
, unsigned vid
)
352 s
= RT305X_ESW_VLANI_VID_S
* (vlan
% 2);
354 RT305X_ESW_REG_VLANI(vlan
/ 2),
355 RT305X_ESW_VLANI_VID_M
<< s
,
356 (vid
& RT305X_ESW_VLANI_VID_M
) << s
);
359 static unsigned esw_get_pvid(struct rt305x_esw
*esw
, unsigned port
)
363 s
= RT305X_ESW_PVIDC_PVID_S
* (port
% 2);
364 val
= esw_r32(esw
, RT305X_ESW_REG_PVIDC(port
/ 2));
365 return (val
>> s
) & RT305X_ESW_PVIDC_PVID_M
;
368 static void esw_set_pvid(struct rt305x_esw
*esw
, unsigned port
, unsigned pvid
)
372 s
= RT305X_ESW_PVIDC_PVID_S
* (port
% 2);
374 RT305X_ESW_REG_PVIDC(port
/ 2),
375 RT305X_ESW_PVIDC_PVID_M
<< s
,
376 (pvid
& RT305X_ESW_PVIDC_PVID_M
) << s
);
379 static unsigned esw_get_vmsc(struct rt305x_esw
*esw
, unsigned vlan
)
383 s
= RT305X_ESW_VMSC_MSC_S
* (vlan
% 4);
384 val
= esw_r32(esw
, RT305X_ESW_REG_VMSC(vlan
/ 4));
385 val
= (val
>> s
) & RT305X_ESW_VMSC_MSC_M
;
390 static void esw_set_vmsc(struct rt305x_esw
*esw
, unsigned vlan
, unsigned msc
)
394 s
= RT305X_ESW_VMSC_MSC_S
* (vlan
% 4);
396 RT305X_ESW_REG_VMSC(vlan
/ 4),
397 RT305X_ESW_VMSC_MSC_M
<< s
,
398 (msc
& RT305X_ESW_VMSC_MSC_M
) << s
);
401 static unsigned esw_get_port_disable(struct rt305x_esw
*esw
)
405 reg
= esw_r32(esw
, RT305X_ESW_REG_POC0
);
406 return (reg
>> RT305X_ESW_POC0_DIS_PORT_S
) &
407 RT305X_ESW_POC0_DIS_PORT_M
;
410 static void esw_set_port_disable(struct rt305x_esw
*esw
, unsigned disable_mask
)
413 unsigned enable_mask
;
417 old_mask
= esw_get_port_disable(esw
);
418 changed
= old_mask
^ disable_mask
;
419 enable_mask
= old_mask
& disable_mask
;
421 /* enable before writing to MII */
422 esw_rmw(esw
, RT305X_ESW_REG_POC0
,
423 (RT305X_ESW_POC0_DIS_PORT_M
<<
424 RT305X_ESW_POC0_DIS_PORT_S
),
425 enable_mask
<< RT305X_ESW_POC0_DIS_PORT_S
);
427 for (i
= 0; i
< RT305X_ESW_NUM_LEDS
; i
++) {
428 if (!(changed
& (1 << i
)))
430 if (disable_mask
& (1 << i
)) {
432 rt305x_mii_write(esw
, i
, MII_BMCR
,
436 rt305x_mii_write(esw
, i
, MII_BMCR
,
444 /* disable after writing to MII */
445 esw_rmw(esw
, RT305X_ESW_REG_POC0
,
446 (RT305X_ESW_POC0_DIS_PORT_M
<<
447 RT305X_ESW_POC0_DIS_PORT_S
),
448 disable_mask
<< RT305X_ESW_POC0_DIS_PORT_S
);
451 static void esw_set_gsc(struct rt305x_esw
*esw
)
453 esw_rmw(esw
, RT305X_ESW_REG_SGC
,
454 RT305X_ESW_GSC_BC_STROM_MASK
<< RT305X_ESW_GSC_BC_STROM_SHIFT
,
455 esw
->bc_storm_protect
<< RT305X_ESW_GSC_BC_STROM_SHIFT
);
456 esw_rmw(esw
, RT305X_ESW_REG_SGC
,
457 RT305X_ESW_GSC_LED_FREQ_MASK
<< RT305X_ESW_GSC_LED_FREQ_SHIFT
,
458 esw
->led_frequency
<< RT305X_ESW_GSC_LED_FREQ_SHIFT
);
461 static int esw_apply_config(struct switch_dev
*dev
);
463 static void esw_hw_init(struct rt305x_esw
*esw
)
467 u8 port_map
= RT305X_ESW_PMAP_LLLLLL
;
471 /* vodoo from original driver */
472 esw_w32(esw
, 0xC8A07850, RT305X_ESW_REG_FCT0
);
473 esw_w32(esw
, 0x00000000, RT305X_ESW_REG_SGC2
);
474 /* Port priority 1 for all ports, vlan enabled. */
475 esw_w32(esw
, 0x00005555 |
476 (RT305X_ESW_PORTS_ALL
<< RT305X_ESW_PFC1_EN_VLAN_S
),
477 RT305X_ESW_REG_PFC1
);
479 /* Enable all ports, Back Pressure and Flow Control */
480 esw_w32(esw
, ((RT305X_ESW_PORTS_ALL
<< RT305X_ESW_POC0_EN_BP_S
) |
481 (RT305X_ESW_PORTS_ALL
<< RT305X_ESW_POC0_EN_FC_S
)),
482 RT305X_ESW_REG_POC0
);
484 /* Enable Aging, and VLAN TAG removal */
485 esw_w32(esw
, ((RT305X_ESW_PORTS_ALL
<< RT305X_ESW_POC2_ENAGING_S
) |
486 (RT305X_ESW_PORTS_NOCPU
<< RT305X_ESW_POC2_UNTAG_EN_S
)),
487 RT305X_ESW_REG_POC2
);
489 if (esw
->reg_initval_fct2
)
490 esw_w32(esw
, esw
->reg_initval_fct2
, RT305X_ESW_REG_FCT2
);
492 esw_w32(esw
, 0x0002500c, RT305X_ESW_REG_FCT2
);
494 /* 300s aging timer, max packet len 1536, broadcast storm prevention
495 * disabled, disable collision abort, mac xor48 hash, 10 packet back
496 * pressure jam, GMII disable was_transmit, back pressure disabled,
497 * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
500 esw_w32(esw
, 0x0008a301, RT305X_ESW_REG_SGC
);
502 /* Setup SoC Port control register */
504 (RT305X_ESW_SOCPC_CRC_PADDING
|
505 (RT305X_ESW_PORTS_CPU
<< RT305X_ESW_SOCPC_DISUN2CPU_S
) |
506 (RT305X_ESW_PORTS_CPU
<< RT305X_ESW_SOCPC_DISMC2CPU_S
) |
507 (RT305X_ESW_PORTS_CPU
<< RT305X_ESW_SOCPC_DISBC2CPU_S
)),
508 RT305X_ESW_REG_SOCPC
);
510 /* ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
511 * turbo mii off, rgmi 3.3v off
513 * port6: enabled, gige, full-duplex, rx/tx-flow-control
515 if (esw
->reg_initval_fpa2
)
516 esw_w32(esw
, esw
->reg_initval_fpa2
, RT305X_ESW_REG_FPA2
);
518 esw_w32(esw
, 0x3f502b28, RT305X_ESW_REG_FPA2
);
519 esw_w32(esw
, 0x00000000, RT305X_ESW_REG_FPA
);
521 /* Force Link/Activity on ports */
522 esw_w32(esw
, RT305X_ESW_LED_LINKACT
, RT305X_ESW_REG_P0LED
);
523 esw_w32(esw
, RT305X_ESW_LED_LINKACT
, RT305X_ESW_REG_P1LED
);
524 esw_w32(esw
, RT305X_ESW_LED_LINKACT
, RT305X_ESW_REG_P2LED
);
525 esw_w32(esw
, RT305X_ESW_LED_LINKACT
, RT305X_ESW_REG_P3LED
);
526 esw_w32(esw
, RT305X_ESW_LED_LINKACT
, RT305X_ESW_REG_P4LED
);
528 /* Copy disabled port configuration from device tree setup */
529 port_disable
= esw
->port_disable
;
531 /* Disable nonexistent ports by reading the switch config
532 * after having enabled all possible ports above
534 port_disable
|= esw_get_port_disable(esw
);
536 for (i
= 0; i
< 6; i
++)
537 esw
->ports
[i
].disable
= (port_disable
& (1 << i
)) != 0;
539 if (ralink_soc
== RT305X_SOC_RT3352
) {
542 rt305x_mii_write(esw
, 0, 31, 0x8000);
543 for (i
= 0; i
< 5; i
++) {
544 if (esw
->ports
[i
].disable
) {
545 rt305x_mii_write(esw
, i
, MII_BMCR
, BMCR_PDOWN
);
547 rt305x_mii_write(esw
, i
, MII_BMCR
,
552 /* TX10 waveform coefficient LSB=0 disable PHY */
553 rt305x_mii_write(esw
, i
, 26, 0x1601);
554 /* TX100/TX10 AD/DA current bias */
555 rt305x_mii_write(esw
, i
, 29, 0x7016);
556 /* TX100 slew rate control */
557 rt305x_mii_write(esw
, i
, 30, 0x0038);
560 /* select global register */
561 rt305x_mii_write(esw
, 0, 31, 0x0);
562 /* enlarge agcsel threshold 3 and threshold 2 */
563 rt305x_mii_write(esw
, 0, 1, 0x4a40);
564 /* enlarge agcsel threshold 5 and threshold 4 */
565 rt305x_mii_write(esw
, 0, 2, 0x6254);
566 /* enlarge agcsel threshold */
567 rt305x_mii_write(esw
, 0, 3, 0xa17f);
568 rt305x_mii_write(esw
, 0, 12, 0x7eaa);
569 /* longer TP_IDL tail length */
570 rt305x_mii_write(esw
, 0, 14, 0x65);
571 /* increased squelch pulse count threshold. */
572 rt305x_mii_write(esw
, 0, 16, 0x0684);
573 /* set TX10 signal amplitude threshold to minimum */
574 rt305x_mii_write(esw
, 0, 17, 0x0fe0);
575 /* set squelch amplitude to higher threshold */
576 rt305x_mii_write(esw
, 0, 18, 0x40ba);
577 /* tune TP_IDL tail and head waveform, enable power
578 * down slew rate control
580 rt305x_mii_write(esw
, 0, 22, 0x253f);
581 /* set PLL/Receive bias current are calibrated */
582 rt305x_mii_write(esw
, 0, 27, 0x2fda);
583 /* change PLL/Receive bias current to internal(RT3350) */
584 rt305x_mii_write(esw
, 0, 28, 0xc410);
585 /* change PLL bias current to internal(RT3052_MP3) */
586 rt305x_mii_write(esw
, 0, 29, 0x598b);
587 /* select local register */
588 rt305x_mii_write(esw
, 0, 31, 0x8000);
589 } else if (ralink_soc
== RT305X_SOC_RT5350
) {
592 /* set the led polarity */
593 esw_w32(esw
, esw
->reg_led_polarity
& 0x1F,
594 RT5350_EWS_REG_LED_CONTROL
);
596 /* local registers */
597 rt305x_mii_write(esw
, 0, 31, 0x8000);
598 for (i
= 0; i
< 5; i
++) {
599 if (esw
->ports
[i
].disable
) {
600 rt305x_mii_write(esw
, i
, MII_BMCR
, BMCR_PDOWN
);
602 rt305x_mii_write(esw
, i
, MII_BMCR
,
607 /* TX10 waveform coefficient LSB=0 disable PHY */
608 rt305x_mii_write(esw
, i
, 26, 0x1601);
609 /* TX100/TX10 AD/DA current bias */
610 rt305x_mii_write(esw
, i
, 29, 0x7015);
611 /* TX100 slew rate control */
612 rt305x_mii_write(esw
, i
, 30, 0x0038);
615 /* global registers */
616 rt305x_mii_write(esw
, 0, 31, 0x0);
617 /* enlarge agcsel threshold 3 and threshold 2 */
618 rt305x_mii_write(esw
, 0, 1, 0x4a40);
619 /* enlarge agcsel threshold 5 and threshold 4 */
620 rt305x_mii_write(esw
, 0, 2, 0x6254);
621 /* enlarge agcsel threshold 6 */
622 rt305x_mii_write(esw
, 0, 3, 0xa17f);
623 rt305x_mii_write(esw
, 0, 12, 0x7eaa);
624 /* longer TP_IDL tail length */
625 rt305x_mii_write(esw
, 0, 14, 0x65);
626 /* increased squelch pulse count threshold. */
627 rt305x_mii_write(esw
, 0, 16, 0x0684);
628 /* set TX10 signal amplitude threshold to minimum */
629 rt305x_mii_write(esw
, 0, 17, 0x0fe0);
630 /* set squelch amplitude to higher threshold */
631 rt305x_mii_write(esw
, 0, 18, 0x40ba);
632 /* tune TP_IDL tail and head waveform, enable power
633 * down slew rate control
635 rt305x_mii_write(esw
, 0, 22, 0x253f);
636 /* set PLL/Receive bias current are calibrated */
637 rt305x_mii_write(esw
, 0, 27, 0x2fda);
638 /* change PLL/Receive bias current to internal(RT3350) */
639 rt305x_mii_write(esw
, 0, 28, 0xc410);
640 /* change PLL bias current to internal(RT3052_MP3) */
641 rt305x_mii_write(esw
, 0, 29, 0x598b);
642 /* select local register */
643 rt305x_mii_write(esw
, 0, 31, 0x8000);
644 } else if (ralink_soc
== MT762X_SOC_MT7628AN
|| ralink_soc
== MT762X_SOC_MT7688
) {
649 /* set the led polarity and led source */
650 esw_w32(esw
, (esw
->reg_led_polarity
& 0x1F) |
651 ((esw
->reg_led_source
<< 8) & 0x700),
652 RT5350_EWS_REG_LED_CONTROL
);
654 rt305x_mii_write(esw
, 0, 31, 0x2000); /* change G2 page */
655 rt305x_mii_write(esw
, 0, 26, 0x0020);
657 for (i
= 0; i
< 5; i
++) {
658 rt305x_mii_write(esw
, i
, 31, 0x8000);
659 rt305x_mii_write(esw
, i
, 0, 0x3100);
660 rt305x_mii_write(esw
, i
, 30, 0xa000);
661 rt305x_mii_write(esw
, i
, 31, 0xa000);
662 rt305x_mii_write(esw
, i
, 16, 0x0606);
663 rt305x_mii_write(esw
, i
, 23, 0x0f0e);
664 rt305x_mii_write(esw
, i
, 24, 0x1610);
665 rt305x_mii_write(esw
, i
, 30, 0x1f15);
666 rt305x_mii_write(esw
, i
, 28, 0x6111);
667 rt305x_mii_write(esw
, i
, 31, 0x2000);
668 rt305x_mii_write(esw
, i
, 26, 0x0000);
671 /* 100Base AOI setting */
672 rt305x_mii_write(esw
, 0, 31, 0x5000);
673 rt305x_mii_write(esw
, 0, 19, 0x004a);
674 rt305x_mii_write(esw
, 0, 20, 0x015a);
675 rt305x_mii_write(esw
, 0, 21, 0x00ee);
676 rt305x_mii_write(esw
, 0, 22, 0x0033);
677 rt305x_mii_write(esw
, 0, 23, 0x020a);
678 rt305x_mii_write(esw
, 0, 24, 0x0000);
679 rt305x_mii_write(esw
, 0, 25, 0x024a);
680 rt305x_mii_write(esw
, 0, 26, 0x035a);
681 rt305x_mii_write(esw
, 0, 27, 0x02ee);
682 rt305x_mii_write(esw
, 0, 28, 0x0233);
683 rt305x_mii_write(esw
, 0, 29, 0x000a);
684 rt305x_mii_write(esw
, 0, 30, 0x0000);
686 rt305x_mii_write(esw
, 0, 31, 0x8000);
687 for (i
= 0; i
< 5; i
++) {
688 if (esw
->ports
[i
].disable
) {
689 rt305x_mii_write(esw
, i
, MII_BMCR
, BMCR_PDOWN
);
691 rt305x_mii_write(esw
, i
, MII_BMCR
,
696 /* TX10 waveform coefficient */
697 rt305x_mii_write(esw
, i
, 26, 0x1601);
698 /* TX100/TX10 AD/DA current bias */
699 rt305x_mii_write(esw
, i
, 29, 0x7058);
700 /* TX100 slew rate control */
701 rt305x_mii_write(esw
, i
, 30, 0x0018);
705 /* select global register */
706 rt305x_mii_write(esw
, 0, 31, 0x0);
707 /* tune TP_IDL tail and head waveform */
708 rt305x_mii_write(esw
, 0, 22, 0x052f);
709 /* set TX10 signal amplitude threshold to minimum */
710 rt305x_mii_write(esw
, 0, 17, 0x0fe0);
711 /* set squelch amplitude to higher threshold */
712 rt305x_mii_write(esw
, 0, 18, 0x40ba);
713 /* longer TP_IDL tail length */
714 rt305x_mii_write(esw
, 0, 14, 0x65);
715 /* select local register */
716 rt305x_mii_write(esw
, 0, 31, 0x8000);
720 port_map
= esw
->port_map
;
722 port_map
= RT305X_ESW_PMAP_LLLLLL
;
724 /* Unused HW feature, but still nice to be consistent here...
725 * This is also exported to userspace ('lan' attribute) so it's
726 * conveniently usable to decide which ports go into the wan vlan by
729 esw_rmw(esw
, RT305X_ESW_REG_SGC2
,
730 RT305X_ESW_SGC2_LAN_PMAP_M
<< RT305X_ESW_SGC2_LAN_PMAP_S
,
731 port_map
<< RT305X_ESW_SGC2_LAN_PMAP_S
);
733 /* make the switch leds blink */
734 for (i
= 0; i
< RT305X_ESW_NUM_LEDS
; i
++)
735 esw
->ports
[i
].led
= 0x05;
737 /* Apply the empty config. */
738 esw_apply_config(&esw
->swdev
);
740 /* Only unmask the port change interrupt */
741 esw_w32(esw
, ~RT305X_ESW_PORT_ST_CHG
, RT305X_ESW_REG_IMR
);
745 int rt3050_esw_has_carrier(struct fe_priv
*priv
)
747 struct rt305x_esw
*esw
= priv
->soc
->swpriv
;
752 link
= esw_r32(esw
, RT305X_ESW_REG_POA
);
753 link
>>= RT305X_ESW_POA_LINK_SHIFT
;
754 cpuport
= link
& BIT(RT305X_ESW_PORT6
);
755 link
&= RT305X_ESW_POA_LINK_MASK
;
756 for (i
= 0; i
<= RT305X_ESW_PORT5
; i
++) {
757 if (priv
->link
[i
] != (link
& BIT(i
)))
758 dev_info(esw
->dev
, "port %d link %s\n", i
, link
& BIT(i
) ? "up" : "down");
759 priv
->link
[i
] = link
& BIT(i
);
762 return !!link
&& cpuport
;
765 static irqreturn_t
esw_interrupt(int irq
, void *_esw
)
767 struct rt305x_esw
*esw
= (struct rt305x_esw
*) _esw
;
770 status
= esw_r32(esw
, RT305X_ESW_REG_ISR
);
771 if (status
& RT305X_ESW_PORT_ST_CHG
) {
774 if (rt3050_esw_has_carrier(esw
->priv
))
775 netif_carrier_on(esw
->priv
->netdev
);
777 netif_carrier_off(esw
->priv
->netdev
);
781 esw_w32(esw
, status
, RT305X_ESW_REG_ISR
);
786 static int esw_apply_config(struct switch_dev
*dev
)
788 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
795 for (i
= 0; i
< RT305X_ESW_NUM_VLANS
; i
++) {
797 if (esw
->global_vlan_enable
) {
798 vid
= esw
->vlans
[i
].vid
;
799 vmsc
= esw
->vlans
[i
].ports
;
801 vid
= RT305X_ESW_VLAN_NONE
;
802 vmsc
= RT305X_ESW_PORTS_NONE
;
804 esw_set_vlan_id(esw
, i
, vid
);
805 esw_set_vmsc(esw
, i
, vmsc
);
808 for (i
= 0; i
< RT305X_ESW_NUM_PORTS
; i
++) {
810 disable
|= esw
->ports
[i
].disable
<< i
;
811 if (esw
->global_vlan_enable
) {
812 doubletag
|= esw
->ports
[i
].doubletag
<< i
;
814 untag
|= esw
->ports
[i
].untag
<< i
;
815 pvid
= esw
->ports
[i
].pvid
;
817 int x
= esw
->alt_vlan_disable
? 0 : 1;
823 esw_set_pvid(esw
, i
, pvid
);
824 if (i
< RT305X_ESW_NUM_LEDS
)
825 esw_w32(esw
, esw
->ports
[i
].led
,
826 RT305X_ESW_REG_P0LED
+ 4*i
);
830 esw_set_port_disable(esw
, disable
);
831 esw_rmw(esw
, RT305X_ESW_REG_SGC2
,
832 (RT305X_ESW_SGC2_DOUBLE_TAG_M
<<
833 RT305X_ESW_SGC2_DOUBLE_TAG_S
),
834 doubletag
<< RT305X_ESW_SGC2_DOUBLE_TAG_S
);
835 esw_rmw(esw
, RT305X_ESW_REG_PFC1
,
836 RT305X_ESW_PFC1_EN_VLAN_M
<< RT305X_ESW_PFC1_EN_VLAN_S
,
837 en_vlan
<< RT305X_ESW_PFC1_EN_VLAN_S
);
838 esw_rmw(esw
, RT305X_ESW_REG_POC2
,
839 RT305X_ESW_POC2_UNTAG_EN_M
<< RT305X_ESW_POC2_UNTAG_EN_S
,
840 untag
<< RT305X_ESW_POC2_UNTAG_EN_S
);
842 if (!esw
->global_vlan_enable
) {
844 * Still need to put all ports into vlan 0 or they'll be
846 * NOTE: vlan 0 is special, no vlan tag is prepended
848 esw_set_vlan_id(esw
, 0, 0);
849 esw_set_vmsc(esw
, 0, RT305X_ESW_PORTS_ALL
);
855 static int esw_reset_switch(struct switch_dev
*dev
)
857 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
859 esw
->global_vlan_enable
= 0;
860 memset(esw
->ports
, 0, sizeof(esw
->ports
));
861 memset(esw
->vlans
, 0, sizeof(esw
->vlans
));
867 static int esw_get_vlan_enable(struct switch_dev
*dev
,
868 const struct switch_attr
*attr
,
869 struct switch_val
*val
)
871 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
873 val
->value
.i
= esw
->global_vlan_enable
;
878 static int esw_set_vlan_enable(struct switch_dev
*dev
,
879 const struct switch_attr
*attr
,
880 struct switch_val
*val
)
882 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
884 esw
->global_vlan_enable
= val
->value
.i
!= 0;
889 static int esw_get_alt_vlan_disable(struct switch_dev
*dev
,
890 const struct switch_attr
*attr
,
891 struct switch_val
*val
)
893 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
895 val
->value
.i
= esw
->alt_vlan_disable
;
900 static int esw_set_alt_vlan_disable(struct switch_dev
*dev
,
901 const struct switch_attr
*attr
,
902 struct switch_val
*val
)
904 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
906 esw
->alt_vlan_disable
= val
->value
.i
!= 0;
912 rt305x_esw_set_bc_status(struct switch_dev
*dev
,
913 const struct switch_attr
*attr
,
914 struct switch_val
*val
)
916 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
918 esw
->bc_storm_protect
= val
->value
.i
& RT305X_ESW_GSC_BC_STROM_MASK
;
924 rt305x_esw_get_bc_status(struct switch_dev
*dev
,
925 const struct switch_attr
*attr
,
926 struct switch_val
*val
)
928 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
930 val
->value
.i
= esw
->bc_storm_protect
;
936 rt305x_esw_set_led_freq(struct switch_dev
*dev
,
937 const struct switch_attr
*attr
,
938 struct switch_val
*val
)
940 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
942 esw
->led_frequency
= val
->value
.i
& RT305X_ESW_GSC_LED_FREQ_MASK
;
948 rt305x_esw_get_led_freq(struct switch_dev
*dev
,
949 const struct switch_attr
*attr
,
950 struct switch_val
*val
)
952 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
954 val
->value
.i
= esw
->led_frequency
;
959 static int esw_get_port_link(struct switch_dev
*dev
,
961 struct switch_port_link
*link
)
963 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
966 if (port
< 0 || port
>= RT305X_ESW_NUM_PORTS
)
969 poa
= esw_r32(esw
, RT305X_ESW_REG_POA
) >> port
;
971 link
->link
= (poa
>> RT305X_ESW_LINK_S
) & 1;
972 link
->duplex
= (poa
>> RT305X_ESW_DUPLEX_S
) & 1;
973 if (port
< RT305X_ESW_NUM_LEDS
) {
974 speed
= (poa
>> RT305X_ESW_SPD_S
) & 1;
976 if (port
== RT305X_ESW_NUM_PORTS
- 1)
978 speed
= (poa
>> RT305X_ESW_SPD_S
) & 3;
982 link
->speed
= SWITCH_PORT_SPEED_10
;
985 link
->speed
= SWITCH_PORT_SPEED_100
;
988 case 3: /* forced gige speed can be 2 or 3 */
989 link
->speed
= SWITCH_PORT_SPEED_1000
;
992 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
999 static int esw_get_port_bool(struct switch_dev
*dev
,
1000 const struct switch_attr
*attr
,
1001 struct switch_val
*val
)
1003 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1004 int idx
= val
->port_vlan
;
1007 if (idx
< 0 || idx
>= RT305X_ESW_NUM_PORTS
)
1011 case RT305X_ESW_ATTR_PORT_DISABLE
:
1012 reg
= RT305X_ESW_REG_POC0
;
1013 shift
= RT305X_ESW_POC0_DIS_PORT_S
;
1015 case RT305X_ESW_ATTR_PORT_DOUBLETAG
:
1016 reg
= RT305X_ESW_REG_SGC2
;
1017 shift
= RT305X_ESW_SGC2_DOUBLE_TAG_S
;
1019 case RT305X_ESW_ATTR_PORT_UNTAG
:
1020 reg
= RT305X_ESW_REG_POC2
;
1021 shift
= RT305X_ESW_POC2_UNTAG_EN_S
;
1023 case RT305X_ESW_ATTR_PORT_LAN
:
1024 reg
= RT305X_ESW_REG_SGC2
;
1025 shift
= RT305X_ESW_SGC2_LAN_PMAP_S
;
1026 if (idx
>= RT305X_ESW_NUM_LANWAN
)
1033 x
= esw_r32(esw
, reg
);
1034 val
->value
.i
= (x
>> (idx
+ shift
)) & 1;
1039 static int esw_set_port_bool(struct switch_dev
*dev
,
1040 const struct switch_attr
*attr
,
1041 struct switch_val
*val
)
1043 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1044 int idx
= val
->port_vlan
;
1046 if (idx
< 0 || idx
>= RT305X_ESW_NUM_PORTS
||
1047 val
->value
.i
< 0 || val
->value
.i
> 1)
1051 case RT305X_ESW_ATTR_PORT_DISABLE
:
1052 esw
->ports
[idx
].disable
= val
->value
.i
;
1054 case RT305X_ESW_ATTR_PORT_DOUBLETAG
:
1055 esw
->ports
[idx
].doubletag
= val
->value
.i
;
1057 case RT305X_ESW_ATTR_PORT_UNTAG
:
1058 esw
->ports
[idx
].untag
= val
->value
.i
;
1067 static int esw_get_port_recv_badgood(struct switch_dev
*dev
,
1068 const struct switch_attr
*attr
,
1069 struct switch_val
*val
)
1071 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1072 int idx
= val
->port_vlan
;
1073 int shift
= attr
->id
== RT305X_ESW_ATTR_PORT_RECV_GOOD
? 0 : 16;
1076 if (idx
< 0 || idx
>= RT305X_ESW_NUM_LANWAN
)
1078 reg
= esw_r32(esw
, RT305X_ESW_REG_PXPC(idx
));
1079 val
->value
.i
= (reg
>> shift
) & 0xffff;
1085 esw_get_port_tr_badgood(struct switch_dev
*dev
,
1086 const struct switch_attr
*attr
,
1087 struct switch_val
*val
)
1089 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1091 int idx
= val
->port_vlan
;
1092 int shift
= attr
->id
== RT5350_ESW_ATTR_PORT_TR_GOOD
? 0 : 16;
1095 if ((ralink_soc
!= RT305X_SOC_RT5350
) && (ralink_soc
!= MT762X_SOC_MT7628AN
) && (ralink_soc
!= MT762X_SOC_MT7688
))
1098 if (idx
< 0 || idx
>= RT305X_ESW_NUM_LANWAN
)
1101 reg
= esw_r32(esw
, RT5350_ESW_REG_PXTPC(idx
));
1102 val
->value
.i
= (reg
>> shift
) & 0xffff;
1107 static int esw_get_port_led(struct switch_dev
*dev
,
1108 const struct switch_attr
*attr
,
1109 struct switch_val
*val
)
1111 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1112 int idx
= val
->port_vlan
;
1114 if (idx
< 0 || idx
>= RT305X_ESW_NUM_PORTS
||
1115 idx
>= RT305X_ESW_NUM_LEDS
)
1118 val
->value
.i
= esw_r32(esw
, RT305X_ESW_REG_P0LED
+ 4*idx
);
1123 static int esw_set_port_led(struct switch_dev
*dev
,
1124 const struct switch_attr
*attr
,
1125 struct switch_val
*val
)
1127 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1128 int idx
= val
->port_vlan
;
1130 if (idx
< 0 || idx
>= RT305X_ESW_NUM_LEDS
)
1133 esw
->ports
[idx
].led
= val
->value
.i
;
1138 static int esw_get_port_pvid(struct switch_dev
*dev
, int port
, int *val
)
1140 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1142 if (port
>= RT305X_ESW_NUM_PORTS
)
1145 *val
= esw_get_pvid(esw
, port
);
1150 static int esw_set_port_pvid(struct switch_dev
*dev
, int port
, int val
)
1152 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1154 if (port
>= RT305X_ESW_NUM_PORTS
)
1157 esw
->ports
[port
].pvid
= val
;
1162 static int esw_get_vlan_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1164 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1171 if (val
->port_vlan
< 0 || val
->port_vlan
>= RT305X_ESW_NUM_VIDS
)
1175 for (i
= 0; i
< RT305X_ESW_NUM_VLANS
; i
++) {
1176 if (esw_get_vlan_id(esw
, i
) == val
->port_vlan
&&
1177 esw_get_vmsc(esw
, i
) != RT305X_ESW_PORTS_NONE
) {
1186 vmsc
= esw_get_vmsc(esw
, vlan_idx
);
1187 poc2
= esw_r32(esw
, RT305X_ESW_REG_POC2
);
1189 for (i
= 0; i
< RT305X_ESW_NUM_PORTS
; i
++) {
1190 struct switch_port
*p
;
1191 int port_mask
= 1 << i
;
1193 if (!(vmsc
& port_mask
))
1196 p
= &val
->value
.ports
[val
->len
++];
1198 if (poc2
& (port_mask
<< RT305X_ESW_POC2_UNTAG_EN_S
))
1201 p
->flags
= 1 << SWITCH_PORT_FLAG_TAGGED
;
1207 static int esw_set_vlan_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1209 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1214 if (val
->port_vlan
< 0 || val
->port_vlan
>= RT305X_ESW_NUM_VIDS
||
1215 val
->len
> RT305X_ESW_NUM_PORTS
)
1218 /* one of the already defined vlans? */
1219 for (i
= 0; i
< RT305X_ESW_NUM_VLANS
; i
++) {
1220 if (esw
->vlans
[i
].vid
== val
->port_vlan
&&
1221 esw
->vlans
[i
].ports
!= RT305X_ESW_PORTS_NONE
) {
1227 /* select a free slot */
1228 for (i
= 0; vlan_idx
== -1 && i
< RT305X_ESW_NUM_VLANS
; i
++) {
1229 if (esw
->vlans
[i
].ports
== RT305X_ESW_PORTS_NONE
)
1233 /* bail if all slots are in use */
1237 ports
= RT305X_ESW_PORTS_NONE
;
1238 for (i
= 0; i
< val
->len
; i
++) {
1239 struct switch_port
*p
= &val
->value
.ports
[i
];
1240 int port_mask
= 1 << p
->id
;
1241 bool untagged
= !(p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
));
1243 if (p
->id
>= RT305X_ESW_NUM_PORTS
)
1247 esw
->ports
[p
->id
].untag
= untagged
;
1249 esw
->vlans
[vlan_idx
].ports
= ports
;
1250 if (ports
== RT305X_ESW_PORTS_NONE
)
1251 esw
->vlans
[vlan_idx
].vid
= RT305X_ESW_VLAN_NONE
;
1253 esw
->vlans
[vlan_idx
].vid
= val
->port_vlan
;
1258 static const struct switch_attr esw_global
[] = {
1260 .type
= SWITCH_TYPE_INT
,
1261 .name
= "enable_vlan",
1262 .description
= "VLAN mode (1:enabled)",
1264 .id
= RT305X_ESW_ATTR_ENABLE_VLAN
,
1265 .get
= esw_get_vlan_enable
,
1266 .set
= esw_set_vlan_enable
,
1269 .type
= SWITCH_TYPE_INT
,
1270 .name
= "alternate_vlan_disable",
1271 .description
= "Use en_vlan instead of doubletag to disable"
1274 .id
= RT305X_ESW_ATTR_ALT_VLAN_DISABLE
,
1275 .get
= esw_get_alt_vlan_disable
,
1276 .set
= esw_set_alt_vlan_disable
,
1279 .type
= SWITCH_TYPE_INT
,
1280 .name
= "bc_storm_protect",
1281 .description
= "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1283 .id
= RT305X_ESW_ATTR_BC_STATUS
,
1284 .get
= rt305x_esw_get_bc_status
,
1285 .set
= rt305x_esw_set_bc_status
,
1288 .type
= SWITCH_TYPE_INT
,
1289 .name
= "led_frequency",
1290 .description
= "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1292 .id
= RT305X_ESW_ATTR_LED_FREQ
,
1293 .get
= rt305x_esw_get_led_freq
,
1294 .set
= rt305x_esw_set_led_freq
,
1298 static const struct switch_attr esw_port
[] = {
1300 .type
= SWITCH_TYPE_INT
,
1302 .description
= "Port state (1:disabled)",
1304 .id
= RT305X_ESW_ATTR_PORT_DISABLE
,
1305 .get
= esw_get_port_bool
,
1306 .set
= esw_set_port_bool
,
1309 .type
= SWITCH_TYPE_INT
,
1310 .name
= "doubletag",
1311 .description
= "Double tagging for incoming vlan packets "
1314 .id
= RT305X_ESW_ATTR_PORT_DOUBLETAG
,
1315 .get
= esw_get_port_bool
,
1316 .set
= esw_set_port_bool
,
1319 .type
= SWITCH_TYPE_INT
,
1321 .description
= "Untag (1:strip outgoing vlan tag)",
1323 .id
= RT305X_ESW_ATTR_PORT_UNTAG
,
1324 .get
= esw_get_port_bool
,
1325 .set
= esw_set_port_bool
,
1328 .type
= SWITCH_TYPE_INT
,
1330 .description
= "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1331 " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1332 " 8:100mact, 10:blink, 11:off, 12:on)",
1334 .id
= RT305X_ESW_ATTR_PORT_LED
,
1335 .get
= esw_get_port_led
,
1336 .set
= esw_set_port_led
,
1339 .type
= SWITCH_TYPE_INT
,
1341 .description
= "HW port group (0:wan, 1:lan)",
1343 .id
= RT305X_ESW_ATTR_PORT_LAN
,
1344 .get
= esw_get_port_bool
,
1347 .type
= SWITCH_TYPE_INT
,
1349 .description
= "Receive bad packet counter",
1350 .id
= RT305X_ESW_ATTR_PORT_RECV_BAD
,
1351 .get
= esw_get_port_recv_badgood
,
1354 .type
= SWITCH_TYPE_INT
,
1355 .name
= "recv_good",
1356 .description
= "Receive good packet counter",
1357 .id
= RT305X_ESW_ATTR_PORT_RECV_GOOD
,
1358 .get
= esw_get_port_recv_badgood
,
1361 .type
= SWITCH_TYPE_INT
,
1364 .description
= "Transmit bad packet counter. rt5350 only",
1365 .id
= RT5350_ESW_ATTR_PORT_TR_BAD
,
1366 .get
= esw_get_port_tr_badgood
,
1369 .type
= SWITCH_TYPE_INT
,
1372 .description
= "Transmit good packet counter. rt5350 only",
1373 .id
= RT5350_ESW_ATTR_PORT_TR_GOOD
,
1374 .get
= esw_get_port_tr_badgood
,
1378 static const struct switch_attr esw_vlan
[] = {
1381 static const struct switch_dev_ops esw_ops
= {
1384 .n_attr
= ARRAY_SIZE(esw_global
),
1388 .n_attr
= ARRAY_SIZE(esw_port
),
1392 .n_attr
= ARRAY_SIZE(esw_vlan
),
1394 .get_vlan_ports
= esw_get_vlan_ports
,
1395 .set_vlan_ports
= esw_set_vlan_ports
,
1396 .get_port_pvid
= esw_get_port_pvid
,
1397 .set_port_pvid
= esw_set_port_pvid
,
1398 .get_port_link
= esw_get_port_link
,
1399 .apply_config
= esw_apply_config
,
1400 .reset_switch
= esw_reset_switch
,
1403 static int esw_probe(struct platform_device
*pdev
)
1405 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1406 struct device_node
*np
= pdev
->dev
.of_node
;
1407 const __be32
*port_map
, *port_disable
, *reg_init
;
1408 struct rt305x_esw
*esw
;
1410 esw
= devm_kzalloc(&pdev
->dev
, sizeof(*esw
), GFP_KERNEL
);
1414 esw
->dev
= &pdev
->dev
;
1415 esw
->irq
= irq_of_parse_and_map(np
, 0);
1416 esw
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
1417 if (IS_ERR(esw
->base
))
1418 return PTR_ERR(esw
->base
);
1420 port_map
= of_get_property(np
, "mediatek,portmap", NULL
);
1422 esw
->port_map
= be32_to_cpu(*port_map
);
1424 port_disable
= of_get_property(np
, "mediatek,portdisable", NULL
);
1426 esw
->port_disable
= be32_to_cpu(*port_disable
);
1428 reg_init
= of_get_property(np
, "ralink,fct2", NULL
);
1430 esw
->reg_initval_fct2
= be32_to_cpu(*reg_init
);
1432 reg_init
= of_get_property(np
, "ralink,fpa2", NULL
);
1434 esw
->reg_initval_fpa2
= be32_to_cpu(*reg_init
);
1436 reg_init
= of_get_property(np
, "mediatek,led_polarity", NULL
);
1438 esw
->reg_led_polarity
= be32_to_cpu(*reg_init
);
1440 reg_init
= of_get_property(np
, "mediatek,led_source", NULL
);
1442 esw
->reg_led_source
= be32_to_cpu(*reg_init
);
1444 esw
->rst_esw
= devm_reset_control_get(&pdev
->dev
, "esw");
1445 if (IS_ERR(esw
->rst_esw
))
1446 esw
->rst_esw
= NULL
;
1447 esw
->rst_ephy
= devm_reset_control_get(&pdev
->dev
, "ephy");
1448 if (IS_ERR(esw
->rst_ephy
))
1449 esw
->rst_ephy
= NULL
;
1451 spin_lock_init(&esw
->reg_rw_lock
);
1452 platform_set_drvdata(pdev
, esw
);
1457 static int esw_remove(struct platform_device
*pdev
)
1459 struct rt305x_esw
*esw
= platform_get_drvdata(pdev
);
1462 esw_w32(esw
, ~0, RT305X_ESW_REG_IMR
);
1463 platform_set_drvdata(pdev
, NULL
);
1469 static const struct of_device_id ralink_esw_match
[] = {
1470 { .compatible
= "ralink,rt3050-esw" },
1473 MODULE_DEVICE_TABLE(of
, ralink_esw_match
);
1475 /* called by the ethernet driver to bound with the switch driver */
1476 int rt3050_esw_init(struct fe_priv
*priv
)
1478 struct device_node
*np
= priv
->switch_np
;
1479 struct platform_device
*pdev
= of_find_device_by_node(np
);
1480 struct switch_dev
*swdev
;
1481 struct rt305x_esw
*esw
;
1482 const __be32
*rgmii
;
1488 if (!of_device_is_compatible(np
, ralink_esw_match
->compatible
))
1491 esw
= platform_get_drvdata(pdev
);
1493 return -EPROBE_DEFER
;
1495 priv
->soc
->swpriv
= esw
;
1500 rgmii
= of_get_property(np
, "ralink,rgmii", NULL
);
1501 if (rgmii
&& be32_to_cpu(*rgmii
) == 1) {
1503 * External switch connected to RGMII interface.
1504 * Unregister the switch device after initialization.
1506 dev_err(&pdev
->dev
, "RGMII mode, not exporting switch device.\n");
1507 unregister_switch(&esw
->swdev
);
1508 platform_set_drvdata(pdev
, NULL
);
1512 swdev
= &esw
->swdev
;
1513 swdev
->of_node
= pdev
->dev
.of_node
;
1514 swdev
->name
= "rt305x-esw";
1515 swdev
->alias
= "rt305x";
1516 swdev
->cpu_port
= RT305X_ESW_PORT6
;
1517 swdev
->ports
= RT305X_ESW_NUM_PORTS
;
1518 swdev
->vlans
= RT305X_ESW_NUM_VIDS
;
1519 swdev
->ops
= &esw_ops
;
1521 ret
= register_switch(swdev
, NULL
);
1523 dev_err(&pdev
->dev
, "register_switch failed\n");
1527 ret
= devm_request_irq(&pdev
->dev
, esw
->irq
, esw_interrupt
, 0, "esw",
1530 esw_w32(esw
, RT305X_ESW_PORT_ST_CHG
, RT305X_ESW_REG_ISR
);
1531 esw_w32(esw
, ~RT305X_ESW_PORT_ST_CHG
, RT305X_ESW_REG_IMR
);
1534 dev_info(&pdev
->dev
, "mediatek esw at 0x%08lx, irq %d initialized\n",
1535 (long unsigned int)esw
->base
, esw
->irq
);
1540 static struct platform_driver esw_driver
= {
1542 .remove
= esw_remove
,
1544 .name
= "rt3050-esw",
1545 .owner
= THIS_MODULE
,
1546 .of_match_table
= ralink_esw_match
,
1550 module_platform_driver(esw_driver
);
1552 MODULE_LICENSE("GPL");
1553 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1554 MODULE_DESCRIPTION("Switch driver for RT305X SoC");
1555 MODULE_VERSION(MTK_FE_DRV_VERSION
);