projects / openwrt / staging / stintel.git / blob
? search:


47471eb1973e8e0352769538378c4250be8bcc1f
[openwrt/staging/stintel.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / esw_rt3050.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 * Copyright (C) 2016 Vittorio Gambaletta <openwrt@vittgam.net>
14 */
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/platform_device.h>
19 #include <asm/mach-ralink/ralink_regs.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22
23 #include <linux/switch.h>
24 #include <linux/reset.h>
25
26 #include "mtk_eth_soc.h"
27 #include "esw_rt3050.h"
28
29 /* HW limitations for this switch:
30 * - No large frame support (PKT_MAX_LEN at most 1536)
31 * - Can't have untagged vlan and tagged vlan on one port at the same time,
32 * though this might be possible using the undocumented PPE.
33 */
34
35 #define RT305X_ESW_REG_ISR 0x00
36 #define RT305X_ESW_REG_IMR 0x04
37 #define RT305X_ESW_REG_FCT0 0x08
38 #define RT305X_ESW_REG_PFC1 0x14
39 #define RT305X_ESW_REG_ATS 0x24
40 #define RT305X_ESW_REG_ATS0 0x28
41 #define RT305X_ESW_REG_ATS1 0x2c
42 #define RT305X_ESW_REG_ATS2 0x30
43 #define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
44 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
45 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
46 #define RT305X_ESW_REG_POA 0x80
47 #define RT305X_ESW_REG_FPA 0x84
48 #define RT305X_ESW_REG_SOCPC 0x8c
49 #define RT305X_ESW_REG_POC0 0x90
50 #define RT305X_ESW_REG_POC1 0x94
51 #define RT305X_ESW_REG_POC2 0x98
52 #define RT305X_ESW_REG_SGC 0x9c
53 #define RT305X_ESW_REG_STRT 0xa0
54 #define RT305X_ESW_REG_PCR0 0xc0
55 #define RT305X_ESW_REG_PCR1 0xc4
56 #define RT305X_ESW_REG_FPA2 0xc8
57 #define RT305X_ESW_REG_FCT2 0xcc
58 #define RT305X_ESW_REG_SGC2 0xe4
59 #define RT305X_ESW_REG_P0LED 0xa4
60 #define RT305X_ESW_REG_P1LED 0xa8
61 #define RT305X_ESW_REG_P2LED 0xac
62 #define RT305X_ESW_REG_P3LED 0xb0
63 #define RT305X_ESW_REG_P4LED 0xb4
64 #define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
65 #define RT305X_ESW_REG_P1PC 0xec
66 #define RT305X_ESW_REG_P2PC 0xf0
67 #define RT305X_ESW_REG_P3PC 0xf4
68 #define RT305X_ESW_REG_P4PC 0xf8
69 #define RT305X_ESW_REG_P5PC 0xfc
70
71 #define RT305X_ESW_LED_LINK 0
72 #define RT305X_ESW_LED_100M 1
73 #define RT305X_ESW_LED_DUPLEX 2
74 #define RT305X_ESW_LED_ACTIVITY 3
75 #define RT305X_ESW_LED_COLLISION 4
76 #define RT305X_ESW_LED_LINKACT 5
77 #define RT305X_ESW_LED_DUPLCOLL 6
78 #define RT305X_ESW_LED_10MACT 7
79 #define RT305X_ESW_LED_100MACT 8
80 /* Additional led states not in datasheet: */
81 #define RT305X_ESW_LED_BLINK 10
82 #define RT305X_ESW_LED_OFF 11
83 #define RT305X_ESW_LED_ON 12
84
85 #define RT305X_ESW_LINK_S 25
86 #define RT305X_ESW_DUPLEX_S 9
87 #define RT305X_ESW_SPD_S 0
88
89 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
90 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
91 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
92
93 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
94
95 #define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
96 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
97
98 #define RT305X_ESW_PVIDC_PVID_M 0xfff
99 #define RT305X_ESW_PVIDC_PVID_S 12
100
101 #define RT305X_ESW_VLANI_VID_M 0xfff
102 #define RT305X_ESW_VLANI_VID_S 12
103
104 #define RT305X_ESW_VMSC_MSC_M 0xff
105 #define RT305X_ESW_VMSC_MSC_S 8
106
107 #define RT305X_ESW_SOCPC_DISUN2CPU_S 0
108 #define RT305X_ESW_SOCPC_DISMC2CPU_S 8
109 #define RT305X_ESW_SOCPC_DISBC2CPU_S 16
110 #define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
111
112 #define RT305X_ESW_POC0_EN_BP_S 0
113 #define RT305X_ESW_POC0_EN_FC_S 8
114 #define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
115 #define RT305X_ESW_POC0_DIS_PORT_M 0x7f
116 #define RT305X_ESW_POC0_DIS_PORT_S 23
117
118 #define RT305X_ESW_POC2_UNTAG_EN_M 0xff
119 #define RT305X_ESW_POC2_UNTAG_EN_S 0
120 #define RT305X_ESW_POC2_ENAGING_S 8
121 #define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
122
123 #define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
124 #define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
125 #define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
126 #define RT305X_ESW_SGC2_LAN_PMAP_S 24
127
128 #define RT305X_ESW_PFC1_EN_VLAN_M 0xff
129 #define RT305X_ESW_PFC1_EN_VLAN_S 16
130 #define RT305X_ESW_PFC1_EN_TOS_S 24
131
132 #define RT305X_ESW_VLAN_NONE 0xfff
133
134 #define RT305X_ESW_GSC_BC_STROM_MASK 0x3
135 #define RT305X_ESW_GSC_BC_STROM_SHIFT 4
136
137 #define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
138 #define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
139
140 #define RT305X_ESW_POA_LINK_MASK 0x1f
141 #define RT305X_ESW_POA_LINK_SHIFT 25
142
143 #define RT305X_ESW_PORT_ST_CHG BIT(26)
144 #define RT305X_ESW_PORT0 0
145 #define RT305X_ESW_PORT1 1
146 #define RT305X_ESW_PORT2 2
147 #define RT305X_ESW_PORT3 3
148 #define RT305X_ESW_PORT4 4
149 #define RT305X_ESW_PORT5 5
150 #define RT305X_ESW_PORT6 6
151
152 #define RT305X_ESW_PORTS_NONE 0
153
154 #define RT305X_ESW_PMAP_LLLLLL 0x3f
155 #define RT305X_ESW_PMAP_LLLLWL 0x2f
156 #define RT305X_ESW_PMAP_WLLLLL 0x3e
157
158 #define RT305X_ESW_PORTS_INTERNAL \
159 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
160 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
161 BIT(RT305X_ESW_PORT4))
162
163 #define RT305X_ESW_PORTS_NOCPU \
164 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
165
166 #define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
167
168 #define RT305X_ESW_PORTS_ALL \
169 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
170
171 #define RT305X_ESW_NUM_VLANS 16
172 #define RT305X_ESW_NUM_VIDS 4096
173 #define RT305X_ESW_NUM_PORTS 7
174 #define RT305X_ESW_NUM_LANWAN 6
175 #define RT305X_ESW_NUM_LEDS 5
176
177 #define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
178 #define RT5350_EWS_REG_LED_CONTROL 0x168
179
180 enum {
181 /* Global attributes. */
182 RT305X_ESW_ATTR_ENABLE_VLAN,
183 RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
184 RT305X_ESW_ATTR_BC_STATUS,
185 RT305X_ESW_ATTR_LED_FREQ,
186 /* Port attributes. */
187 RT305X_ESW_ATTR_PORT_DISABLE,
188 RT305X_ESW_ATTR_PORT_DOUBLETAG,
189 RT305X_ESW_ATTR_PORT_UNTAG,
190 RT305X_ESW_ATTR_PORT_LED,
191 RT305X_ESW_ATTR_PORT_LAN,
192 RT305X_ESW_ATTR_PORT_RECV_BAD,
193 RT305X_ESW_ATTR_PORT_RECV_GOOD,
194 RT5350_ESW_ATTR_PORT_TR_BAD,
195 RT5350_ESW_ATTR_PORT_TR_GOOD,
196 };
197
198 struct esw_port {
199 bool disable;
200 bool doubletag;
201 bool untag;
202 u8 led;
203 u16 pvid;
204 };
205
206 struct esw_vlan {
207 u8 ports;
208 u16 vid;
209 };
210
211 enum {
212 RT305X_ESW_VLAN_CONFIG_NONE = 0,
213 RT305X_ESW_VLAN_CONFIG_LLLLW,
214 RT305X_ESW_VLAN_CONFIG_WLLLL,
215 };
216
217 struct rt305x_esw {
218 struct device *dev;
219 void __iomem *base;
220 int irq;
221 struct fe_priv *priv;
222
223 /* Protects against concurrent register r/w operations. */
224 spinlock_t reg_rw_lock;
225
226 unsigned char port_map;
227 unsigned char port_disable;
228 unsigned int reg_initval_fct2;
229 unsigned int reg_initval_fpa2;
230 unsigned int reg_led_polarity;
231 unsigned int reg_led_source;
232
233 struct switch_dev swdev;
234 bool global_vlan_enable;
235 bool alt_vlan_disable;
236 int bc_storm_protect;
237 int led_frequency;
238 struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
239 struct esw_port ports[RT305X_ESW_NUM_PORTS];
240 struct reset_control *rst_esw;
241 struct reset_control *rst_ephy;
242
243 };
244
245 static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
246 {
247 __raw_writel(val, esw->base + reg);
248 }
249
250 static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
251 {
252 return __raw_readl(esw->base + reg);
253 }
254
255 static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg,
256 unsigned long mask, unsigned long val)
257 {
258 unsigned long t;
259
260 t = __raw_readl(esw->base + reg) & ~mask;
261 __raw_writel(t | val, esw->base + reg);
262 }
263
264 static void esw_reset(struct rt305x_esw *esw)
265 {
266 if (!esw->rst_esw)
267 return;
268
269 reset_control_assert(esw->rst_esw);
270 usleep_range(60, 120);
271 reset_control_deassert(esw->rst_esw);
272 /* the esw takes long to reset otherwise the board hang */
273 msleep(10);
274 }
275
276 static void esw_reset_ephy(struct rt305x_esw *esw)
277 {
278 if (!esw->rst_ephy)
279 return;
280
281 reset_control_assert(esw->rst_ephy);
282 usleep_range(60, 120);
283 reset_control_deassert(esw->rst_ephy);
284 usleep_range(60, 120);
285 }
286
287 static void esw_rmw(struct rt305x_esw *esw, unsigned reg,
288 unsigned long mask, unsigned long val)
289 {
290 unsigned long flags;
291
292 spin_lock_irqsave(&esw->reg_rw_lock, flags);
293 esw_rmw_raw(esw, reg, mask, val);
294 spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
295 }
296
297 static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,
298 u32 phy_register, u32 write_data)
299 {
300 unsigned long t_start = jiffies;
301 int ret = 0;
302
303 while (1) {
304 if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
305 RT305X_ESW_PCR1_WT_DONE))
306 break;
307 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
308 ret = 1;
309 goto out;
310 }
311 }
312
313 write_data &= 0xffff;
314 esw_w32(esw, (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
315 (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
316 (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
317 RT305X_ESW_REG_PCR0);
318
319 t_start = jiffies;
320 while (1) {
321 if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
322 RT305X_ESW_PCR1_WT_DONE)
323 break;
324
325 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
326 ret = 1;
327 break;
328 }
329 }
330 out:
331 if (ret)
332 dev_err(esw->dev, "ramips_eth: MDIO timeout\n");
333 return ret;
334 }
335
336 static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
337 {
338 unsigned s;
339 unsigned val;
340
341 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
342 val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
343 val = (val >> s) & RT305X_ESW_VLANI_VID_M;
344
345 return val;
346 }
347
348 static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
349 {
350 unsigned s;
351
352 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
353 esw_rmw(esw,
354 RT305X_ESW_REG_VLANI(vlan / 2),
355 RT305X_ESW_VLANI_VID_M << s,
356 (vid & RT305X_ESW_VLANI_VID_M) << s);
357 }
358
359 static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
360 {
361 unsigned s, val;
362
363 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
364 val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
365 return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
366 }
367
368 static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
369 {
370 unsigned s;
371
372 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
373 esw_rmw(esw,
374 RT305X_ESW_REG_PVIDC(port / 2),
375 RT305X_ESW_PVIDC_PVID_M << s,
376 (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
377 }
378
379 static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
380 {
381 unsigned s, val;
382
383 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
384 val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
385 val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
386
387 return val;
388 }
389
390 static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
391 {
392 unsigned s;
393
394 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
395 esw_rmw(esw,
396 RT305X_ESW_REG_VMSC(vlan / 4),
397 RT305X_ESW_VMSC_MSC_M << s,
398 (msc & RT305X_ESW_VMSC_MSC_M) << s);
399 }
400
401 static unsigned esw_get_port_disable(struct rt305x_esw *esw)
402 {
403 unsigned reg;
404
405 reg = esw_r32(esw, RT305X_ESW_REG_POC0);
406 return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
407 RT305X_ESW_POC0_DIS_PORT_M;
408 }
409
410 static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
411 {
412 unsigned old_mask;
413 unsigned enable_mask;
414 unsigned changed;
415 int i;
416
417 old_mask = esw_get_port_disable(esw);
418 changed = old_mask ^ disable_mask;
419 enable_mask = old_mask & disable_mask;
420
421 /* enable before writing to MII */
422 esw_rmw(esw, RT305X_ESW_REG_POC0,
423 (RT305X_ESW_POC0_DIS_PORT_M <<
424 RT305X_ESW_POC0_DIS_PORT_S),
425 enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
426
427 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
428 if (!(changed & (1 << i)))
429 continue;
430 if (disable_mask & (1 << i)) {
431 /* disable */
432 rt305x_mii_write(esw, i, MII_BMCR,
433 BMCR_PDOWN);
434 } else {
435 /* enable */
436 rt305x_mii_write(esw, i, MII_BMCR,
437 BMCR_FULLDPLX |
438 BMCR_ANENABLE |
439 BMCR_ANRESTART |
440 BMCR_SPEED100);
441 }
442 }
443
444 /* disable after writing to MII */
445 esw_rmw(esw, RT305X_ESW_REG_POC0,
446 (RT305X_ESW_POC0_DIS_PORT_M <<
447 RT305X_ESW_POC0_DIS_PORT_S),
448 disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
449 }
450
451 static void esw_set_gsc(struct rt305x_esw *esw)
452 {
453 esw_rmw(esw, RT305X_ESW_REG_SGC,
454 RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
455 esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
456 esw_rmw(esw, RT305X_ESW_REG_SGC,
457 RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
458 esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
459 }
460
461 static int esw_apply_config(struct switch_dev *dev);
462
463 static void esw_hw_init(struct rt305x_esw *esw)
464 {
465 int i;
466 u8 port_disable = 0;
467 u8 port_map = RT305X_ESW_PMAP_LLLLLL;
468
469 esw_reset(esw);
470
471 /* vodoo from original driver */
472 esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
473 esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
474 /* Port priority 1 for all ports, vlan enabled. */
475 esw_w32(esw, 0x00005555 |
476 (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
477 RT305X_ESW_REG_PFC1);
478
479 /* Enable all ports, Back Pressure and Flow Control */
480 esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
481 (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
482 RT305X_ESW_REG_POC0);
483
484 /* Enable Aging, and VLAN TAG removal */
485 esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
486 (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
487 RT305X_ESW_REG_POC2);
488
489 if (esw->reg_initval_fct2)
490 esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
491 else
492 esw_w32(esw, 0x0002500c, RT305X_ESW_REG_FCT2);
493
494 /* 300s aging timer, max packet len 1536, broadcast storm prevention
495 * disabled, disable collision abort, mac xor48 hash, 10 packet back
496 * pressure jam, GMII disable was_transmit, back pressure disabled,
497 * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
498 * ports.
499 */
500 esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
501
502 /* Setup SoC Port control register */
503 esw_w32(esw,
504 (RT305X_ESW_SOCPC_CRC_PADDING |
505 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
506 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
507 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
508 RT305X_ESW_REG_SOCPC);
509
510 /* ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
511 * turbo mii off, rgmi 3.3v off
512 * port5: disabled
513 * port6: enabled, gige, full-duplex, rx/tx-flow-control
514 */
515 if (esw->reg_initval_fpa2)
516 esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
517 else
518 esw_w32(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
519 esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
520
521 /* Force Link/Activity on ports */
522 esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P0LED);
523 esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P1LED);
524 esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P2LED);
525 esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P3LED);
526 esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P4LED);
527
528 /* Copy disabled port configuration from device tree setup */
529 port_disable = esw->port_disable;
530
531 /* Disable nonexistent ports by reading the switch config
532 * after having enabled all possible ports above
533 */
534 port_disable |= esw_get_port_disable(esw);
535
536 for (i = 0; i < 6; i++)
537 esw->ports[i].disable = (port_disable & (1 << i)) != 0;
538
539 if (ralink_soc == RT305X_SOC_RT3352) {
540 esw_reset_ephy(esw);
541
542 rt305x_mii_write(esw, 0, 31, 0x8000);
543 for (i = 0; i < 5; i++) {
544 if (esw->ports[i].disable) {
545 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
546 } else {
547 rt305x_mii_write(esw, i, MII_BMCR,
548 BMCR_FULLDPLX |
549 BMCR_ANENABLE |
550 BMCR_SPEED100);
551 }
552 /* TX10 waveform coefficient LSB=0 disable PHY */
553 rt305x_mii_write(esw, i, 26, 0x1601);
554 /* TX100/TX10 AD/DA current bias */
555 rt305x_mii_write(esw, i, 29, 0x7016);
556 /* TX100 slew rate control */
557 rt305x_mii_write(esw, i, 30, 0x0038);
558 }
559
560 /* select global register */
561 rt305x_mii_write(esw, 0, 31, 0x0);
562 /* enlarge agcsel threshold 3 and threshold 2 */
563 rt305x_mii_write(esw, 0, 1, 0x4a40);
564 /* enlarge agcsel threshold 5 and threshold 4 */
565 rt305x_mii_write(esw, 0, 2, 0x6254);
566 /* enlarge agcsel threshold */
567 rt305x_mii_write(esw, 0, 3, 0xa17f);
568 rt305x_mii_write(esw, 0, 12, 0x7eaa);
569 /* longer TP_IDL tail length */
570 rt305x_mii_write(esw, 0, 14, 0x65);
571 /* increased squelch pulse count threshold. */
572 rt305x_mii_write(esw, 0, 16, 0x0684);
573 /* set TX10 signal amplitude threshold to minimum */
574 rt305x_mii_write(esw, 0, 17, 0x0fe0);
575 /* set squelch amplitude to higher threshold */
576 rt305x_mii_write(esw, 0, 18, 0x40ba);
577 /* tune TP_IDL tail and head waveform, enable power
578 * down slew rate control
579 */
580 rt305x_mii_write(esw, 0, 22, 0x253f);
581 /* set PLL/Receive bias current are calibrated */
582 rt305x_mii_write(esw, 0, 27, 0x2fda);
583 /* change PLL/Receive bias current to internal(RT3350) */
584 rt305x_mii_write(esw, 0, 28, 0xc410);
585 /* change PLL bias current to internal(RT3052_MP3) */
586 rt305x_mii_write(esw, 0, 29, 0x598b);
587 /* select local register */
588 rt305x_mii_write(esw, 0, 31, 0x8000);
589 } else if (ralink_soc == RT305X_SOC_RT5350) {
590 esw_reset_ephy(esw);
591
592 /* set the led polarity */
593 esw_w32(esw, esw->reg_led_polarity & 0x1F,
594 RT5350_EWS_REG_LED_CONTROL);
595
596 /* local registers */
597 rt305x_mii_write(esw, 0, 31, 0x8000);
598 for (i = 0; i < 5; i++) {
599 if (esw->ports[i].disable) {
600 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
601 } else {
602 rt305x_mii_write(esw, i, MII_BMCR,
603 BMCR_FULLDPLX |
604 BMCR_ANENABLE |
605 BMCR_SPEED100);
606 }
607 /* TX10 waveform coefficient LSB=0 disable PHY */
608 rt305x_mii_write(esw, i, 26, 0x1601);
609 /* TX100/TX10 AD/DA current bias */
610 rt305x_mii_write(esw, i, 29, 0x7015);
611 /* TX100 slew rate control */
612 rt305x_mii_write(esw, i, 30, 0x0038);
613 }
614
615 /* global registers */
616 rt305x_mii_write(esw, 0, 31, 0x0);
617 /* enlarge agcsel threshold 3 and threshold 2 */
618 rt305x_mii_write(esw, 0, 1, 0x4a40);
619 /* enlarge agcsel threshold 5 and threshold 4 */
620 rt305x_mii_write(esw, 0, 2, 0x6254);
621 /* enlarge agcsel threshold 6 */
622 rt305x_mii_write(esw, 0, 3, 0xa17f);
623 rt305x_mii_write(esw, 0, 12, 0x7eaa);
624 /* longer TP_IDL tail length */
625 rt305x_mii_write(esw, 0, 14, 0x65);
626 /* increased squelch pulse count threshold. */
627 rt305x_mii_write(esw, 0, 16, 0x0684);
628 /* set TX10 signal amplitude threshold to minimum */
629 rt305x_mii_write(esw, 0, 17, 0x0fe0);
630 /* set squelch amplitude to higher threshold */
631 rt305x_mii_write(esw, 0, 18, 0x40ba);
632 /* tune TP_IDL tail and head waveform, enable power
633 * down slew rate control
634 */
635 rt305x_mii_write(esw, 0, 22, 0x253f);
636 /* set PLL/Receive bias current are calibrated */
637 rt305x_mii_write(esw, 0, 27, 0x2fda);
638 /* change PLL/Receive bias current to internal(RT3350) */
639 rt305x_mii_write(esw, 0, 28, 0xc410);
640 /* change PLL bias current to internal(RT3052_MP3) */
641 rt305x_mii_write(esw, 0, 29, 0x598b);
642 /* select local register */
643 rt305x_mii_write(esw, 0, 31, 0x8000);
644 } else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
645 int i;
646
647 esw_reset_ephy(esw);
648
649 /* set the led polarity and led source */
650 esw_w32(esw, (esw->reg_led_polarity & 0x1F) |
651 ((esw->reg_led_source << 8) & 0x700),
652 RT5350_EWS_REG_LED_CONTROL);
653
654 rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */
655 rt305x_mii_write(esw, 0, 26, 0x0020);
656
657 for (i = 0; i < 5; i++) {
658 rt305x_mii_write(esw, i, 31, 0x8000);
659 rt305x_mii_write(esw, i, 0, 0x3100);
660 rt305x_mii_write(esw, i, 30, 0xa000);
661 rt305x_mii_write(esw, i, 31, 0xa000);
662 rt305x_mii_write(esw, i, 16, 0x0606);
663 rt305x_mii_write(esw, i, 23, 0x0f0e);
664 rt305x_mii_write(esw, i, 24, 0x1610);
665 rt305x_mii_write(esw, i, 30, 0x1f15);
666 rt305x_mii_write(esw, i, 28, 0x6111);
667 rt305x_mii_write(esw, i, 31, 0x2000);
668 rt305x_mii_write(esw, i, 26, 0x0000);
669 }
670
671 /* 100Base AOI setting */
672 rt305x_mii_write(esw, 0, 31, 0x5000);
673 rt305x_mii_write(esw, 0, 19, 0x004a);
674 rt305x_mii_write(esw, 0, 20, 0x015a);
675 rt305x_mii_write(esw, 0, 21, 0x00ee);
676 rt305x_mii_write(esw, 0, 22, 0x0033);
677 rt305x_mii_write(esw, 0, 23, 0x020a);
678 rt305x_mii_write(esw, 0, 24, 0x0000);
679 rt305x_mii_write(esw, 0, 25, 0x024a);
680 rt305x_mii_write(esw, 0, 26, 0x035a);
681 rt305x_mii_write(esw, 0, 27, 0x02ee);
682 rt305x_mii_write(esw, 0, 28, 0x0233);
683 rt305x_mii_write(esw, 0, 29, 0x000a);
684 rt305x_mii_write(esw, 0, 30, 0x0000);
685 } else {
686 rt305x_mii_write(esw, 0, 31, 0x8000);
687 for (i = 0; i < 5; i++) {
688 if (esw->ports[i].disable) {
689 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
690 } else {
691 rt305x_mii_write(esw, i, MII_BMCR,
692 BMCR_FULLDPLX |
693 BMCR_ANENABLE |
694 BMCR_SPEED100);
695 }
696 /* TX10 waveform coefficient */
697 rt305x_mii_write(esw, i, 26, 0x1601);
698 /* TX100/TX10 AD/DA current bias */
699 rt305x_mii_write(esw, i, 29, 0x7058);
700 /* TX100 slew rate control */
701 rt305x_mii_write(esw, i, 30, 0x0018);
702 }
703
704 /* PHY IOT */
705 /* select global register */
706 rt305x_mii_write(esw, 0, 31, 0x0);
707 /* tune TP_IDL tail and head waveform */
708 rt305x_mii_write(esw, 0, 22, 0x052f);
709 /* set TX10 signal amplitude threshold to minimum */
710 rt305x_mii_write(esw, 0, 17, 0x0fe0);
711 /* set squelch amplitude to higher threshold */
712 rt305x_mii_write(esw, 0, 18, 0x40ba);
713 /* longer TP_IDL tail length */
714 rt305x_mii_write(esw, 0, 14, 0x65);
715 /* select local register */
716 rt305x_mii_write(esw, 0, 31, 0x8000);
717 }
718
719 if (esw->port_map)
720 port_map = esw->port_map;
721 else
722 port_map = RT305X_ESW_PMAP_LLLLLL;
723
724 /* Unused HW feature, but still nice to be consistent here...
725 * This is also exported to userspace ('lan' attribute) so it's
726 * conveniently usable to decide which ports go into the wan vlan by
727 * default.
728 */
729 esw_rmw(esw, RT305X_ESW_REG_SGC2,
730 RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
731 port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
732
733 /* make the switch leds blink */
734 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
735 esw->ports[i].led = 0x05;
736
737 /* Apply the empty config. */
738 esw_apply_config(&esw->swdev);
739
740 /* Only unmask the port change interrupt */
741 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
742 }
743
744
745 int rt3050_esw_has_carrier(struct fe_priv *priv)
746 {
747 struct rt305x_esw *esw = priv->soc->swpriv;
748 u32 link;
749 int i;
750 bool cpuport;
751
752 link = esw_r32(esw, RT305X_ESW_REG_POA);
753 link >>= RT305X_ESW_POA_LINK_SHIFT;
754 cpuport = link & BIT(RT305X_ESW_PORT6);
755 link &= RT305X_ESW_POA_LINK_MASK;
756 for (i = 0; i <= RT305X_ESW_PORT5; i++) {
757 if (priv->link[i] != (link & BIT(i)))
758 dev_info(esw->dev, "port %d link %s\n", i, link & BIT(i) ? "up" : "down");
759 priv->link[i] = link & BIT(i);
760 }
761
762 return !!link && cpuport;
763 }
764
765 static irqreturn_t esw_interrupt(int irq, void *_esw)
766 {
767 struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
768 u32 status;
769
770 status = esw_r32(esw, RT305X_ESW_REG_ISR);
771 if (status & RT305X_ESW_PORT_ST_CHG) {
772 if (!esw->priv)
773 goto out;
774 if (rt3050_esw_has_carrier(esw->priv))
775 netif_carrier_on(esw->priv->netdev);
776 else
777 netif_carrier_off(esw->priv->netdev);
778 }
779
780 out:
781 esw_w32(esw, status, RT305X_ESW_REG_ISR);
782
783 return IRQ_HANDLED;
784 }
785
786 static int esw_apply_config(struct switch_dev *dev)
787 {
788 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
789 int i;
790 u8 disable = 0;
791 u8 doubletag = 0;
792 u8 en_vlan = 0;
793 u8 untag = 0;
794
795 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
796 u32 vid, vmsc;
797 if (esw->global_vlan_enable) {
798 vid = esw->vlans[i].vid;
799 vmsc = esw->vlans[i].ports;
800 } else {
801 vid = RT305X_ESW_VLAN_NONE;
802 vmsc = RT305X_ESW_PORTS_NONE;
803 }
804 esw_set_vlan_id(esw, i, vid);
805 esw_set_vmsc(esw, i, vmsc);
806 }
807
808 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
809 u32 pvid;
810 disable |= esw->ports[i].disable << i;
811 if (esw->global_vlan_enable) {
812 doubletag |= esw->ports[i].doubletag << i;
813 en_vlan |= 1 << i;
814 untag |= esw->ports[i].untag << i;
815 pvid = esw->ports[i].pvid;
816 } else {
817 int x = esw->alt_vlan_disable ? 0 : 1;
818 doubletag |= x << i;
819 en_vlan |= x << i;
820 untag |= x << i;
821 pvid = 0;
822 }
823 esw_set_pvid(esw, i, pvid);
824 if (i < RT305X_ESW_NUM_LEDS)
825 esw_w32(esw, esw->ports[i].led,
826 RT305X_ESW_REG_P0LED + 4*i);
827 }
828
829 esw_set_gsc(esw);
830 esw_set_port_disable(esw, disable);
831 esw_rmw(esw, RT305X_ESW_REG_SGC2,
832 (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
833 RT305X_ESW_SGC2_DOUBLE_TAG_S),
834 doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
835 esw_rmw(esw, RT305X_ESW_REG_PFC1,
836 RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
837 en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
838 esw_rmw(esw, RT305X_ESW_REG_POC2,
839 RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
840 untag << RT305X_ESW_POC2_UNTAG_EN_S);
841
842 if (!esw->global_vlan_enable) {
843 /*
844 * Still need to put all ports into vlan 0 or they'll be
845 * isolated.
846 * NOTE: vlan 0 is special, no vlan tag is prepended
847 */
848 esw_set_vlan_id(esw, 0, 0);
849 esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
850 }
851
852 return 0;
853 }
854
855 static int esw_reset_switch(struct switch_dev *dev)
856 {
857 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
858
859 esw->global_vlan_enable = 0;
860 memset(esw->ports, 0, sizeof(esw->ports));
861 memset(esw->vlans, 0, sizeof(esw->vlans));
862 esw_hw_init(esw);
863
864 return 0;
865 }
866
867 static int esw_get_vlan_enable(struct switch_dev *dev,
868 const struct switch_attr *attr,
869 struct switch_val *val)
870 {
871 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
872
873 val->value.i = esw->global_vlan_enable;
874
875 return 0;
876 }
877
878 static int esw_set_vlan_enable(struct switch_dev *dev,
879 const struct switch_attr *attr,
880 struct switch_val *val)
881 {
882 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
883
884 esw->global_vlan_enable = val->value.i != 0;
885
886 return 0;
887 }
888
889 static int esw_get_alt_vlan_disable(struct switch_dev *dev,
890 const struct switch_attr *attr,
891 struct switch_val *val)
892 {
893 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
894
895 val->value.i = esw->alt_vlan_disable;
896
897 return 0;
898 }
899
900 static int esw_set_alt_vlan_disable(struct switch_dev *dev,
901 const struct switch_attr *attr,
902 struct switch_val *val)
903 {
904 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
905
906 esw->alt_vlan_disable = val->value.i != 0;
907
908 return 0;
909 }
910
911 static int
912 rt305x_esw_set_bc_status(struct switch_dev *dev,
913 const struct switch_attr *attr,
914 struct switch_val *val)
915 {
916 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
917
918 esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
919
920 return 0;
921 }
922
923 static int
924 rt305x_esw_get_bc_status(struct switch_dev *dev,
925 const struct switch_attr *attr,
926 struct switch_val *val)
927 {
928 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
929
930 val->value.i = esw->bc_storm_protect;
931
932 return 0;
933 }
934
935 static int
936 rt305x_esw_set_led_freq(struct switch_dev *dev,
937 const struct switch_attr *attr,
938 struct switch_val *val)
939 {
940 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
941
942 esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
943
944 return 0;
945 }
946
947 static int
948 rt305x_esw_get_led_freq(struct switch_dev *dev,
949 const struct switch_attr *attr,
950 struct switch_val *val)
951 {
952 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
953
954 val->value.i = esw->led_frequency;
955
956 return 0;
957 }
958
959 static int esw_get_port_link(struct switch_dev *dev,
960 int port,
961 struct switch_port_link *link)
962 {
963 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
964 u32 speed, poa;
965
966 if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
967 return -EINVAL;
968
969 poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
970
971 link->link = (poa >> RT305X_ESW_LINK_S) & 1;
972 link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
973 if (port < RT305X_ESW_NUM_LEDS) {
974 speed = (poa >> RT305X_ESW_SPD_S) & 1;
975 } else {
976 if (port == RT305X_ESW_NUM_PORTS - 1)
977 poa >>= 1;
978 speed = (poa >> RT305X_ESW_SPD_S) & 3;
979 }
980 switch (speed) {
981 case 0:
982 link->speed = SWITCH_PORT_SPEED_10;
983 break;
984 case 1:
985 link->speed = SWITCH_PORT_SPEED_100;
986 break;
987 case 2:
988 case 3: /* forced gige speed can be 2 or 3 */
989 link->speed = SWITCH_PORT_SPEED_1000;
990 break;
991 default:
992 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
993 break;
994 }
995
996 return 0;
997 }
998
999 static int esw_get_port_bool(struct switch_dev *dev,
1000 const struct switch_attr *attr,
1001 struct switch_val *val)
1002 {
1003 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1004 int idx = val->port_vlan;
1005 u32 x, reg, shift;
1006
1007 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1008 return -EINVAL;
1009
1010 switch (attr->id) {
1011 case RT305X_ESW_ATTR_PORT_DISABLE:
1012 reg = RT305X_ESW_REG_POC0;
1013 shift = RT305X_ESW_POC0_DIS_PORT_S;
1014 break;
1015 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1016 reg = RT305X_ESW_REG_SGC2;
1017 shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1018 break;
1019 case RT305X_ESW_ATTR_PORT_UNTAG:
1020 reg = RT305X_ESW_REG_POC2;
1021 shift = RT305X_ESW_POC2_UNTAG_EN_S;
1022 break;
1023 case RT305X_ESW_ATTR_PORT_LAN:
1024 reg = RT305X_ESW_REG_SGC2;
1025 shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1026 if (idx >= RT305X_ESW_NUM_LANWAN)
1027 return -EINVAL;
1028 break;
1029 default:
1030 return -EINVAL;
1031 }
1032
1033 x = esw_r32(esw, reg);
1034 val->value.i = (x >> (idx + shift)) & 1;
1035
1036 return 0;
1037 }
1038
1039 static int esw_set_port_bool(struct switch_dev *dev,
1040 const struct switch_attr *attr,
1041 struct switch_val *val)
1042 {
1043 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1044 int idx = val->port_vlan;
1045
1046 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1047 val->value.i < 0 || val->value.i > 1)
1048 return -EINVAL;
1049
1050 switch (attr->id) {
1051 case RT305X_ESW_ATTR_PORT_DISABLE:
1052 esw->ports[idx].disable = val->value.i;
1053 break;
1054 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1055 esw->ports[idx].doubletag = val->value.i;
1056 break;
1057 case RT305X_ESW_ATTR_PORT_UNTAG:
1058 esw->ports[idx].untag = val->value.i;
1059 break;
1060 default:
1061 return -EINVAL;
1062 }
1063
1064 return 0;
1065 }
1066
1067 static int esw_get_port_recv_badgood(struct switch_dev *dev,
1068 const struct switch_attr *attr,
1069 struct switch_val *val)
1070 {
1071 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1072 int idx = val->port_vlan;
1073 int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1074 u32 reg;
1075
1076 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1077 return -EINVAL;
1078 reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1079 val->value.i = (reg >> shift) & 0xffff;
1080
1081 return 0;
1082 }
1083
1084 static int
1085 esw_get_port_tr_badgood(struct switch_dev *dev,
1086 const struct switch_attr *attr,
1087 struct switch_val *val)
1088 {
1089 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1090
1091 int idx = val->port_vlan;
1092 int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1093 u32 reg;
1094
1095 if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN) && (ralink_soc != MT762X_SOC_MT7688))
1096 return -EINVAL;
1097
1098 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1099 return -EINVAL;
1100
1101 reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1102 val->value.i = (reg >> shift) & 0xffff;
1103
1104 return 0;
1105 }
1106
1107 static int esw_get_port_led(struct switch_dev *dev,
1108 const struct switch_attr *attr,
1109 struct switch_val *val)
1110 {
1111 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1112 int idx = val->port_vlan;
1113
1114 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1115 idx >= RT305X_ESW_NUM_LEDS)
1116 return -EINVAL;
1117
1118 val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1119
1120 return 0;
1121 }
1122
1123 static int esw_set_port_led(struct switch_dev *dev,
1124 const struct switch_attr *attr,
1125 struct switch_val *val)
1126 {
1127 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1128 int idx = val->port_vlan;
1129
1130 if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1131 return -EINVAL;
1132
1133 esw->ports[idx].led = val->value.i;
1134
1135 return 0;
1136 }
1137
1138 static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1139 {
1140 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1141
1142 if (port >= RT305X_ESW_NUM_PORTS)
1143 return -EINVAL;
1144
1145 *val = esw_get_pvid(esw, port);
1146
1147 return 0;
1148 }
1149
1150 static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1151 {
1152 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1153
1154 if (port >= RT305X_ESW_NUM_PORTS)
1155 return -EINVAL;
1156
1157 esw->ports[port].pvid = val;
1158
1159 return 0;
1160 }
1161
1162 static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1163 {
1164 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1165 u32 vmsc, poc2;
1166 int vlan_idx = -1;
1167 int i;
1168
1169 val->len = 0;
1170
1171 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1172 return -EINVAL;
1173
1174 /* valid vlan? */
1175 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1176 if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1177 esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1178 vlan_idx = i;
1179 break;
1180 }
1181 }
1182
1183 if (vlan_idx == -1)
1184 return -EINVAL;
1185
1186 vmsc = esw_get_vmsc(esw, vlan_idx);
1187 poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1188
1189 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1190 struct switch_port *p;
1191 int port_mask = 1 << i;
1192
1193 if (!(vmsc & port_mask))
1194 continue;
1195
1196 p = &val->value.ports[val->len++];
1197 p->id = i;
1198 if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1199 p->flags = 0;
1200 else
1201 p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1202 }
1203
1204 return 0;
1205 }
1206
1207 static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1208 {
1209 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1210 int ports;
1211 int vlan_idx = -1;
1212 int i;
1213
1214 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1215 val->len > RT305X_ESW_NUM_PORTS)
1216 return -EINVAL;
1217
1218 /* one of the already defined vlans? */
1219 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1220 if (esw->vlans[i].vid == val->port_vlan &&
1221 esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1222 vlan_idx = i;
1223 break;
1224 }
1225 }
1226
1227 /* select a free slot */
1228 for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1229 if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1230 vlan_idx = i;
1231 }
1232
1233 /* bail if all slots are in use */
1234 if (vlan_idx == -1)
1235 return -EINVAL;
1236
1237 ports = RT305X_ESW_PORTS_NONE;
1238 for (i = 0; i < val->len; i++) {
1239 struct switch_port *p = &val->value.ports[i];
1240 int port_mask = 1 << p->id;
1241 bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1242
1243 if (p->id >= RT305X_ESW_NUM_PORTS)
1244 return -EINVAL;
1245
1246 ports |= port_mask;
1247 esw->ports[p->id].untag = untagged;
1248 }
1249 esw->vlans[vlan_idx].ports = ports;
1250 if (ports == RT305X_ESW_PORTS_NONE)
1251 esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1252 else
1253 esw->vlans[vlan_idx].vid = val->port_vlan;
1254
1255 return 0;
1256 }
1257
1258 static const struct switch_attr esw_global[] = {
1259 {
1260 .type = SWITCH_TYPE_INT,
1261 .name = "enable_vlan",
1262 .description = "VLAN mode (1:enabled)",
1263 .max = 1,
1264 .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1265 .get = esw_get_vlan_enable,
1266 .set = esw_set_vlan_enable,
1267 },
1268 {
1269 .type = SWITCH_TYPE_INT,
1270 .name = "alternate_vlan_disable",
1271 .description = "Use en_vlan instead of doubletag to disable"
1272 " VLAN mode",
1273 .max = 1,
1274 .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1275 .get = esw_get_alt_vlan_disable,
1276 .set = esw_set_alt_vlan_disable,
1277 },
1278 {
1279 .type = SWITCH_TYPE_INT,
1280 .name = "bc_storm_protect",
1281 .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1282 .max = 3,
1283 .id = RT305X_ESW_ATTR_BC_STATUS,
1284 .get = rt305x_esw_get_bc_status,
1285 .set = rt305x_esw_set_bc_status,
1286 },
1287 {
1288 .type = SWITCH_TYPE_INT,
1289 .name = "led_frequency",
1290 .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1291 .max = 3,
1292 .id = RT305X_ESW_ATTR_LED_FREQ,
1293 .get = rt305x_esw_get_led_freq,
1294 .set = rt305x_esw_set_led_freq,
1295 }
1296 };
1297
1298 static const struct switch_attr esw_port[] = {
1299 {
1300 .type = SWITCH_TYPE_INT,
1301 .name = "disable",
1302 .description = "Port state (1:disabled)",
1303 .max = 1,
1304 .id = RT305X_ESW_ATTR_PORT_DISABLE,
1305 .get = esw_get_port_bool,
1306 .set = esw_set_port_bool,
1307 },
1308 {
1309 .type = SWITCH_TYPE_INT,
1310 .name = "doubletag",
1311 .description = "Double tagging for incoming vlan packets "
1312 "(1:enabled)",
1313 .max = 1,
1314 .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1315 .get = esw_get_port_bool,
1316 .set = esw_set_port_bool,
1317 },
1318 {
1319 .type = SWITCH_TYPE_INT,
1320 .name = "untag",
1321 .description = "Untag (1:strip outgoing vlan tag)",
1322 .max = 1,
1323 .id = RT305X_ESW_ATTR_PORT_UNTAG,
1324 .get = esw_get_port_bool,
1325 .set = esw_set_port_bool,
1326 },
1327 {
1328 .type = SWITCH_TYPE_INT,
1329 .name = "led",
1330 .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1331 " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1332 " 8:100mact, 10:blink, 11:off, 12:on)",
1333 .max = 15,
1334 .id = RT305X_ESW_ATTR_PORT_LED,
1335 .get = esw_get_port_led,
1336 .set = esw_set_port_led,
1337 },
1338 {
1339 .type = SWITCH_TYPE_INT,
1340 .name = "lan",
1341 .description = "HW port group (0:wan, 1:lan)",
1342 .max = 1,
1343 .id = RT305X_ESW_ATTR_PORT_LAN,
1344 .get = esw_get_port_bool,
1345 },
1346 {
1347 .type = SWITCH_TYPE_INT,
1348 .name = "recv_bad",
1349 .description = "Receive bad packet counter",
1350 .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1351 .get = esw_get_port_recv_badgood,
1352 },
1353 {
1354 .type = SWITCH_TYPE_INT,
1355 .name = "recv_good",
1356 .description = "Receive good packet counter",
1357 .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1358 .get = esw_get_port_recv_badgood,
1359 },
1360 {
1361 .type = SWITCH_TYPE_INT,
1362 .name = "tr_bad",
1363
1364 .description = "Transmit bad packet counter. rt5350 only",
1365 .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1366 .get = esw_get_port_tr_badgood,
1367 },
1368 {
1369 .type = SWITCH_TYPE_INT,
1370 .name = "tr_good",
1371
1372 .description = "Transmit good packet counter. rt5350 only",
1373 .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1374 .get = esw_get_port_tr_badgood,
1375 },
1376 };
1377
1378 static const struct switch_attr esw_vlan[] = {
1379 };
1380
1381 static const struct switch_dev_ops esw_ops = {
1382 .attr_global = {
1383 .attr = esw_global,
1384 .n_attr = ARRAY_SIZE(esw_global),
1385 },
1386 .attr_port = {
1387 .attr = esw_port,
1388 .n_attr = ARRAY_SIZE(esw_port),
1389 },
1390 .attr_vlan = {
1391 .attr = esw_vlan,
1392 .n_attr = ARRAY_SIZE(esw_vlan),
1393 },
1394 .get_vlan_ports = esw_get_vlan_ports,
1395 .set_vlan_ports = esw_set_vlan_ports,
1396 .get_port_pvid = esw_get_port_pvid,
1397 .set_port_pvid = esw_set_port_pvid,
1398 .get_port_link = esw_get_port_link,
1399 .apply_config = esw_apply_config,
1400 .reset_switch = esw_reset_switch,
1401 };
1402
1403 static int esw_probe(struct platform_device *pdev)
1404 {
1405 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1406 struct device_node *np = pdev->dev.of_node;
1407 const __be32 *port_map, *port_disable, *reg_init;
1408 struct rt305x_esw *esw;
1409
1410 esw = devm_kzalloc(&pdev->dev, sizeof(*esw), GFP_KERNEL);
1411 if (!esw)
1412 return -ENOMEM;
1413
1414 esw->dev = &pdev->dev;
1415 esw->irq = irq_of_parse_and_map(np, 0);
1416 esw->base = devm_ioremap_resource(&pdev->dev, res);
1417 if (IS_ERR(esw->base))
1418 return PTR_ERR(esw->base);
1419
1420 port_map = of_get_property(np, "mediatek,portmap", NULL);
1421 if (port_map)
1422 esw->port_map = be32_to_cpu(*port_map);
1423
1424 port_disable = of_get_property(np, "mediatek,portdisable", NULL);
1425 if (port_disable)
1426 esw->port_disable = be32_to_cpu(*port_disable);
1427
1428 reg_init = of_get_property(np, "ralink,fct2", NULL);
1429 if (reg_init)
1430 esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1431
1432 reg_init = of_get_property(np, "ralink,fpa2", NULL);
1433 if (reg_init)
1434 esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1435
1436 reg_init = of_get_property(np, "mediatek,led_polarity", NULL);
1437 if (reg_init)
1438 esw->reg_led_polarity = be32_to_cpu(*reg_init);
1439
1440 reg_init = of_get_property(np, "mediatek,led_source", NULL);
1441 if (reg_init)
1442 esw->reg_led_source = be32_to_cpu(*reg_init);
1443
1444 esw->rst_esw = devm_reset_control_get(&pdev->dev, "esw");
1445 if (IS_ERR(esw->rst_esw))
1446 esw->rst_esw = NULL;
1447 esw->rst_ephy = devm_reset_control_get(&pdev->dev, "ephy");
1448 if (IS_ERR(esw->rst_ephy))
1449 esw->rst_ephy = NULL;
1450
1451 spin_lock_init(&esw->reg_rw_lock);
1452 platform_set_drvdata(pdev, esw);
1453
1454 return 0;
1455 }
1456
1457 static int esw_remove(struct platform_device *pdev)
1458 {
1459 struct rt305x_esw *esw = platform_get_drvdata(pdev);
1460
1461 if (esw) {
1462 esw_w32(esw, ~0, RT305X_ESW_REG_IMR);
1463 platform_set_drvdata(pdev, NULL);
1464 }
1465
1466 return 0;
1467 }
1468
1469 static const struct of_device_id ralink_esw_match[] = {
1470 { .compatible = "ralink,rt3050-esw" },
1471 {},
1472 };
1473 MODULE_DEVICE_TABLE(of, ralink_esw_match);
1474
1475 /* called by the ethernet driver to bound with the switch driver */
1476 int rt3050_esw_init(struct fe_priv *priv)
1477 {
1478 struct device_node *np = priv->switch_np;
1479 struct platform_device *pdev = of_find_device_by_node(np);
1480 struct switch_dev *swdev;
1481 struct rt305x_esw *esw;
1482 const __be32 *rgmii;
1483 int ret;
1484
1485 if (!pdev)
1486 return -ENODEV;
1487
1488 if (!of_device_is_compatible(np, ralink_esw_match->compatible))
1489 return -EINVAL;
1490
1491 esw = platform_get_drvdata(pdev);
1492 if (!esw)
1493 return -EPROBE_DEFER;
1494
1495 priv->soc->swpriv = esw;
1496 esw->priv = priv;
1497
1498 esw_hw_init(esw);
1499
1500 rgmii = of_get_property(np, "ralink,rgmii", NULL);
1501 if (rgmii && be32_to_cpu(*rgmii) == 1) {
1502 /*
1503 * External switch connected to RGMII interface.
1504 * Unregister the switch device after initialization.
1505 */
1506 dev_err(&pdev->dev, "RGMII mode, not exporting switch device.\n");
1507 unregister_switch(&esw->swdev);
1508 platform_set_drvdata(pdev, NULL);
1509 return -ENODEV;
1510 }
1511
1512 swdev = &esw->swdev;
1513 swdev->of_node = pdev->dev.of_node;
1514 swdev->name = "rt305x-esw";
1515 swdev->alias = "rt305x";
1516 swdev->cpu_port = RT305X_ESW_PORT6;
1517 swdev->ports = RT305X_ESW_NUM_PORTS;
1518 swdev->vlans = RT305X_ESW_NUM_VIDS;
1519 swdev->ops = &esw_ops;
1520
1521 ret = register_switch(swdev, NULL);
1522 if (ret < 0) {
1523 dev_err(&pdev->dev, "register_switch failed\n");
1524 return ret;
1525 }
1526
1527 ret = devm_request_irq(&pdev->dev, esw->irq, esw_interrupt, 0, "esw",
1528 esw);
1529 if (!ret) {
1530 esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1531 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1532 }
1533
1534 dev_info(&pdev->dev, "mediatek esw at 0x%08lx, irq %d initialized\n",
1535 (long unsigned int)esw->base, esw->irq);
1536
1537 return 0;
1538 }
1539
1540 static struct platform_driver esw_driver = {
1541 .probe = esw_probe,
1542 .remove = esw_remove,
1543 .driver = {
1544 .name = "rt3050-esw",
1545 .owner = THIS_MODULE,
1546 .of_match_table = ralink_esw_match,
1547 },
1548 };
1549
1550 module_platform_driver(esw_driver);
1551
1552 MODULE_LICENSE("GPL");
1553 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1554 MODULE_DESCRIPTION("Switch driver for RT305X SoC");
1555 MODULE_VERSION(MTK_FE_DRV_VERSION);
Staging tree of Stijn Tintel