projects / openwrt / staging / stintel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
raimps: mtk_eth_soc: drop rst_esw from ESW driver
[openwrt/staging/stintel.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / esw_rt3050.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 * Copyright (C) 2016 Vittorio Gambaletta <openwrt@vittgam.net>
14 */
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/platform_device.h>
19 #include <asm/mach-ralink/ralink_regs.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22
23 #include <linux/switch.h>
24 #include <linux/reset.h>
25
26 #include "mtk_eth_soc.h"
27 #include "esw_rt3050.h"
28
29 /* HW limitations for this switch:
30 * - No large frame support (PKT_MAX_LEN at most 1536)
31 * - Can't have untagged vlan and tagged vlan on one port at the same time,
32 * though this might be possible using the undocumented PPE.
33 */
34
35 #define RT305X_ESW_REG_ISR 0x00
36 #define RT305X_ESW_REG_IMR 0x04
37 #define RT305X_ESW_REG_FCT0 0x08
38 #define RT305X_ESW_REG_PFC1 0x14
39 #define RT305X_ESW_REG_ATS 0x24
40 #define RT305X_ESW_REG_ATS0 0x28
41 #define RT305X_ESW_REG_ATS1 0x2c
42 #define RT305X_ESW_REG_ATS2 0x30
43 #define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
44 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
45 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
46 #define RT305X_ESW_REG_POA 0x80
47 #define RT305X_ESW_REG_FPA 0x84
48 #define RT305X_ESW_REG_SOCPC 0x8c
49 #define RT305X_ESW_REG_POC0 0x90
50 #define RT305X_ESW_REG_POC1 0x94
51 #define RT305X_ESW_REG_POC2 0x98
52 #define RT305X_ESW_REG_SGC 0x9c
53 #define RT305X_ESW_REG_STRT 0xa0
54 #define RT305X_ESW_REG_PCR0 0xc0
55 #define RT305X_ESW_REG_PCR1 0xc4
56 #define RT305X_ESW_REG_FPA2 0xc8
57 #define RT305X_ESW_REG_FCT2 0xcc
58 #define RT305X_ESW_REG_SGC2 0xe4
59 #define RT305X_ESW_REG_P0LED 0xa4
60 #define RT305X_ESW_REG_P1LED 0xa8
61 #define RT305X_ESW_REG_P2LED 0xac
62 #define RT305X_ESW_REG_P3LED 0xb0
63 #define RT305X_ESW_REG_P4LED 0xb4
64 #define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
65 #define RT305X_ESW_REG_P1PC 0xec
66 #define RT305X_ESW_REG_P2PC 0xf0
67 #define RT305X_ESW_REG_P3PC 0xf4
68 #define RT305X_ESW_REG_P4PC 0xf8
69 #define RT305X_ESW_REG_P5PC 0xfc
70
71 #define RT305X_ESW_LED_LINK 0
72 #define RT305X_ESW_LED_100M 1
73 #define RT305X_ESW_LED_DUPLEX 2
74 #define RT305X_ESW_LED_ACTIVITY 3
75 #define RT305X_ESW_LED_COLLISION 4
76 #define RT305X_ESW_LED_LINKACT 5
77 #define RT305X_ESW_LED_DUPLCOLL 6
78 #define RT305X_ESW_LED_10MACT 7
79 #define RT305X_ESW_LED_100MACT 8
80 /* Additional led states not in datasheet: */
81 #define RT305X_ESW_LED_BLINK 10
82 #define RT305X_ESW_LED_OFF 11
83 #define RT305X_ESW_LED_ON 12
84
85 #define RT305X_ESW_LINK_S 25
86 #define RT305X_ESW_DUPLEX_S 9
87 #define RT305X_ESW_SPD_S 0
88
89 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
90 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
91 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
92
93 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
94
95 #define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
96 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
97
98 #define RT305X_ESW_PVIDC_PVID_M 0xfff
99 #define RT305X_ESW_PVIDC_PVID_S 12
100
101 #define RT305X_ESW_VLANI_VID_M 0xfff
102 #define RT305X_ESW_VLANI_VID_S 12
103
104 #define RT305X_ESW_VMSC_MSC_M 0xff
105 #define RT305X_ESW_VMSC_MSC_S 8
106
107 #define RT305X_ESW_SOCPC_DISUN2CPU_S 0
108 #define RT305X_ESW_SOCPC_DISMC2CPU_S 8
109 #define RT305X_ESW_SOCPC_DISBC2CPU_S 16
110 #define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
111
112 #define RT305X_ESW_POC0_EN_BP_S 0
113 #define RT305X_ESW_POC0_EN_FC_S 8
114 #define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
115 #define RT305X_ESW_POC0_DIS_PORT_M 0x7f
116 #define RT305X_ESW_POC0_DIS_PORT_S 23
117
118 #define RT305X_ESW_POC2_UNTAG_EN_M 0xff
119 #define RT305X_ESW_POC2_UNTAG_EN_S 0
120 #define RT305X_ESW_POC2_ENAGING_S 8
121 #define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
122
123 #define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
124 #define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
125 #define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
126 #define RT305X_ESW_SGC2_LAN_PMAP_S 24
127
128 #define RT305X_ESW_PFC1_EN_VLAN_M 0xff
129 #define RT305X_ESW_PFC1_EN_VLAN_S 16
130 #define RT305X_ESW_PFC1_EN_TOS_S 24
131
132 #define RT305X_ESW_VLAN_NONE 0xfff
133
134 #define RT305X_ESW_GSC_BC_STROM_MASK 0x3
135 #define RT305X_ESW_GSC_BC_STROM_SHIFT 4
136
137 #define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
138 #define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
139
140 #define RT305X_ESW_POA_LINK_MASK 0x1f
141 #define RT305X_ESW_POA_LINK_SHIFT 25
142
143 #define RT305X_ESW_PORT_ST_CHG BIT(26)
144 #define RT305X_ESW_PORT0 0
145 #define RT305X_ESW_PORT1 1
146 #define RT305X_ESW_PORT2 2
147 #define RT305X_ESW_PORT3 3
148 #define RT305X_ESW_PORT4 4
149 #define RT305X_ESW_PORT5 5
150 #define RT305X_ESW_PORT6 6
151
152 #define RT305X_ESW_PORTS_NONE 0
153
154 #define RT305X_ESW_PMAP_LLLLLL 0x3f
155 #define RT305X_ESW_PMAP_LLLLWL 0x2f
156 #define RT305X_ESW_PMAP_WLLLLL 0x3e
157
158 #define RT305X_ESW_PORTS_INTERNAL \
159 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
160 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
161 BIT(RT305X_ESW_PORT4))
162
163 #define RT305X_ESW_PORTS_NOCPU \
164 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
165
166 #define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
167
168 #define RT305X_ESW_PORTS_ALL \
169 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
170
171 #define RT305X_ESW_NUM_VLANS 16
172 #define RT305X_ESW_NUM_VIDS 4096
173 #define RT305X_ESW_NUM_PORTS 7
174 #define RT305X_ESW_NUM_LANWAN 6
175 #define RT305X_ESW_NUM_LEDS 5
176
177 #define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
178 #define RT5350_EWS_REG_LED_CONTROL 0x168
179
180 enum {
181 /* Global attributes. */
182 RT305X_ESW_ATTR_ENABLE_VLAN,
183 RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
184 RT305X_ESW_ATTR_BC_STATUS,
185 RT305X_ESW_ATTR_LED_FREQ,
186 /* Port attributes. */
187 RT305X_ESW_ATTR_PORT_DISABLE,
188 RT305X_ESW_ATTR_PORT_DOUBLETAG,
189 RT305X_ESW_ATTR_PORT_UNTAG,
190 RT305X_ESW_ATTR_PORT_LED,
191 RT305X_ESW_ATTR_PORT_LAN,
192 RT305X_ESW_ATTR_PORT_RECV_BAD,
193 RT305X_ESW_ATTR_PORT_RECV_GOOD,
194 RT5350_ESW_ATTR_PORT_TR_BAD,
195 RT5350_ESW_ATTR_PORT_TR_GOOD,
196 };
197
198 struct esw_port {
199 bool disable;
200 bool doubletag;
201 bool untag;
202 u8 led;
203 u16 pvid;
204 };
205
206 struct esw_vlan {
207 u8 ports;
208 u16 vid;
209 };
210
211 enum {
212 RT305X_ESW_VLAN_CONFIG_NONE = 0,
213 RT305X_ESW_VLAN_CONFIG_LLLLW,
214 RT305X_ESW_VLAN_CONFIG_WLLLL,
215 };
216
217 struct rt305x_esw {
218 struct device *dev;
219 void __iomem *base;
220 int irq;
221 struct fe_priv *priv;
222
223 /* Protects against concurrent register r/w operations. */
224 spinlock_t reg_rw_lock;
225
226 unsigned char port_map;
227 unsigned char port_disable;
228 unsigned int reg_initval_fct2;
229 unsigned int reg_initval_fpa2;
230 unsigned int reg_led_polarity;
231 unsigned int reg_led_source;
232
233 struct switch_dev swdev;
234 bool global_vlan_enable;
235 bool alt_vlan_disable;
236 int bc_storm_protect;
237 int led_frequency;
238 struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
239 struct esw_port ports[RT305X_ESW_NUM_PORTS];
240 struct reset_control *rst_ephy;
241
242 };
243
244 static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
245 {
246 __raw_writel(val, esw->base + reg);
247 }
248
249 static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
250 {
251 return __raw_readl(esw->base + reg);
252 }
253
254 static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg,
255 unsigned long mask, unsigned long val)
256 {
257 unsigned long t;
258
259 t = __raw_readl(esw->base + reg) & ~mask;
260 __raw_writel(t | val, esw->base + reg);
261 }
262
263 static void esw_reset_ephy(struct rt305x_esw *esw)
264 {
265 if (!esw->rst_ephy)
266 return;
267
268 reset_control_assert(esw->rst_ephy);
269 usleep_range(60, 120);
270 reset_control_deassert(esw->rst_ephy);
271 usleep_range(60, 120);
272 }
273
274 static void esw_rmw(struct rt305x_esw *esw, unsigned reg,
275 unsigned long mask, unsigned long val)
276 {
277 unsigned long flags;
278
279 spin_lock_irqsave(&esw->reg_rw_lock, flags);
280 esw_rmw_raw(esw, reg, mask, val);
281 spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
282 }
283
284 static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,
285 u32 phy_register, u32 write_data)
286 {
287 unsigned long t_start = jiffies;
288 int ret = 0;
289
290 while (1) {
291 if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
292 RT305X_ESW_PCR1_WT_DONE))
293 break;
294 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
295 ret = 1;
296 goto out;
297 }
298 }
299
300 write_data &= 0xffff;
301 esw_w32(esw, (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
302 (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
303 (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
304 RT305X_ESW_REG_PCR0);
305
306 t_start = jiffies;
307 while (1) {
308 if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
309 RT305X_ESW_PCR1_WT_DONE)
310 break;
311
312 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
313 ret = 1;
314 break;
315 }
316 }
317 out:
318 if (ret)
319 dev_err(esw->dev, "ramips_eth: MDIO timeout\n");
320 return ret;
321 }
322
323 static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
324 {
325 unsigned s;
326 unsigned val;
327
328 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
329 val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
330 val = (val >> s) & RT305X_ESW_VLANI_VID_M;
331
332 return val;
333 }
334
335 static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
336 {
337 unsigned s;
338
339 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
340 esw_rmw(esw,
341 RT305X_ESW_REG_VLANI(vlan / 2),
342 RT305X_ESW_VLANI_VID_M << s,
343 (vid & RT305X_ESW_VLANI_VID_M) << s);
344 }
345
346 static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
347 {
348 unsigned s, val;
349
350 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
351 val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
352 return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
353 }
354
355 static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
356 {
357 unsigned s;
358
359 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
360 esw_rmw(esw,
361 RT305X_ESW_REG_PVIDC(port / 2),
362 RT305X_ESW_PVIDC_PVID_M << s,
363 (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
364 }
365
366 static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
367 {
368 unsigned s, val;
369
370 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
371 val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
372 val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
373
374 return val;
375 }
376
377 static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
378 {
379 unsigned s;
380
381 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
382 esw_rmw(esw,
383 RT305X_ESW_REG_VMSC(vlan / 4),
384 RT305X_ESW_VMSC_MSC_M << s,
385 (msc & RT305X_ESW_VMSC_MSC_M) << s);
386 }
387
388 static unsigned esw_get_port_disable(struct rt305x_esw *esw)
389 {
390 unsigned reg;
391
392 reg = esw_r32(esw, RT305X_ESW_REG_POC0);
393 return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
394 RT305X_ESW_POC0_DIS_PORT_M;
395 }
396
397 static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
398 {
399 unsigned old_mask;
400 unsigned enable_mask;
401 unsigned changed;
402 int i;
403
404 old_mask = esw_get_port_disable(esw);
405 changed = old_mask ^ disable_mask;
406 enable_mask = old_mask & disable_mask;
407
408 /* enable before writing to MII */
409 esw_rmw(esw, RT305X_ESW_REG_POC0,
410 (RT305X_ESW_POC0_DIS_PORT_M <<
411 RT305X_ESW_POC0_DIS_PORT_S),
412 enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
413
414 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
415 if (!(changed & (1 << i)))
416 continue;
417 if (disable_mask & (1 << i)) {
418 /* disable */
419 rt305x_mii_write(esw, i, MII_BMCR,
420 BMCR_PDOWN);
421 } else {
422 /* enable */
423 rt305x_mii_write(esw, i, MII_BMCR,
424 BMCR_FULLDPLX |
425 BMCR_ANENABLE |
426 BMCR_ANRESTART |
427 BMCR_SPEED100);
428 }
429 }
430
431 /* disable after writing to MII */
432 esw_rmw(esw, RT305X_ESW_REG_POC0,
433 (RT305X_ESW_POC0_DIS_PORT_M <<
434 RT305X_ESW_POC0_DIS_PORT_S),
435 disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
436 }
437
438 static void esw_set_gsc(struct rt305x_esw *esw)
439 {
440 esw_rmw(esw, RT305X_ESW_REG_SGC,
441 RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
442 esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
443 esw_rmw(esw, RT305X_ESW_REG_SGC,
444 RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
445 esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
446 }
447
448 static int esw_apply_config(struct switch_dev *dev);
449
450 static void esw_hw_init(struct rt305x_esw *esw)
451 {
452 int i;
453 u8 port_disable = 0;
454 u8 port_map = RT305X_ESW_PMAP_LLLLLL;
455
456 /* vodoo from original driver */
457 esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
458 esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
459 /* Port priority 1 for all ports, vlan enabled. */
460 esw_w32(esw, 0x00005555 |
461 (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
462 RT305X_ESW_REG_PFC1);
463
464 /* Enable all ports, Back Pressure and Flow Control */
465 esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
466 (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
467 RT305X_ESW_REG_POC0);
468
469 /* Enable Aging, and VLAN TAG removal */
470 esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
471 (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
472 RT305X_ESW_REG_POC2);
473
474 if (esw->reg_initval_fct2)
475 esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
476 else
477 esw_w32(esw, 0x0002500c, RT305X_ESW_REG_FCT2);
478
479 /* 300s aging timer, max packet len 1536, broadcast storm prevention
480 * disabled, disable collision abort, mac xor48 hash, 10 packet back
481 * pressure jam, GMII disable was_transmit, back pressure disabled,
482 * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
483 * ports.
484 */
485 esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
486
487 /* Setup SoC Port control register */
488 esw_w32(esw,
489 (RT305X_ESW_SOCPC_CRC_PADDING |
490 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
491 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
492 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
493 RT305X_ESW_REG_SOCPC);
494
495 /* ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
496 * turbo mii off, rgmi 3.3v off
497 * port5: disabled
498 * port6: enabled, gige, full-duplex, rx/tx-flow-control
499 */
500 if (esw->reg_initval_fpa2)
501 esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
502 else
503 esw_w32(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
504 esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
505
506 /* Force Link/Activity on ports */
507 esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P0LED);
508 esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P1LED);
509 esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P2LED);
510 esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P3LED);
511 esw_w32(esw, RT305X_ESW_LED_LINKACT, RT305X_ESW_REG_P4LED);
512
513 /* Copy disabled port configuration from device tree setup */
514 port_disable = esw->port_disable;
515
516 /* Disable nonexistent ports by reading the switch config
517 * after having enabled all possible ports above
518 */
519 port_disable |= esw_get_port_disable(esw);
520
521 for (i = 0; i < 6; i++)
522 esw->ports[i].disable = (port_disable & (1 << i)) != 0;
523
524 if (ralink_soc == RT305X_SOC_RT3352) {
525 esw_reset_ephy(esw);
526
527 rt305x_mii_write(esw, 0, 31, 0x8000);
528 for (i = 0; i < 5; i++) {
529 if (esw->ports[i].disable) {
530 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
531 } else {
532 rt305x_mii_write(esw, i, MII_BMCR,
533 BMCR_FULLDPLX |
534 BMCR_ANENABLE |
535 BMCR_SPEED100);
536 }
537 /* TX10 waveform coefficient LSB=0 disable PHY */
538 rt305x_mii_write(esw, i, 26, 0x1601);
539 /* TX100/TX10 AD/DA current bias */
540 rt305x_mii_write(esw, i, 29, 0x7016);
541 /* TX100 slew rate control */
542 rt305x_mii_write(esw, i, 30, 0x0038);
543 }
544
545 /* select global register */
546 rt305x_mii_write(esw, 0, 31, 0x0);
547 /* enlarge agcsel threshold 3 and threshold 2 */
548 rt305x_mii_write(esw, 0, 1, 0x4a40);
549 /* enlarge agcsel threshold 5 and threshold 4 */
550 rt305x_mii_write(esw, 0, 2, 0x6254);
551 /* enlarge agcsel threshold */
552 rt305x_mii_write(esw, 0, 3, 0xa17f);
553 rt305x_mii_write(esw, 0, 12, 0x7eaa);
554 /* longer TP_IDL tail length */
555 rt305x_mii_write(esw, 0, 14, 0x65);
556 /* increased squelch pulse count threshold. */
557 rt305x_mii_write(esw, 0, 16, 0x0684);
558 /* set TX10 signal amplitude threshold to minimum */
559 rt305x_mii_write(esw, 0, 17, 0x0fe0);
560 /* set squelch amplitude to higher threshold */
561 rt305x_mii_write(esw, 0, 18, 0x40ba);
562 /* tune TP_IDL tail and head waveform, enable power
563 * down slew rate control
564 */
565 rt305x_mii_write(esw, 0, 22, 0x253f);
566 /* set PLL/Receive bias current are calibrated */
567 rt305x_mii_write(esw, 0, 27, 0x2fda);
568 /* change PLL/Receive bias current to internal(RT3350) */
569 rt305x_mii_write(esw, 0, 28, 0xc410);
570 /* change PLL bias current to internal(RT3052_MP3) */
571 rt305x_mii_write(esw, 0, 29, 0x598b);
572 /* select local register */
573 rt305x_mii_write(esw, 0, 31, 0x8000);
574 } else if (ralink_soc == RT305X_SOC_RT5350) {
575 esw_reset_ephy(esw);
576
577 /* set the led polarity */
578 esw_w32(esw, esw->reg_led_polarity & 0x1F,
579 RT5350_EWS_REG_LED_CONTROL);
580
581 /* local registers */
582 rt305x_mii_write(esw, 0, 31, 0x8000);
583 for (i = 0; i < 5; i++) {
584 if (esw->ports[i].disable) {
585 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
586 } else {
587 rt305x_mii_write(esw, i, MII_BMCR,
588 BMCR_FULLDPLX |
589 BMCR_ANENABLE |
590 BMCR_SPEED100);
591 }
592 /* TX10 waveform coefficient LSB=0 disable PHY */
593 rt305x_mii_write(esw, i, 26, 0x1601);
594 /* TX100/TX10 AD/DA current bias */
595 rt305x_mii_write(esw, i, 29, 0x7015);
596 /* TX100 slew rate control */
597 rt305x_mii_write(esw, i, 30, 0x0038);
598 }
599
600 /* global registers */
601 rt305x_mii_write(esw, 0, 31, 0x0);
602 /* enlarge agcsel threshold 3 and threshold 2 */
603 rt305x_mii_write(esw, 0, 1, 0x4a40);
604 /* enlarge agcsel threshold 5 and threshold 4 */
605 rt305x_mii_write(esw, 0, 2, 0x6254);
606 /* enlarge agcsel threshold 6 */
607 rt305x_mii_write(esw, 0, 3, 0xa17f);
608 rt305x_mii_write(esw, 0, 12, 0x7eaa);
609 /* longer TP_IDL tail length */
610 rt305x_mii_write(esw, 0, 14, 0x65);
611 /* increased squelch pulse count threshold. */
612 rt305x_mii_write(esw, 0, 16, 0x0684);
613 /* set TX10 signal amplitude threshold to minimum */
614 rt305x_mii_write(esw, 0, 17, 0x0fe0);
615 /* set squelch amplitude to higher threshold */
616 rt305x_mii_write(esw, 0, 18, 0x40ba);
617 /* tune TP_IDL tail and head waveform, enable power
618 * down slew rate control
619 */
620 rt305x_mii_write(esw, 0, 22, 0x253f);
621 /* set PLL/Receive bias current are calibrated */
622 rt305x_mii_write(esw, 0, 27, 0x2fda);
623 /* change PLL/Receive bias current to internal(RT3350) */
624 rt305x_mii_write(esw, 0, 28, 0xc410);
625 /* change PLL bias current to internal(RT3052_MP3) */
626 rt305x_mii_write(esw, 0, 29, 0x598b);
627 /* select local register */
628 rt305x_mii_write(esw, 0, 31, 0x8000);
629 } else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
630 int i;
631
632 esw_reset_ephy(esw);
633
634 /* set the led polarity and led source */
635 esw_w32(esw, (esw->reg_led_polarity & 0x1F) |
636 ((esw->reg_led_source << 8) & 0x700),
637 RT5350_EWS_REG_LED_CONTROL);
638
639 rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */
640 rt305x_mii_write(esw, 0, 26, 0x0020);
641
642 for (i = 0; i < 5; i++) {
643 rt305x_mii_write(esw, i, 31, 0x8000);
644 rt305x_mii_write(esw, i, 0, 0x3100);
645 rt305x_mii_write(esw, i, 30, 0xa000);
646 rt305x_mii_write(esw, i, 31, 0xa000);
647 rt305x_mii_write(esw, i, 16, 0x0606);
648 rt305x_mii_write(esw, i, 23, 0x0f0e);
649 rt305x_mii_write(esw, i, 24, 0x1610);
650 rt305x_mii_write(esw, i, 30, 0x1f15);
651 rt305x_mii_write(esw, i, 28, 0x6111);
652 rt305x_mii_write(esw, i, 31, 0x2000);
653 rt305x_mii_write(esw, i, 26, 0x0000);
654 }
655
656 /* 100Base AOI setting */
657 rt305x_mii_write(esw, 0, 31, 0x5000);
658 rt305x_mii_write(esw, 0, 19, 0x004a);
659 rt305x_mii_write(esw, 0, 20, 0x015a);
660 rt305x_mii_write(esw, 0, 21, 0x00ee);
661 rt305x_mii_write(esw, 0, 22, 0x0033);
662 rt305x_mii_write(esw, 0, 23, 0x020a);
663 rt305x_mii_write(esw, 0, 24, 0x0000);
664 rt305x_mii_write(esw, 0, 25, 0x024a);
665 rt305x_mii_write(esw, 0, 26, 0x035a);
666 rt305x_mii_write(esw, 0, 27, 0x02ee);
667 rt305x_mii_write(esw, 0, 28, 0x0233);
668 rt305x_mii_write(esw, 0, 29, 0x000a);
669 rt305x_mii_write(esw, 0, 30, 0x0000);
670 } else {
671 rt305x_mii_write(esw, 0, 31, 0x8000);
672 for (i = 0; i < 5; i++) {
673 if (esw->ports[i].disable) {
674 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
675 } else {
676 rt305x_mii_write(esw, i, MII_BMCR,
677 BMCR_FULLDPLX |
678 BMCR_ANENABLE |
679 BMCR_SPEED100);
680 }
681 /* TX10 waveform coefficient */
682 rt305x_mii_write(esw, i, 26, 0x1601);
683 /* TX100/TX10 AD/DA current bias */
684 rt305x_mii_write(esw, i, 29, 0x7058);
685 /* TX100 slew rate control */
686 rt305x_mii_write(esw, i, 30, 0x0018);
687 }
688
689 /* PHY IOT */
690 /* select global register */
691 rt305x_mii_write(esw, 0, 31, 0x0);
692 /* tune TP_IDL tail and head waveform */
693 rt305x_mii_write(esw, 0, 22, 0x052f);
694 /* set TX10 signal amplitude threshold to minimum */
695 rt305x_mii_write(esw, 0, 17, 0x0fe0);
696 /* set squelch amplitude to higher threshold */
697 rt305x_mii_write(esw, 0, 18, 0x40ba);
698 /* longer TP_IDL tail length */
699 rt305x_mii_write(esw, 0, 14, 0x65);
700 /* select local register */
701 rt305x_mii_write(esw, 0, 31, 0x8000);
702 }
703
704 if (esw->port_map)
705 port_map = esw->port_map;
706 else
707 port_map = RT305X_ESW_PMAP_LLLLLL;
708
709 /* Unused HW feature, but still nice to be consistent here...
710 * This is also exported to userspace ('lan' attribute) so it's
711 * conveniently usable to decide which ports go into the wan vlan by
712 * default.
713 */
714 esw_rmw(esw, RT305X_ESW_REG_SGC2,
715 RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
716 port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
717
718 /* make the switch leds blink */
719 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
720 esw->ports[i].led = 0x05;
721
722 /* Apply the empty config. */
723 esw_apply_config(&esw->swdev);
724
725 /* Only unmask the port change interrupt */
726 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
727 }
728
729
730 int rt3050_esw_has_carrier(struct fe_priv *priv)
731 {
732 struct rt305x_esw *esw = priv->soc->swpriv;
733 u32 link;
734 int i;
735 bool cpuport;
736
737 link = esw_r32(esw, RT305X_ESW_REG_POA);
738 link >>= RT305X_ESW_POA_LINK_SHIFT;
739 cpuport = link & BIT(RT305X_ESW_PORT6);
740 link &= RT305X_ESW_POA_LINK_MASK;
741 for (i = 0; i <= RT305X_ESW_PORT5; i++) {
742 if (priv->link[i] != (link & BIT(i)))
743 dev_info(esw->dev, "port %d link %s\n", i, link & BIT(i) ? "up" : "down");
744 priv->link[i] = link & BIT(i);
745 }
746
747 return !!link && cpuport;
748 }
749
750 static irqreturn_t esw_interrupt(int irq, void *_esw)
751 {
752 struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
753 u32 status;
754
755 status = esw_r32(esw, RT305X_ESW_REG_ISR);
756 if (status & RT305X_ESW_PORT_ST_CHG) {
757 if (!esw->priv)
758 goto out;
759 if (rt3050_esw_has_carrier(esw->priv))
760 netif_carrier_on(esw->priv->netdev);
761 else
762 netif_carrier_off(esw->priv->netdev);
763 }
764
765 out:
766 esw_w32(esw, status, RT305X_ESW_REG_ISR);
767
768 return IRQ_HANDLED;
769 }
770
771 static int esw_apply_config(struct switch_dev *dev)
772 {
773 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
774 int i;
775 u8 disable = 0;
776 u8 doubletag = 0;
777 u8 en_vlan = 0;
778 u8 untag = 0;
779
780 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
781 u32 vid, vmsc;
782 if (esw->global_vlan_enable) {
783 vid = esw->vlans[i].vid;
784 vmsc = esw->vlans[i].ports;
785 } else {
786 vid = RT305X_ESW_VLAN_NONE;
787 vmsc = RT305X_ESW_PORTS_NONE;
788 }
789 esw_set_vlan_id(esw, i, vid);
790 esw_set_vmsc(esw, i, vmsc);
791 }
792
793 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
794 u32 pvid;
795 disable |= esw->ports[i].disable << i;
796 if (esw->global_vlan_enable) {
797 doubletag |= esw->ports[i].doubletag << i;
798 en_vlan |= 1 << i;
799 untag |= esw->ports[i].untag << i;
800 pvid = esw->ports[i].pvid;
801 } else {
802 int x = esw->alt_vlan_disable ? 0 : 1;
803 doubletag |= x << i;
804 en_vlan |= x << i;
805 untag |= x << i;
806 pvid = 0;
807 }
808 esw_set_pvid(esw, i, pvid);
809 if (i < RT305X_ESW_NUM_LEDS)
810 esw_w32(esw, esw->ports[i].led,
811 RT305X_ESW_REG_P0LED + 4*i);
812 }
813
814 esw_set_gsc(esw);
815 esw_set_port_disable(esw, disable);
816 esw_rmw(esw, RT305X_ESW_REG_SGC2,
817 (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
818 RT305X_ESW_SGC2_DOUBLE_TAG_S),
819 doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
820 esw_rmw(esw, RT305X_ESW_REG_PFC1,
821 RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
822 en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
823 esw_rmw(esw, RT305X_ESW_REG_POC2,
824 RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
825 untag << RT305X_ESW_POC2_UNTAG_EN_S);
826
827 if (!esw->global_vlan_enable) {
828 /*
829 * Still need to put all ports into vlan 0 or they'll be
830 * isolated.
831 * NOTE: vlan 0 is special, no vlan tag is prepended
832 */
833 esw_set_vlan_id(esw, 0, 0);
834 esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
835 }
836
837 return 0;
838 }
839
840 static int esw_reset_switch(struct switch_dev *dev)
841 {
842 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
843
844 esw->global_vlan_enable = 0;
845 memset(esw->ports, 0, sizeof(esw->ports));
846 memset(esw->vlans, 0, sizeof(esw->vlans));
847 esw_hw_init(esw);
848
849 return 0;
850 }
851
852 static int esw_get_vlan_enable(struct switch_dev *dev,
853 const struct switch_attr *attr,
854 struct switch_val *val)
855 {
856 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
857
858 val->value.i = esw->global_vlan_enable;
859
860 return 0;
861 }
862
863 static int esw_set_vlan_enable(struct switch_dev *dev,
864 const struct switch_attr *attr,
865 struct switch_val *val)
866 {
867 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
868
869 esw->global_vlan_enable = val->value.i != 0;
870
871 return 0;
872 }
873
874 static int esw_get_alt_vlan_disable(struct switch_dev *dev,
875 const struct switch_attr *attr,
876 struct switch_val *val)
877 {
878 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
879
880 val->value.i = esw->alt_vlan_disable;
881
882 return 0;
883 }
884
885 static int esw_set_alt_vlan_disable(struct switch_dev *dev,
886 const struct switch_attr *attr,
887 struct switch_val *val)
888 {
889 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
890
891 esw->alt_vlan_disable = val->value.i != 0;
892
893 return 0;
894 }
895
896 static int
897 rt305x_esw_set_bc_status(struct switch_dev *dev,
898 const struct switch_attr *attr,
899 struct switch_val *val)
900 {
901 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
902
903 esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
904
905 return 0;
906 }
907
908 static int
909 rt305x_esw_get_bc_status(struct switch_dev *dev,
910 const struct switch_attr *attr,
911 struct switch_val *val)
912 {
913 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
914
915 val->value.i = esw->bc_storm_protect;
916
917 return 0;
918 }
919
920 static int
921 rt305x_esw_set_led_freq(struct switch_dev *dev,
922 const struct switch_attr *attr,
923 struct switch_val *val)
924 {
925 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
926
927 esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
928
929 return 0;
930 }
931
932 static int
933 rt305x_esw_get_led_freq(struct switch_dev *dev,
934 const struct switch_attr *attr,
935 struct switch_val *val)
936 {
937 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
938
939 val->value.i = esw->led_frequency;
940
941 return 0;
942 }
943
944 static int esw_get_port_link(struct switch_dev *dev,
945 int port,
946 struct switch_port_link *link)
947 {
948 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
949 u32 speed, poa;
950
951 if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
952 return -EINVAL;
953
954 poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
955
956 link->link = (poa >> RT305X_ESW_LINK_S) & 1;
957 link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
958 if (port < RT305X_ESW_NUM_LEDS) {
959 speed = (poa >> RT305X_ESW_SPD_S) & 1;
960 } else {
961 if (port == RT305X_ESW_NUM_PORTS - 1)
962 poa >>= 1;
963 speed = (poa >> RT305X_ESW_SPD_S) & 3;
964 }
965 switch (speed) {
966 case 0:
967 link->speed = SWITCH_PORT_SPEED_10;
968 break;
969 case 1:
970 link->speed = SWITCH_PORT_SPEED_100;
971 break;
972 case 2:
973 case 3: /* forced gige speed can be 2 or 3 */
974 link->speed = SWITCH_PORT_SPEED_1000;
975 break;
976 default:
977 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
978 break;
979 }
980
981 return 0;
982 }
983
984 static int esw_get_port_bool(struct switch_dev *dev,
985 const struct switch_attr *attr,
986 struct switch_val *val)
987 {
988 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
989 int idx = val->port_vlan;
990 u32 x, reg, shift;
991
992 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
993 return -EINVAL;
994
995 switch (attr->id) {
996 case RT305X_ESW_ATTR_PORT_DISABLE:
997 reg = RT305X_ESW_REG_POC0;
998 shift = RT305X_ESW_POC0_DIS_PORT_S;
999 break;
1000 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1001 reg = RT305X_ESW_REG_SGC2;
1002 shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1003 break;
1004 case RT305X_ESW_ATTR_PORT_UNTAG:
1005 reg = RT305X_ESW_REG_POC2;
1006 shift = RT305X_ESW_POC2_UNTAG_EN_S;
1007 break;
1008 case RT305X_ESW_ATTR_PORT_LAN:
1009 reg = RT305X_ESW_REG_SGC2;
1010 shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1011 if (idx >= RT305X_ESW_NUM_LANWAN)
1012 return -EINVAL;
1013 break;
1014 default:
1015 return -EINVAL;
1016 }
1017
1018 x = esw_r32(esw, reg);
1019 val->value.i = (x >> (idx + shift)) & 1;
1020
1021 return 0;
1022 }
1023
1024 static int esw_set_port_bool(struct switch_dev *dev,
1025 const struct switch_attr *attr,
1026 struct switch_val *val)
1027 {
1028 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1029 int idx = val->port_vlan;
1030
1031 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1032 val->value.i < 0 || val->value.i > 1)
1033 return -EINVAL;
1034
1035 switch (attr->id) {
1036 case RT305X_ESW_ATTR_PORT_DISABLE:
1037 esw->ports[idx].disable = val->value.i;
1038 break;
1039 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1040 esw->ports[idx].doubletag = val->value.i;
1041 break;
1042 case RT305X_ESW_ATTR_PORT_UNTAG:
1043 esw->ports[idx].untag = val->value.i;
1044 break;
1045 default:
1046 return -EINVAL;
1047 }
1048
1049 return 0;
1050 }
1051
1052 static int esw_get_port_recv_badgood(struct switch_dev *dev,
1053 const struct switch_attr *attr,
1054 struct switch_val *val)
1055 {
1056 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1057 int idx = val->port_vlan;
1058 int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1059 u32 reg;
1060
1061 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1062 return -EINVAL;
1063 reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1064 val->value.i = (reg >> shift) & 0xffff;
1065
1066 return 0;
1067 }
1068
1069 static int
1070 esw_get_port_tr_badgood(struct switch_dev *dev,
1071 const struct switch_attr *attr,
1072 struct switch_val *val)
1073 {
1074 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1075
1076 int idx = val->port_vlan;
1077 int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1078 u32 reg;
1079
1080 if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN) && (ralink_soc != MT762X_SOC_MT7688))
1081 return -EINVAL;
1082
1083 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1084 return -EINVAL;
1085
1086 reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1087 val->value.i = (reg >> shift) & 0xffff;
1088
1089 return 0;
1090 }
1091
1092 static int esw_get_port_led(struct switch_dev *dev,
1093 const struct switch_attr *attr,
1094 struct switch_val *val)
1095 {
1096 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1097 int idx = val->port_vlan;
1098
1099 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1100 idx >= RT305X_ESW_NUM_LEDS)
1101 return -EINVAL;
1102
1103 val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1104
1105 return 0;
1106 }
1107
1108 static int esw_set_port_led(struct switch_dev *dev,
1109 const struct switch_attr *attr,
1110 struct switch_val *val)
1111 {
1112 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1113 int idx = val->port_vlan;
1114
1115 if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1116 return -EINVAL;
1117
1118 esw->ports[idx].led = val->value.i;
1119
1120 return 0;
1121 }
1122
1123 static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1124 {
1125 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1126
1127 if (port >= RT305X_ESW_NUM_PORTS)
1128 return -EINVAL;
1129
1130 *val = esw_get_pvid(esw, port);
1131
1132 return 0;
1133 }
1134
1135 static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1136 {
1137 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1138
1139 if (port >= RT305X_ESW_NUM_PORTS)
1140 return -EINVAL;
1141
1142 esw->ports[port].pvid = val;
1143
1144 return 0;
1145 }
1146
1147 static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1148 {
1149 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1150 u32 vmsc, poc2;
1151 int vlan_idx = -1;
1152 int i;
1153
1154 val->len = 0;
1155
1156 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1157 return -EINVAL;
1158
1159 /* valid vlan? */
1160 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1161 if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1162 esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1163 vlan_idx = i;
1164 break;
1165 }
1166 }
1167
1168 if (vlan_idx == -1)
1169 return -EINVAL;
1170
1171 vmsc = esw_get_vmsc(esw, vlan_idx);
1172 poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1173
1174 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1175 struct switch_port *p;
1176 int port_mask = 1 << i;
1177
1178 if (!(vmsc & port_mask))
1179 continue;
1180
1181 p = &val->value.ports[val->len++];
1182 p->id = i;
1183 if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1184 p->flags = 0;
1185 else
1186 p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1187 }
1188
1189 return 0;
1190 }
1191
1192 static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1193 {
1194 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1195 int ports;
1196 int vlan_idx = -1;
1197 int i;
1198
1199 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1200 val->len > RT305X_ESW_NUM_PORTS)
1201 return -EINVAL;
1202
1203 /* one of the already defined vlans? */
1204 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1205 if (esw->vlans[i].vid == val->port_vlan &&
1206 esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1207 vlan_idx = i;
1208 break;
1209 }
1210 }
1211
1212 /* select a free slot */
1213 for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1214 if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1215 vlan_idx = i;
1216 }
1217
1218 /* bail if all slots are in use */
1219 if (vlan_idx == -1)
1220 return -EINVAL;
1221
1222 ports = RT305X_ESW_PORTS_NONE;
1223 for (i = 0; i < val->len; i++) {
1224 struct switch_port *p = &val->value.ports[i];
1225 int port_mask = 1 << p->id;
1226 bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1227
1228 if (p->id >= RT305X_ESW_NUM_PORTS)
1229 return -EINVAL;
1230
1231 ports |= port_mask;
1232 esw->ports[p->id].untag = untagged;
1233 }
1234 esw->vlans[vlan_idx].ports = ports;
1235 if (ports == RT305X_ESW_PORTS_NONE)
1236 esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1237 else
1238 esw->vlans[vlan_idx].vid = val->port_vlan;
1239
1240 return 0;
1241 }
1242
1243 static const struct switch_attr esw_global[] = {
1244 {
1245 .type = SWITCH_TYPE_INT,
1246 .name = "enable_vlan",
1247 .description = "VLAN mode (1:enabled)",
1248 .max = 1,
1249 .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1250 .get = esw_get_vlan_enable,
1251 .set = esw_set_vlan_enable,
1252 },
1253 {
1254 .type = SWITCH_TYPE_INT,
1255 .name = "alternate_vlan_disable",
1256 .description = "Use en_vlan instead of doubletag to disable"
1257 " VLAN mode",
1258 .max = 1,
1259 .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1260 .get = esw_get_alt_vlan_disable,
1261 .set = esw_set_alt_vlan_disable,
1262 },
1263 {
1264 .type = SWITCH_TYPE_INT,
1265 .name = "bc_storm_protect",
1266 .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1267 .max = 3,
1268 .id = RT305X_ESW_ATTR_BC_STATUS,
1269 .get = rt305x_esw_get_bc_status,
1270 .set = rt305x_esw_set_bc_status,
1271 },
1272 {
1273 .type = SWITCH_TYPE_INT,
1274 .name = "led_frequency",
1275 .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1276 .max = 3,
1277 .id = RT305X_ESW_ATTR_LED_FREQ,
1278 .get = rt305x_esw_get_led_freq,
1279 .set = rt305x_esw_set_led_freq,
1280 }
1281 };
1282
1283 static const struct switch_attr esw_port[] = {
1284 {
1285 .type = SWITCH_TYPE_INT,
1286 .name = "disable",
1287 .description = "Port state (1:disabled)",
1288 .max = 1,
1289 .id = RT305X_ESW_ATTR_PORT_DISABLE,
1290 .get = esw_get_port_bool,
1291 .set = esw_set_port_bool,
1292 },
1293 {
1294 .type = SWITCH_TYPE_INT,
1295 .name = "doubletag",
1296 .description = "Double tagging for incoming vlan packets "
1297 "(1:enabled)",
1298 .max = 1,
1299 .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1300 .get = esw_get_port_bool,
1301 .set = esw_set_port_bool,
1302 },
1303 {
1304 .type = SWITCH_TYPE_INT,
1305 .name = "untag",
1306 .description = "Untag (1:strip outgoing vlan tag)",
1307 .max = 1,
1308 .id = RT305X_ESW_ATTR_PORT_UNTAG,
1309 .get = esw_get_port_bool,
1310 .set = esw_set_port_bool,
1311 },
1312 {
1313 .type = SWITCH_TYPE_INT,
1314 .name = "led",
1315 .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1316 " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1317 " 8:100mact, 10:blink, 11:off, 12:on)",
1318 .max = 15,
1319 .id = RT305X_ESW_ATTR_PORT_LED,
1320 .get = esw_get_port_led,
1321 .set = esw_set_port_led,
1322 },
1323 {
1324 .type = SWITCH_TYPE_INT,
1325 .name = "lan",
1326 .description = "HW port group (0:wan, 1:lan)",
1327 .max = 1,
1328 .id = RT305X_ESW_ATTR_PORT_LAN,
1329 .get = esw_get_port_bool,
1330 },
1331 {
1332 .type = SWITCH_TYPE_INT,
1333 .name = "recv_bad",
1334 .description = "Receive bad packet counter",
1335 .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1336 .get = esw_get_port_recv_badgood,
1337 },
1338 {
1339 .type = SWITCH_TYPE_INT,
1340 .name = "recv_good",
1341 .description = "Receive good packet counter",
1342 .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1343 .get = esw_get_port_recv_badgood,
1344 },
1345 {
1346 .type = SWITCH_TYPE_INT,
1347 .name = "tr_bad",
1348
1349 .description = "Transmit bad packet counter. rt5350 only",
1350 .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1351 .get = esw_get_port_tr_badgood,
1352 },
1353 {
1354 .type = SWITCH_TYPE_INT,
1355 .name = "tr_good",
1356
1357 .description = "Transmit good packet counter. rt5350 only",
1358 .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1359 .get = esw_get_port_tr_badgood,
1360 },
1361 };
1362
1363 static const struct switch_attr esw_vlan[] = {
1364 };
1365
1366 static const struct switch_dev_ops esw_ops = {
1367 .attr_global = {
1368 .attr = esw_global,
1369 .n_attr = ARRAY_SIZE(esw_global),
1370 },
1371 .attr_port = {
1372 .attr = esw_port,
1373 .n_attr = ARRAY_SIZE(esw_port),
1374 },
1375 .attr_vlan = {
1376 .attr = esw_vlan,
1377 .n_attr = ARRAY_SIZE(esw_vlan),
1378 },
1379 .get_vlan_ports = esw_get_vlan_ports,
1380 .set_vlan_ports = esw_set_vlan_ports,
1381 .get_port_pvid = esw_get_port_pvid,
1382 .set_port_pvid = esw_set_port_pvid,
1383 .get_port_link = esw_get_port_link,
1384 .apply_config = esw_apply_config,
1385 .reset_switch = esw_reset_switch,
1386 };
1387
1388 static int esw_probe(struct platform_device *pdev)
1389 {
1390 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1391 struct device_node *np = pdev->dev.of_node;
1392 const __be32 *port_map, *port_disable, *reg_init;
1393 struct rt305x_esw *esw;
1394
1395 esw = devm_kzalloc(&pdev->dev, sizeof(*esw), GFP_KERNEL);
1396 if (!esw)
1397 return -ENOMEM;
1398
1399 esw->dev = &pdev->dev;
1400 esw->irq = irq_of_parse_and_map(np, 0);
1401 esw->base = devm_ioremap_resource(&pdev->dev, res);
1402 if (IS_ERR(esw->base))
1403 return PTR_ERR(esw->base);
1404
1405 port_map = of_get_property(np, "mediatek,portmap", NULL);
1406 if (port_map)
1407 esw->port_map = be32_to_cpu(*port_map);
1408
1409 port_disable = of_get_property(np, "mediatek,portdisable", NULL);
1410 if (port_disable)
1411 esw->port_disable = be32_to_cpu(*port_disable);
1412
1413 reg_init = of_get_property(np, "ralink,fct2", NULL);
1414 if (reg_init)
1415 esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1416
1417 reg_init = of_get_property(np, "ralink,fpa2", NULL);
1418 if (reg_init)
1419 esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1420
1421 reg_init = of_get_property(np, "mediatek,led_polarity", NULL);
1422 if (reg_init)
1423 esw->reg_led_polarity = be32_to_cpu(*reg_init);
1424
1425 reg_init = of_get_property(np, "mediatek,led_source", NULL);
1426 if (reg_init)
1427 esw->reg_led_source = be32_to_cpu(*reg_init);
1428
1429 esw->rst_ephy = devm_reset_control_get_exclusive(&pdev->dev, "ephy");
1430 if (IS_ERR(esw->rst_ephy)) {
1431 dev_err(esw->dev, "failed to get EPHY reset: %pe\n", esw->rst_ephy);
1432 esw->rst_ephy = NULL;
1433 }
1434
1435 spin_lock_init(&esw->reg_rw_lock);
1436 platform_set_drvdata(pdev, esw);
1437
1438 return 0;
1439 }
1440
1441 static int esw_remove(struct platform_device *pdev)
1442 {
1443 struct rt305x_esw *esw = platform_get_drvdata(pdev);
1444
1445 if (esw) {
1446 esw_w32(esw, ~0, RT305X_ESW_REG_IMR);
1447 platform_set_drvdata(pdev, NULL);
1448 }
1449
1450 return 0;
1451 }
1452
1453 static const struct of_device_id ralink_esw_match[] = {
1454 { .compatible = "ralink,rt3050-esw" },
1455 {},
1456 };
1457 MODULE_DEVICE_TABLE(of, ralink_esw_match);
1458
1459 /* called by the ethernet driver to bound with the switch driver */
1460 int rt3050_esw_init(struct fe_priv *priv)
1461 {
1462 struct device_node *np = priv->switch_np;
1463 struct platform_device *pdev = of_find_device_by_node(np);
1464 struct switch_dev *swdev;
1465 struct rt305x_esw *esw;
1466 const __be32 *rgmii;
1467 int ret;
1468
1469 if (!pdev)
1470 return -ENODEV;
1471
1472 if (!of_device_is_compatible(np, ralink_esw_match->compatible))
1473 return -EINVAL;
1474
1475 esw = platform_get_drvdata(pdev);
1476 if (!esw)
1477 return -EPROBE_DEFER;
1478
1479 priv->soc->swpriv = esw;
1480 esw->priv = priv;
1481
1482 esw_hw_init(esw);
1483
1484 rgmii = of_get_property(np, "ralink,rgmii", NULL);
1485 if (rgmii && be32_to_cpu(*rgmii) == 1) {
1486 /*
1487 * External switch connected to RGMII interface.
1488 * Unregister the switch device after initialization.
1489 */
1490 dev_err(&pdev->dev, "RGMII mode, not exporting switch device.\n");
1491 unregister_switch(&esw->swdev);
1492 platform_set_drvdata(pdev, NULL);
1493 return -ENODEV;
1494 }
1495
1496 swdev = &esw->swdev;
1497 swdev->of_node = pdev->dev.of_node;
1498 swdev->name = "rt305x-esw";
1499 swdev->alias = "rt305x";
1500 swdev->cpu_port = RT305X_ESW_PORT6;
1501 swdev->ports = RT305X_ESW_NUM_PORTS;
1502 swdev->vlans = RT305X_ESW_NUM_VIDS;
1503 swdev->ops = &esw_ops;
1504
1505 ret = register_switch(swdev, NULL);
1506 if (ret < 0) {
1507 dev_err(&pdev->dev, "register_switch failed\n");
1508 return ret;
1509 }
1510
1511 ret = devm_request_irq(&pdev->dev, esw->irq, esw_interrupt, 0, "esw",
1512 esw);
1513 if (!ret) {
1514 esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1515 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1516 }
1517
1518 dev_info(&pdev->dev, "mediatek esw at 0x%08lx, irq %d initialized\n",
1519 (long unsigned int)esw->base, esw->irq);
1520
1521 return 0;
1522 }
1523
1524 static struct platform_driver esw_driver = {
1525 .probe = esw_probe,
1526 .remove = esw_remove,
1527 .driver = {
1528 .name = "rt3050-esw",
1529 .owner = THIS_MODULE,
1530 .of_match_table = ralink_esw_match,
1531 },
1532 };
1533
1534 module_platform_driver(esw_driver);
1535
1536 MODULE_LICENSE("GPL");
1537 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1538 MODULE_DESCRIPTION("Switch driver for RT305X SoC");
1539 MODULE_VERSION(MTK_FE_DRV_VERSION);
Staging tree of Stijn Tintel