2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
32 #include <asm/mach-ralink/ralink_regs.h>
34 #include "ralink_soc_eth.h"
36 #include <linux/ioport.h>
37 #include <linux/switch.h>
38 #include <linux/mii.h>
40 #include <ralink_regs.h>
42 #include <asm/mach-ralink/rt305x_esw_platform.h>
45 * HW limitations for this switch:
46 * - No large frame support (PKT_MAX_LEN at most 1536)
47 * - Can't have untagged vlan and tagged vlan on one port at the same time,
48 * though this might be possible using the undocumented PPE.
51 #define RT305X_ESW_REG_ISR 0x00
52 #define RT305X_ESW_REG_IMR 0x04
53 #define RT305X_ESW_REG_FCT0 0x08
54 #define RT305X_ESW_REG_PFC1 0x14
55 #define RT305X_ESW_REG_ATS 0x24
56 #define RT305X_ESW_REG_ATS0 0x28
57 #define RT305X_ESW_REG_ATS1 0x2c
58 #define RT305X_ESW_REG_ATS2 0x30
59 #define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
60 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
61 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
62 #define RT305X_ESW_REG_POA 0x80
63 #define RT305X_ESW_REG_FPA 0x84
64 #define RT305X_ESW_REG_SOCPC 0x8c
65 #define RT305X_ESW_REG_POC0 0x90
66 #define RT305X_ESW_REG_POC1 0x94
67 #define RT305X_ESW_REG_POC2 0x98
68 #define RT305X_ESW_REG_SGC 0x9c
69 #define RT305X_ESW_REG_STRT 0xa0
70 #define RT305X_ESW_REG_PCR0 0xc0
71 #define RT305X_ESW_REG_PCR1 0xc4
72 #define RT305X_ESW_REG_FPA2 0xc8
73 #define RT305X_ESW_REG_FCT2 0xcc
74 #define RT305X_ESW_REG_SGC2 0xe4
75 #define RT305X_ESW_REG_P0LED 0xa4
76 #define RT305X_ESW_REG_P1LED 0xa8
77 #define RT305X_ESW_REG_P2LED 0xac
78 #define RT305X_ESW_REG_P3LED 0xb0
79 #define RT305X_ESW_REG_P4LED 0xb4
80 #define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
81 #define RT305X_ESW_REG_P1PC 0xec
82 #define RT305X_ESW_REG_P2PC 0xf0
83 #define RT305X_ESW_REG_P3PC 0xf4
84 #define RT305X_ESW_REG_P4PC 0xf8
85 #define RT305X_ESW_REG_P5PC 0xfc
87 #define RT305X_ESW_LED_LINK 0
88 #define RT305X_ESW_LED_100M 1
89 #define RT305X_ESW_LED_DUPLEX 2
90 #define RT305X_ESW_LED_ACTIVITY 3
91 #define RT305X_ESW_LED_COLLISION 4
92 #define RT305X_ESW_LED_LINKACT 5
93 #define RT305X_ESW_LED_DUPLCOLL 6
94 #define RT305X_ESW_LED_10MACT 7
95 #define RT305X_ESW_LED_100MACT 8
96 /* Additional led states not in datasheet: */
97 #define RT305X_ESW_LED_BLINK 10
98 #define RT305X_ESW_LED_ON 12
100 #define RT305X_ESW_LINK_S 25
101 #define RT305X_ESW_DUPLEX_S 9
102 #define RT305X_ESW_SPD_S 0
104 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
105 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
106 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
108 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
110 #define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
111 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
113 #define RT305X_ESW_PVIDC_PVID_M 0xfff
114 #define RT305X_ESW_PVIDC_PVID_S 12
116 #define RT305X_ESW_VLANI_VID_M 0xfff
117 #define RT305X_ESW_VLANI_VID_S 12
119 #define RT305X_ESW_VMSC_MSC_M 0xff
120 #define RT305X_ESW_VMSC_MSC_S 8
122 #define RT305X_ESW_SOCPC_DISUN2CPU_S 0
123 #define RT305X_ESW_SOCPC_DISMC2CPU_S 8
124 #define RT305X_ESW_SOCPC_DISBC2CPU_S 16
125 #define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
127 #define RT305X_ESW_POC0_EN_BP_S 0
128 #define RT305X_ESW_POC0_EN_FC_S 8
129 #define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
130 #define RT305X_ESW_POC0_DIS_PORT_M 0x7f
131 #define RT305X_ESW_POC0_DIS_PORT_S 23
133 #define RT305X_ESW_POC2_UNTAG_EN_M 0xff
134 #define RT305X_ESW_POC2_UNTAG_EN_S 0
135 #define RT305X_ESW_POC2_ENAGING_S 8
136 #define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
138 #define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
139 #define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
140 #define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
141 #define RT305X_ESW_SGC2_LAN_PMAP_S 24
143 #define RT305X_ESW_PFC1_EN_VLAN_M 0xff
144 #define RT305X_ESW_PFC1_EN_VLAN_S 16
145 #define RT305X_ESW_PFC1_EN_TOS_S 24
147 #define RT305X_ESW_VLAN_NONE 0xfff
149 #define RT305X_ESW_GSC_BC_STROM_MASK 0x3
150 #define RT305X_ESW_GSC_BC_STROM_SHIFT 4
152 #define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
153 #define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
155 #define RT305X_ESW_POA_LINK_MASK 0x1f
156 #define RT305X_ESW_POA_LINK_SHIFT 25
158 #define RT305X_ESW_PORT_ST_CHG BIT(26)
159 #define RT305X_ESW_PORT0 0
160 #define RT305X_ESW_PORT1 1
161 #define RT305X_ESW_PORT2 2
162 #define RT305X_ESW_PORT3 3
163 #define RT305X_ESW_PORT4 4
164 #define RT305X_ESW_PORT5 5
165 #define RT305X_ESW_PORT6 6
167 #define RT305X_ESW_PORTS_NONE 0
169 #define RT305X_ESW_PMAP_LLLLLL 0x3f
170 #define RT305X_ESW_PMAP_LLLLWL 0x2f
171 #define RT305X_ESW_PMAP_WLLLLL 0x3e
173 #define RT305X_ESW_PORTS_INTERNAL \
174 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
175 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
176 BIT(RT305X_ESW_PORT4))
178 #define RT305X_ESW_PORTS_NOCPU \
179 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
181 #define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
183 #define RT305X_ESW_PORTS_ALL \
184 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
186 #define RT305X_ESW_NUM_VLANS 16
187 #define RT305X_ESW_NUM_VIDS 4096
188 #define RT305X_ESW_NUM_PORTS 7
189 #define RT305X_ESW_NUM_LANWAN 6
190 #define RT305X_ESW_NUM_LEDS 5
192 #define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
193 #define RT5350_EWS_REG_LED_POLARITY 0x168
194 #define RT5350_RESET_EPHY BIT(24)
197 /* Global attributes. */
198 RT305X_ESW_ATTR_ENABLE_VLAN
,
199 RT305X_ESW_ATTR_ALT_VLAN_DISABLE
,
200 RT305X_ESW_ATTR_BC_STATUS
,
201 RT305X_ESW_ATTR_LED_FREQ
,
202 /* Port attributes. */
203 RT305X_ESW_ATTR_PORT_DISABLE
,
204 RT305X_ESW_ATTR_PORT_DOUBLETAG
,
205 RT305X_ESW_ATTR_PORT_UNTAG
,
206 RT305X_ESW_ATTR_PORT_LED
,
207 RT305X_ESW_ATTR_PORT_LAN
,
208 RT305X_ESW_ATTR_PORT_RECV_BAD
,
209 RT305X_ESW_ATTR_PORT_RECV_GOOD
,
210 RT5350_ESW_ATTR_PORT_TR_BAD
,
211 RT5350_ESW_ATTR_PORT_TR_GOOD
,
231 const struct rt305x_esw_platform_data
*pdata
;
232 /* Protects against concurrent register rmw operations. */
233 spinlock_t reg_rw_lock
;
235 unsigned char port_map
;
236 unsigned int reg_initval_fct2
;
237 unsigned int reg_initval_fpa2
;
238 unsigned int reg_led_polarity
;
241 struct switch_dev swdev
;
242 bool global_vlan_enable
;
243 bool alt_vlan_disable
;
244 int bc_storm_protect
;
246 struct esw_vlan vlans
[RT305X_ESW_NUM_VLANS
];
247 struct esw_port ports
[RT305X_ESW_NUM_PORTS
];
251 static inline void esw_w32(struct rt305x_esw
*esw
, u32 val
, unsigned reg
)
253 __raw_writel(val
, esw
->base
+ reg
);
256 static inline u32
esw_r32(struct rt305x_esw
*esw
, unsigned reg
)
258 return __raw_readl(esw
->base
+ reg
);
261 static inline void esw_rmw_raw(struct rt305x_esw
*esw
, unsigned reg
, unsigned long mask
,
266 t
= __raw_readl(esw
->base
+ reg
) & ~mask
;
267 __raw_writel(t
| val
, esw
->base
+ reg
);
270 static void esw_rmw(struct rt305x_esw
*esw
, unsigned reg
, unsigned long mask
,
275 spin_lock_irqsave(&esw
->reg_rw_lock
, flags
);
276 esw_rmw_raw(esw
, reg
, mask
, val
);
277 spin_unlock_irqrestore(&esw
->reg_rw_lock
, flags
);
280 static u32
rt305x_mii_write(struct rt305x_esw
*esw
, u32 phy_addr
, u32 phy_register
,
283 unsigned long t_start
= jiffies
;
287 if (!(esw_r32(esw
, RT305X_ESW_REG_PCR1
) &
288 RT305X_ESW_PCR1_WT_DONE
))
290 if (time_after(jiffies
, t_start
+ RT305X_ESW_PHY_TIMEOUT
)) {
296 write_data
&= 0xffff;
298 (write_data
<< RT305X_ESW_PCR0_WT_NWAY_DATA_S
) |
299 (phy_register
<< RT305X_ESW_PCR0_CPU_PHY_REG_S
) |
300 (phy_addr
) | RT305X_ESW_PCR0_WT_PHY_CMD
,
301 RT305X_ESW_REG_PCR0
);
305 if (esw_r32(esw
, RT305X_ESW_REG_PCR1
) &
306 RT305X_ESW_PCR1_WT_DONE
)
309 if (time_after(jiffies
, t_start
+ RT305X_ESW_PHY_TIMEOUT
)) {
316 printk(KERN_ERR
"ramips_eth: MDIO timeout\n");
320 static unsigned esw_get_vlan_id(struct rt305x_esw
*esw
, unsigned vlan
)
325 s
= RT305X_ESW_VLANI_VID_S
* (vlan
% 2);
326 val
= esw_r32(esw
, RT305X_ESW_REG_VLANI(vlan
/ 2));
327 val
= (val
>> s
) & RT305X_ESW_VLANI_VID_M
;
332 static void esw_set_vlan_id(struct rt305x_esw
*esw
, unsigned vlan
, unsigned vid
)
336 s
= RT305X_ESW_VLANI_VID_S
* (vlan
% 2);
338 RT305X_ESW_REG_VLANI(vlan
/ 2),
339 RT305X_ESW_VLANI_VID_M
<< s
,
340 (vid
& RT305X_ESW_VLANI_VID_M
) << s
);
343 static unsigned esw_get_pvid(struct rt305x_esw
*esw
, unsigned port
)
347 s
= RT305X_ESW_PVIDC_PVID_S
* (port
% 2);
348 val
= esw_r32(esw
, RT305X_ESW_REG_PVIDC(port
/ 2));
349 return (val
>> s
) & RT305X_ESW_PVIDC_PVID_M
;
352 static void esw_set_pvid(struct rt305x_esw
*esw
, unsigned port
, unsigned pvid
)
356 s
= RT305X_ESW_PVIDC_PVID_S
* (port
% 2);
358 RT305X_ESW_REG_PVIDC(port
/ 2),
359 RT305X_ESW_PVIDC_PVID_M
<< s
,
360 (pvid
& RT305X_ESW_PVIDC_PVID_M
) << s
);
363 static unsigned esw_get_vmsc(struct rt305x_esw
*esw
, unsigned vlan
)
367 s
= RT305X_ESW_VMSC_MSC_S
* (vlan
% 4);
368 val
= esw_r32(esw
, RT305X_ESW_REG_VMSC(vlan
/ 4));
369 val
= (val
>> s
) & RT305X_ESW_VMSC_MSC_M
;
374 static void esw_set_vmsc(struct rt305x_esw
*esw
, unsigned vlan
, unsigned msc
)
378 s
= RT305X_ESW_VMSC_MSC_S
* (vlan
% 4);
380 RT305X_ESW_REG_VMSC(vlan
/ 4),
381 RT305X_ESW_VMSC_MSC_M
<< s
,
382 (msc
& RT305X_ESW_VMSC_MSC_M
) << s
);
385 static unsigned esw_get_port_disable(struct rt305x_esw
*esw
)
388 reg
= esw_r32(esw
, RT305X_ESW_REG_POC0
);
389 return (reg
>> RT305X_ESW_POC0_DIS_PORT_S
) &
390 RT305X_ESW_POC0_DIS_PORT_M
;
393 static void esw_set_port_disable(struct rt305x_esw
*esw
, unsigned disable_mask
)
396 unsigned enable_mask
;
400 old_mask
= esw_get_port_disable(esw
);
401 changed
= old_mask
^ disable_mask
;
402 enable_mask
= old_mask
& disable_mask
;
404 /* enable before writing to MII */
405 esw_rmw(esw
, RT305X_ESW_REG_POC0
,
406 (RT305X_ESW_POC0_DIS_PORT_M
<<
407 RT305X_ESW_POC0_DIS_PORT_S
),
408 enable_mask
<< RT305X_ESW_POC0_DIS_PORT_S
);
410 for (i
= 0; i
< RT305X_ESW_NUM_LEDS
; i
++) {
411 if (!(changed
& (1 << i
)))
413 if (disable_mask
& (1 << i
)) {
415 rt305x_mii_write(esw
, i
, MII_BMCR
,
419 rt305x_mii_write(esw
, i
, MII_BMCR
,
427 /* disable after writing to MII */
428 esw_rmw(esw
, RT305X_ESW_REG_POC0
,
429 (RT305X_ESW_POC0_DIS_PORT_M
<<
430 RT305X_ESW_POC0_DIS_PORT_S
),
431 disable_mask
<< RT305X_ESW_POC0_DIS_PORT_S
);
434 static void esw_set_gsc(struct rt305x_esw
*esw
)
436 esw_rmw(esw
, RT305X_ESW_REG_SGC
,
437 RT305X_ESW_GSC_BC_STROM_MASK
<< RT305X_ESW_GSC_BC_STROM_SHIFT
,
438 esw
->bc_storm_protect
<< RT305X_ESW_GSC_BC_STROM_SHIFT
);
439 esw_rmw(esw
, RT305X_ESW_REG_SGC
,
440 RT305X_ESW_GSC_LED_FREQ_MASK
<< RT305X_ESW_GSC_LED_FREQ_SHIFT
,
441 esw
->led_frequency
<< RT305X_ESW_GSC_LED_FREQ_SHIFT
);
444 static int esw_apply_config(struct switch_dev
*dev
);
446 static void esw_hw_init(struct rt305x_esw
*esw
)
450 u8 port_map
= RT305X_ESW_PMAP_LLLLLL
;
452 /* vodoo from original driver */
453 esw_w32(esw
, 0xC8A07850, RT305X_ESW_REG_FCT0
);
454 esw_w32(esw
, 0x00000000, RT305X_ESW_REG_SGC2
);
455 /* Port priority 1 for all ports, vlan enabled. */
456 esw_w32(esw
, 0x00005555 |
457 (RT305X_ESW_PORTS_ALL
<< RT305X_ESW_PFC1_EN_VLAN_S
),
458 RT305X_ESW_REG_PFC1
);
460 /* Enable Back Pressure, and Flow Control */
462 ((RT305X_ESW_PORTS_ALL
<< RT305X_ESW_POC0_EN_BP_S
) |
463 (RT305X_ESW_PORTS_ALL
<< RT305X_ESW_POC0_EN_FC_S
)),
464 RT305X_ESW_REG_POC0
);
466 /* Enable Aging, and VLAN TAG removal */
468 ((RT305X_ESW_PORTS_ALL
<< RT305X_ESW_POC2_ENAGING_S
) |
469 (RT305X_ESW_PORTS_NOCPU
<< RT305X_ESW_POC2_UNTAG_EN_S
)),
470 RT305X_ESW_REG_POC2
);
472 if (esw
->reg_initval_fct2
)
473 esw_w32(esw
, esw
->reg_initval_fct2
, RT305X_ESW_REG_FCT2
);
475 esw_w32(esw
, esw
->pdata
->reg_initval_fct2
, RT305X_ESW_REG_FCT2
);
478 * 300s aging timer, max packet len 1536, broadcast storm prevention
479 * disabled, disable collision abort, mac xor48 hash, 10 packet back
480 * pressure jam, GMII disable was_transmit, back pressure disabled,
481 * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
484 esw_w32(esw
, 0x0008a301, RT305X_ESW_REG_SGC
);
486 /* Setup SoC Port control register */
488 (RT305X_ESW_SOCPC_CRC_PADDING
|
489 (RT305X_ESW_PORTS_CPU
<< RT305X_ESW_SOCPC_DISUN2CPU_S
) |
490 (RT305X_ESW_PORTS_CPU
<< RT305X_ESW_SOCPC_DISMC2CPU_S
) |
491 (RT305X_ESW_PORTS_CPU
<< RT305X_ESW_SOCPC_DISBC2CPU_S
)),
492 RT305X_ESW_REG_SOCPC
);
494 if (esw
->reg_initval_fpa2
)
495 esw_w32(esw
, esw
->reg_initval_fpa2
, RT305X_ESW_REG_FPA2
);
497 esw_w32(esw
, esw
->pdata
->reg_initval_fpa2
, RT305X_ESW_REG_FPA2
);
498 esw_w32(esw
, 0x00000000, RT305X_ESW_REG_FPA
);
500 /* Force Link/Activity on ports */
501 esw_w32(esw
, 0x00000005, RT305X_ESW_REG_P0LED
);
502 esw_w32(esw
, 0x00000005, RT305X_ESW_REG_P1LED
);
503 esw_w32(esw
, 0x00000005, RT305X_ESW_REG_P2LED
);
504 esw_w32(esw
, 0x00000005, RT305X_ESW_REG_P3LED
);
505 esw_w32(esw
, 0x00000005, RT305X_ESW_REG_P4LED
);
507 /* Copy disabled port configuration from bootloader setup */
508 port_disable
= esw_get_port_disable(esw
);
509 for (i
= 0; i
< 6; i
++)
510 esw
->ports
[i
].disable
= (port_disable
& (1 << i
)) != 0;
512 if (ralink_soc
== RT305X_SOC_RT3352
) {
514 fe_reset(RT5350_RESET_EPHY
);
516 rt305x_mii_write(esw
, 0, 31, 0x8000);
517 for (i
= 0; i
< 5; i
++) {
518 if (esw
->ports
[i
].disable
) {
519 rt305x_mii_write(esw
, i
, MII_BMCR
, BMCR_PDOWN
);
521 rt305x_mii_write(esw
, i
, MII_BMCR
,
526 /* TX10 waveform coefficient LSB=0 disable PHY */
527 rt305x_mii_write(esw
, i
, 26, 0x1601);
528 /* TX100/TX10 AD/DA current bias */
529 rt305x_mii_write(esw
, i
, 29, 0x7016);
530 /* TX100 slew rate control */
531 rt305x_mii_write(esw
, i
, 30, 0x0038);
534 /* select global register */
535 rt305x_mii_write(esw
, 0, 31, 0x0);
536 /* enlarge agcsel threshold 3 and threshold 2 */
537 rt305x_mii_write(esw
, 0, 1, 0x4a40);
538 /* enlarge agcsel threshold 5 and threshold 4 */
539 rt305x_mii_write(esw
, 0, 2, 0x6254);
540 /* enlarge agcsel threshold */
541 rt305x_mii_write(esw
, 0, 3, 0xa17f);
542 rt305x_mii_write(esw
, 0,12, 0x7eaa);
543 /* longer TP_IDL tail length */
544 rt305x_mii_write(esw
, 0, 14, 0x65);
545 /* increased squelch pulse count threshold. */
546 rt305x_mii_write(esw
, 0, 16, 0x0684);
547 /* set TX10 signal amplitude threshold to minimum */
548 rt305x_mii_write(esw
, 0, 17, 0x0fe0);
549 /* set squelch amplitude to higher threshold */
550 rt305x_mii_write(esw
, 0, 18, 0x40ba);
551 /* tune TP_IDL tail and head waveform, enable power down slew rate control */
552 rt305x_mii_write(esw
, 0, 22, 0x253f);
553 /* set PLL/Receive bias current are calibrated */
554 rt305x_mii_write(esw
, 0, 27, 0x2fda);
555 /* change PLL/Receive bias current to internal(RT3350) */
556 rt305x_mii_write(esw
, 0, 28, 0xc410);
557 /* change PLL bias current to internal(RT3052_MP3) */
558 rt305x_mii_write(esw
, 0, 29, 0x598b);
559 /* select local register */
560 rt305x_mii_write(esw
, 0, 31, 0x8000);
561 } else if (ralink_soc
== RT305X_SOC_RT5350
) {
563 fe_reset(RT5350_RESET_EPHY
);
565 /* set the led polarity */
566 esw_w32(esw
, esw
->reg_led_polarity
& 0x1F, RT5350_EWS_REG_LED_POLARITY
);
568 /* local registers */
569 rt305x_mii_write(esw
, 0, 31, 0x8000);
570 for (i
= 0; i
< 5; i
++) {
571 if (esw
->ports
[i
].disable
) {
572 rt305x_mii_write(esw
, i
, MII_BMCR
, BMCR_PDOWN
);
574 rt305x_mii_write(esw
, i
, MII_BMCR
,
579 /* TX10 waveform coefficient LSB=0 disable PHY */
580 rt305x_mii_write(esw
, i
, 26, 0x1601);
581 /* TX100/TX10 AD/DA current bias */
582 rt305x_mii_write(esw
, i
, 29, 0x7015);
583 /* TX100 slew rate control */
584 rt305x_mii_write(esw
, i
, 30, 0x0038);
587 /* global registers */
588 rt305x_mii_write(esw
, 0, 31, 0x0);
589 /* enlarge agcsel threshold 3 and threshold 2 */
590 rt305x_mii_write(esw
, 0, 1, 0x4a40);
591 /* enlarge agcsel threshold 5 and threshold 4 */
592 rt305x_mii_write(esw
, 0, 2, 0x6254);
593 /* enlarge agcsel threshold 6 */
594 rt305x_mii_write(esw
, 0, 3, 0xa17f);
595 rt305x_mii_write(esw
, 0, 12, 0x7eaa);
596 /* longer TP_IDL tail length */
597 rt305x_mii_write(esw
, 0, 14, 0x65);
598 /* increased squelch pulse count threshold. */
599 rt305x_mii_write(esw
, 0, 16, 0x0684);
600 /* set TX10 signal amplitude threshold to minimum */
601 rt305x_mii_write(esw
, 0, 17, 0x0fe0);
602 /* set squelch amplitude to higher threshold */
603 rt305x_mii_write(esw
, 0, 18, 0x40ba);
604 /* tune TP_IDL tail and head waveform, enable power down slew rate control */
605 rt305x_mii_write(esw
, 0, 22, 0x253f);
606 /* set PLL/Receive bias current are calibrated */
607 rt305x_mii_write(esw
, 0, 27, 0x2fda);
608 /* change PLL/Receive bias current to internal(RT3350) */
609 rt305x_mii_write(esw
, 0, 28, 0xc410);
610 /* change PLL bias current to internal(RT3052_MP3) */
611 rt305x_mii_write(esw
, 0, 29, 0x598b);
612 /* select local register */
613 rt305x_mii_write(esw
, 0, 31, 0x8000);
614 } else if (ralink_soc
== MT762X_SOC_MT7628AN
|| ralink_soc
== MT762X_SOC_MT7688
) {
620 fe_reset(RT5350_RESET_EPHY
);
622 rt305x_mii_write(esw
, 0, 31, 0x2000); /* change G2 page */
623 rt305x_mii_write(esw
, 0, 26, 0x0020);
625 for (i
= 0; i
< 5; i
++) {
626 rt305x_mii_write(esw
, i
, 31, 0x8000); //change L0 page
627 rt305x_mii_write(esw
, i
, 0, 0x3100);
628 // mii_mgr_read(i, 26, &phy_val);// EEE setting
629 // phy_val |= (1 << 5);
630 // rt305x_mii_write(esw, i, 26, phy_val);
631 rt305x_mii_write(esw
, i
, 30, 0xa000);
632 rt305x_mii_write(esw
, i
, 31, 0xa000); // change L2 page
633 rt305x_mii_write(esw
, i
, 16, 0x0606);
634 rt305x_mii_write(esw
, i
, 23, 0x0f0e);
635 rt305x_mii_write(esw
, i
, 24, 0x1610);
636 rt305x_mii_write(esw
, i
, 30, 0x1f15);
637 rt305x_mii_write(esw
, i
, 28, 0x6111);
638 // mii_mgr_read(i, 4, &phy_val);
639 // phy_val |= (1 << 10);
640 // rt305x_mii_write(esw, i, 4, phy_val);
641 rt305x_mii_write(esw
, i
, 31, 0x2000); // change G2 page
642 rt305x_mii_write(esw
, i
, 26, 0x0000);
645 //100Base AOI setting
646 rt305x_mii_write(esw
, 0, 31, 0x5000); //change G5 page
647 rt305x_mii_write(esw
, 0, 19, 0x004a);
648 rt305x_mii_write(esw
, 0, 20, 0x015a);
649 rt305x_mii_write(esw
, 0, 21, 0x00ee);
650 rt305x_mii_write(esw
, 0, 22, 0x0033);
651 rt305x_mii_write(esw
, 0, 23, 0x020a);
652 rt305x_mii_write(esw
, 0, 24, 0x0000);
653 rt305x_mii_write(esw
, 0, 25, 0x024a);
654 rt305x_mii_write(esw
, 0, 26, 0x035a);
655 rt305x_mii_write(esw
, 0, 27, 0x02ee);
656 rt305x_mii_write(esw
, 0, 28, 0x0233);
657 rt305x_mii_write(esw
, 0, 29, 0x000a);
658 rt305x_mii_write(esw
, 0, 30, 0x0000);
660 rt305x_mii_write(esw
, 0, 31, 0x8000);
661 for (i
= 0; i
< 5; i
++) {
662 if (esw
->ports
[i
].disable
) {
663 rt305x_mii_write(esw
, i
, MII_BMCR
, BMCR_PDOWN
);
665 rt305x_mii_write(esw
, i
, MII_BMCR
,
670 /* TX10 waveform coefficient */
671 rt305x_mii_write(esw
, i
, 26, 0x1601);
672 /* TX100/TX10 AD/DA current bias */
673 rt305x_mii_write(esw
, i
, 29, 0x7058);
674 /* TX100 slew rate control */
675 rt305x_mii_write(esw
, i
, 30, 0x0018);
679 /* select global register */
680 rt305x_mii_write(esw
, 0, 31, 0x0);
681 /* tune TP_IDL tail and head waveform */
682 rt305x_mii_write(esw
, 0, 22, 0x052f);
683 /* set TX10 signal amplitude threshold to minimum */
684 rt305x_mii_write(esw
, 0, 17, 0x0fe0);
685 /* set squelch amplitude to higher threshold */
686 rt305x_mii_write(esw
, 0, 18, 0x40ba);
687 /* longer TP_IDL tail length */
688 rt305x_mii_write(esw
, 0, 14, 0x65);
689 /* select local register */
690 rt305x_mii_write(esw
, 0, 31, 0x8000);
694 port_map
= esw
->port_map
;
696 port_map
= RT305X_ESW_PMAP_LLLLLL
;
699 * Unused HW feature, but still nice to be consistent here...
700 * This is also exported to userspace ('lan' attribute) so it's
701 * conveniently usable to decide which ports go into the wan vlan by
704 esw_rmw(esw
, RT305X_ESW_REG_SGC2
,
705 RT305X_ESW_SGC2_LAN_PMAP_M
<< RT305X_ESW_SGC2_LAN_PMAP_S
,
706 port_map
<< RT305X_ESW_SGC2_LAN_PMAP_S
);
708 /* make the switch leds blink */
709 for (i
= 0; i
< RT305X_ESW_NUM_LEDS
; i
++)
710 esw
->ports
[i
].led
= 0x05;
712 /* Apply the empty config. */
713 esw_apply_config(&esw
->swdev
);
715 /* Only unmask the port change interrupt */
716 esw_w32(esw
, ~RT305X_ESW_PORT_ST_CHG
, RT305X_ESW_REG_IMR
);
719 static irqreturn_t
esw_interrupt(int irq
, void *_esw
)
721 struct rt305x_esw
*esw
= (struct rt305x_esw
*) _esw
;
724 status
= esw_r32(esw
, RT305X_ESW_REG_ISR
);
725 if (status
& RT305X_ESW_PORT_ST_CHG
) {
726 u32 link
= esw_r32(esw
, RT305X_ESW_REG_POA
);
727 link
>>= RT305X_ESW_POA_LINK_SHIFT
;
728 link
&= RT305X_ESW_POA_LINK_MASK
;
729 dev_info(esw
->dev
, "link changed 0x%02X\n", link
);
731 esw_w32(esw
, status
, RT305X_ESW_REG_ISR
);
736 static int esw_apply_config(struct switch_dev
*dev
)
738 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
745 for (i
= 0; i
< RT305X_ESW_NUM_VLANS
; i
++) {
747 if (esw
->global_vlan_enable
) {
748 vid
= esw
->vlans
[i
].vid
;
749 vmsc
= esw
->vlans
[i
].ports
;
751 vid
= RT305X_ESW_VLAN_NONE
;
752 vmsc
= RT305X_ESW_PORTS_NONE
;
754 esw_set_vlan_id(esw
, i
, vid
);
755 esw_set_vmsc(esw
, i
, vmsc
);
758 for (i
= 0; i
< RT305X_ESW_NUM_PORTS
; i
++) {
760 disable
|= esw
->ports
[i
].disable
<< i
;
761 if (esw
->global_vlan_enable
) {
762 doubletag
|= esw
->ports
[i
].doubletag
<< i
;
764 untag
|= esw
->ports
[i
].untag
<< i
;
765 pvid
= esw
->ports
[i
].pvid
;
767 int x
= esw
->alt_vlan_disable
? 0 : 1;
773 esw_set_pvid(esw
, i
, pvid
);
774 if (i
< RT305X_ESW_NUM_LEDS
)
775 esw_w32(esw
, esw
->ports
[i
].led
,
776 RT305X_ESW_REG_P0LED
+ 4*i
);
780 esw_set_port_disable(esw
, disable
);
781 esw_rmw(esw
, RT305X_ESW_REG_SGC2
,
782 (RT305X_ESW_SGC2_DOUBLE_TAG_M
<<
783 RT305X_ESW_SGC2_DOUBLE_TAG_S
),
784 doubletag
<< RT305X_ESW_SGC2_DOUBLE_TAG_S
);
785 esw_rmw(esw
, RT305X_ESW_REG_PFC1
,
786 RT305X_ESW_PFC1_EN_VLAN_M
<< RT305X_ESW_PFC1_EN_VLAN_S
,
787 en_vlan
<< RT305X_ESW_PFC1_EN_VLAN_S
);
788 esw_rmw(esw
, RT305X_ESW_REG_POC2
,
789 RT305X_ESW_POC2_UNTAG_EN_M
<< RT305X_ESW_POC2_UNTAG_EN_S
,
790 untag
<< RT305X_ESW_POC2_UNTAG_EN_S
);
792 if (!esw
->global_vlan_enable
) {
794 * Still need to put all ports into vlan 0 or they'll be
796 * NOTE: vlan 0 is special, no vlan tag is prepended
798 esw_set_vlan_id(esw
, 0, 0);
799 esw_set_vmsc(esw
, 0, RT305X_ESW_PORTS_ALL
);
805 static int esw_reset_switch(struct switch_dev
*dev
)
807 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
809 esw
->global_vlan_enable
= 0;
810 memset(esw
->ports
, 0, sizeof(esw
->ports
));
811 memset(esw
->vlans
, 0, sizeof(esw
->vlans
));
817 static int esw_get_vlan_enable(struct switch_dev
*dev
,
818 const struct switch_attr
*attr
,
819 struct switch_val
*val
)
821 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
823 val
->value
.i
= esw
->global_vlan_enable
;
828 static int esw_set_vlan_enable(struct switch_dev
*dev
,
829 const struct switch_attr
*attr
,
830 struct switch_val
*val
)
832 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
834 esw
->global_vlan_enable
= val
->value
.i
!= 0;
839 static int esw_get_alt_vlan_disable(struct switch_dev
*dev
,
840 const struct switch_attr
*attr
,
841 struct switch_val
*val
)
843 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
845 val
->value
.i
= esw
->alt_vlan_disable
;
850 static int esw_set_alt_vlan_disable(struct switch_dev
*dev
,
851 const struct switch_attr
*attr
,
852 struct switch_val
*val
)
854 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
856 esw
->alt_vlan_disable
= val
->value
.i
!= 0;
862 rt305x_esw_set_bc_status(struct switch_dev
*dev
,
863 const struct switch_attr
*attr
,
864 struct switch_val
*val
)
866 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
868 esw
->bc_storm_protect
= val
->value
.i
& RT305X_ESW_GSC_BC_STROM_MASK
;
874 rt305x_esw_get_bc_status(struct switch_dev
*dev
,
875 const struct switch_attr
*attr
,
876 struct switch_val
*val
)
878 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
880 val
->value
.i
= esw
->bc_storm_protect
;
886 rt305x_esw_set_led_freq(struct switch_dev
*dev
,
887 const struct switch_attr
*attr
,
888 struct switch_val
*val
)
890 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
892 esw
->led_frequency
= val
->value
.i
& RT305X_ESW_GSC_LED_FREQ_MASK
;
898 rt305x_esw_get_led_freq(struct switch_dev
*dev
,
899 const struct switch_attr
*attr
,
900 struct switch_val
*val
)
902 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
904 val
->value
.i
= esw
->led_frequency
;
909 static int esw_get_port_link(struct switch_dev
*dev
,
911 struct switch_port_link
*link
)
913 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
916 if (port
< 0 || port
>= RT305X_ESW_NUM_PORTS
)
919 poa
= esw_r32(esw
, RT305X_ESW_REG_POA
) >> port
;
921 link
->link
= (poa
>> RT305X_ESW_LINK_S
) & 1;
922 link
->duplex
= (poa
>> RT305X_ESW_DUPLEX_S
) & 1;
923 if (port
< RT305X_ESW_NUM_LEDS
) {
924 speed
= (poa
>> RT305X_ESW_SPD_S
) & 1;
926 if (port
== RT305X_ESW_NUM_PORTS
- 1)
928 speed
= (poa
>> RT305X_ESW_SPD_S
) & 3;
932 link
->speed
= SWITCH_PORT_SPEED_10
;
935 link
->speed
= SWITCH_PORT_SPEED_100
;
938 case 3: /* forced gige speed can be 2 or 3 */
939 link
->speed
= SWITCH_PORT_SPEED_1000
;
942 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
949 static int esw_get_port_bool(struct switch_dev
*dev
,
950 const struct switch_attr
*attr
,
951 struct switch_val
*val
)
953 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
954 int idx
= val
->port_vlan
;
957 if (idx
< 0 || idx
>= RT305X_ESW_NUM_PORTS
)
961 case RT305X_ESW_ATTR_PORT_DISABLE
:
962 reg
= RT305X_ESW_REG_POC0
;
963 shift
= RT305X_ESW_POC0_DIS_PORT_S
;
965 case RT305X_ESW_ATTR_PORT_DOUBLETAG
:
966 reg
= RT305X_ESW_REG_SGC2
;
967 shift
= RT305X_ESW_SGC2_DOUBLE_TAG_S
;
969 case RT305X_ESW_ATTR_PORT_UNTAG
:
970 reg
= RT305X_ESW_REG_POC2
;
971 shift
= RT305X_ESW_POC2_UNTAG_EN_S
;
973 case RT305X_ESW_ATTR_PORT_LAN
:
974 reg
= RT305X_ESW_REG_SGC2
;
975 shift
= RT305X_ESW_SGC2_LAN_PMAP_S
;
976 if (idx
>= RT305X_ESW_NUM_LANWAN
)
983 x
= esw_r32(esw
, reg
);
984 val
->value
.i
= (x
>> (idx
+ shift
)) & 1;
989 static int esw_set_port_bool(struct switch_dev
*dev
,
990 const struct switch_attr
*attr
,
991 struct switch_val
*val
)
993 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
994 int idx
= val
->port_vlan
;
996 if (idx
< 0 || idx
>= RT305X_ESW_NUM_PORTS
||
997 val
->value
.i
< 0 || val
->value
.i
> 1)
1001 case RT305X_ESW_ATTR_PORT_DISABLE
:
1002 esw
->ports
[idx
].disable
= val
->value
.i
;
1004 case RT305X_ESW_ATTR_PORT_DOUBLETAG
:
1005 esw
->ports
[idx
].doubletag
= val
->value
.i
;
1007 case RT305X_ESW_ATTR_PORT_UNTAG
:
1008 esw
->ports
[idx
].untag
= val
->value
.i
;
1017 static int esw_get_port_recv_badgood(struct switch_dev
*dev
,
1018 const struct switch_attr
*attr
,
1019 struct switch_val
*val
)
1021 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1022 int idx
= val
->port_vlan
;
1023 int shift
= attr
->id
== RT305X_ESW_ATTR_PORT_RECV_GOOD
? 0 : 16;
1026 if (idx
< 0 || idx
>= RT305X_ESW_NUM_LANWAN
)
1028 reg
= esw_r32(esw
, RT305X_ESW_REG_PXPC(idx
));
1029 val
->value
.i
= (reg
>> shift
) & 0xffff;
1035 esw_get_port_tr_badgood(struct switch_dev
*dev
,
1036 const struct switch_attr
*attr
,
1037 struct switch_val
*val
)
1039 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1041 int idx
= val
->port_vlan
;
1042 int shift
= attr
->id
== RT5350_ESW_ATTR_PORT_TR_GOOD
? 0 : 16;
1045 if ((ralink_soc
!= RT305X_SOC_RT5350
) && (ralink_soc
!= MT762X_SOC_MT7628AN
) && (ralink_soc
!= MT762X_SOC_MT7688
))
1048 if (idx
< 0 || idx
>= RT305X_ESW_NUM_LANWAN
)
1051 reg
= esw_r32(esw
, RT5350_ESW_REG_PXTPC(idx
));
1052 val
->value
.i
= (reg
>> shift
) & 0xffff;
1057 static int esw_get_port_led(struct switch_dev
*dev
,
1058 const struct switch_attr
*attr
,
1059 struct switch_val
*val
)
1061 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1062 int idx
= val
->port_vlan
;
1064 if (idx
< 0 || idx
>= RT305X_ESW_NUM_PORTS
||
1065 idx
>= RT305X_ESW_NUM_LEDS
)
1068 val
->value
.i
= esw_r32(esw
, RT305X_ESW_REG_P0LED
+ 4*idx
);
1073 static int esw_set_port_led(struct switch_dev
*dev
,
1074 const struct switch_attr
*attr
,
1075 struct switch_val
*val
)
1077 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1078 int idx
= val
->port_vlan
;
1080 if (idx
< 0 || idx
>= RT305X_ESW_NUM_LEDS
)
1083 esw
->ports
[idx
].led
= val
->value
.i
;
1088 static int esw_get_port_pvid(struct switch_dev
*dev
, int port
, int *val
)
1090 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1092 if (port
>= RT305X_ESW_NUM_PORTS
)
1095 *val
= esw_get_pvid(esw
, port
);
1100 static int esw_set_port_pvid(struct switch_dev
*dev
, int port
, int val
)
1102 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1104 if (port
>= RT305X_ESW_NUM_PORTS
)
1107 esw
->ports
[port
].pvid
= val
;
1112 static int esw_get_vlan_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1114 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1121 if (val
->port_vlan
< 0 || val
->port_vlan
>= RT305X_ESW_NUM_VIDS
)
1125 for (i
= 0; i
< RT305X_ESW_NUM_VLANS
; i
++) {
1126 if (esw_get_vlan_id(esw
, i
) == val
->port_vlan
&&
1127 esw_get_vmsc(esw
, i
) != RT305X_ESW_PORTS_NONE
) {
1136 vmsc
= esw_get_vmsc(esw
, vlan_idx
);
1137 poc2
= esw_r32(esw
, RT305X_ESW_REG_POC2
);
1139 for (i
= 0; i
< RT305X_ESW_NUM_PORTS
; i
++) {
1140 struct switch_port
*p
;
1141 int port_mask
= 1 << i
;
1143 if (!(vmsc
& port_mask
))
1146 p
= &val
->value
.ports
[val
->len
++];
1148 if (poc2
& (port_mask
<< RT305X_ESW_POC2_UNTAG_EN_S
))
1151 p
->flags
= 1 << SWITCH_PORT_FLAG_TAGGED
;
1157 static int esw_set_vlan_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1159 struct rt305x_esw
*esw
= container_of(dev
, struct rt305x_esw
, swdev
);
1164 if (val
->port_vlan
< 0 || val
->port_vlan
>= RT305X_ESW_NUM_VIDS
||
1165 val
->len
> RT305X_ESW_NUM_PORTS
)
1168 /* one of the already defined vlans? */
1169 for (i
= 0; i
< RT305X_ESW_NUM_VLANS
; i
++) {
1170 if (esw
->vlans
[i
].vid
== val
->port_vlan
&&
1171 esw
->vlans
[i
].ports
!= RT305X_ESW_PORTS_NONE
) {
1177 /* select a free slot */
1178 for (i
= 0; vlan_idx
== -1 && i
< RT305X_ESW_NUM_VLANS
; i
++) {
1179 if (esw
->vlans
[i
].ports
== RT305X_ESW_PORTS_NONE
)
1183 /* bail if all slots are in use */
1187 ports
= RT305X_ESW_PORTS_NONE
;
1188 for (i
= 0; i
< val
->len
; i
++) {
1189 struct switch_port
*p
= &val
->value
.ports
[i
];
1190 int port_mask
= 1 << p
->id
;
1191 bool untagged
= !(p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
));
1193 if (p
->id
>= RT305X_ESW_NUM_PORTS
)
1197 esw
->ports
[p
->id
].untag
= untagged
;
1199 esw
->vlans
[vlan_idx
].ports
= ports
;
1200 if (ports
== RT305X_ESW_PORTS_NONE
)
1201 esw
->vlans
[vlan_idx
].vid
= RT305X_ESW_VLAN_NONE
;
1203 esw
->vlans
[vlan_idx
].vid
= val
->port_vlan
;
1208 static const struct switch_attr esw_global
[] = {
1210 .type
= SWITCH_TYPE_INT
,
1211 .name
= "enable_vlan",
1212 .description
= "VLAN mode (1:enabled)",
1214 .id
= RT305X_ESW_ATTR_ENABLE_VLAN
,
1215 .get
= esw_get_vlan_enable
,
1216 .set
= esw_set_vlan_enable
,
1219 .type
= SWITCH_TYPE_INT
,
1220 .name
= "alternate_vlan_disable",
1221 .description
= "Use en_vlan instead of doubletag to disable"
1224 .id
= RT305X_ESW_ATTR_ALT_VLAN_DISABLE
,
1225 .get
= esw_get_alt_vlan_disable
,
1226 .set
= esw_set_alt_vlan_disable
,
1229 .type
= SWITCH_TYPE_INT
,
1230 .name
= "bc_storm_protect",
1231 .description
= "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1233 .id
= RT305X_ESW_ATTR_BC_STATUS
,
1234 .get
= rt305x_esw_get_bc_status
,
1235 .set
= rt305x_esw_set_bc_status
,
1238 .type
= SWITCH_TYPE_INT
,
1239 .name
= "led_frequency",
1240 .description
= "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1242 .id
= RT305X_ESW_ATTR_LED_FREQ
,
1243 .get
= rt305x_esw_get_led_freq
,
1244 .set
= rt305x_esw_set_led_freq
,
1248 static const struct switch_attr esw_port
[] = {
1250 .type
= SWITCH_TYPE_INT
,
1252 .description
= "Port state (1:disabled)",
1254 .id
= RT305X_ESW_ATTR_PORT_DISABLE
,
1255 .get
= esw_get_port_bool
,
1256 .set
= esw_set_port_bool
,
1259 .type
= SWITCH_TYPE_INT
,
1260 .name
= "doubletag",
1261 .description
= "Double tagging for incoming vlan packets "
1264 .id
= RT305X_ESW_ATTR_PORT_DOUBLETAG
,
1265 .get
= esw_get_port_bool
,
1266 .set
= esw_set_port_bool
,
1269 .type
= SWITCH_TYPE_INT
,
1271 .description
= "Untag (1:strip outgoing vlan tag)",
1273 .id
= RT305X_ESW_ATTR_PORT_UNTAG
,
1274 .get
= esw_get_port_bool
,
1275 .set
= esw_set_port_bool
,
1278 .type
= SWITCH_TYPE_INT
,
1280 .description
= "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1281 " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1282 " 8:100mact, 10:blink, 11:off, 12:on)",
1284 .id
= RT305X_ESW_ATTR_PORT_LED
,
1285 .get
= esw_get_port_led
,
1286 .set
= esw_set_port_led
,
1289 .type
= SWITCH_TYPE_INT
,
1291 .description
= "HW port group (0:wan, 1:lan)",
1293 .id
= RT305X_ESW_ATTR_PORT_LAN
,
1294 .get
= esw_get_port_bool
,
1297 .type
= SWITCH_TYPE_INT
,
1299 .description
= "Receive bad packet counter",
1300 .id
= RT305X_ESW_ATTR_PORT_RECV_BAD
,
1301 .get
= esw_get_port_recv_badgood
,
1304 .type
= SWITCH_TYPE_INT
,
1305 .name
= "recv_good",
1306 .description
= "Receive good packet counter",
1307 .id
= RT305X_ESW_ATTR_PORT_RECV_GOOD
,
1308 .get
= esw_get_port_recv_badgood
,
1311 .type
= SWITCH_TYPE_INT
,
1314 .description
= "Transmit bad packet counter. rt5350 only",
1315 .id
= RT5350_ESW_ATTR_PORT_TR_BAD
,
1316 .get
= esw_get_port_tr_badgood
,
1319 .type
= SWITCH_TYPE_INT
,
1322 .description
= "Transmit good packet counter. rt5350 only",
1323 .id
= RT5350_ESW_ATTR_PORT_TR_GOOD
,
1324 .get
= esw_get_port_tr_badgood
,
1328 static const struct switch_attr esw_vlan
[] = {
1331 static const struct switch_dev_ops esw_ops
= {
1334 .n_attr
= ARRAY_SIZE(esw_global
),
1338 .n_attr
= ARRAY_SIZE(esw_port
),
1342 .n_attr
= ARRAY_SIZE(esw_vlan
),
1344 .get_vlan_ports
= esw_get_vlan_ports
,
1345 .set_vlan_ports
= esw_set_vlan_ports
,
1346 .get_port_pvid
= esw_get_port_pvid
,
1347 .set_port_pvid
= esw_set_port_pvid
,
1348 .get_port_link
= esw_get_port_link
,
1349 .apply_config
= esw_apply_config
,
1350 .reset_switch
= esw_reset_switch
,
1353 static struct rt305x_esw_platform_data rt3050_esw_data
= {
1354 /* All ports are LAN ports. */
1355 .vlan_config
= RT305X_ESW_VLAN_CONFIG_NONE
,
1356 .reg_initval_fct2
= 0x00d6500c,
1358 * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1359 * turbo mii off, rgmi 3.3v off
1361 * port6: enabled, gige, full-duplex, rx/tx-flow-control
1363 .reg_initval_fpa2
= 0x3f502b28,
1366 static const struct of_device_id ralink_esw_match
[] = {
1367 { .compatible
= "ralink,rt3050-esw", .data
= &rt3050_esw_data
},
1370 MODULE_DEVICE_TABLE(of
, ralink_esw_match
);
1372 static int esw_probe(struct platform_device
*pdev
)
1374 struct device_node
*np
= pdev
->dev
.of_node
;
1375 const struct rt305x_esw_platform_data
*pdata
;
1376 const __be32
*port_map
, *reg_init
;
1377 struct rt305x_esw
*esw
;
1378 struct switch_dev
*swdev
;
1379 struct resource
*res
, *irq
;
1382 pdata
= pdev
->dev
.platform_data
;
1384 const struct of_device_id
*match
;
1385 match
= of_match_device(ralink_esw_match
, &pdev
->dev
);
1387 pdata
= (struct rt305x_esw_platform_data
*) match
->data
;
1392 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1394 dev_err(&pdev
->dev
, "no memory resource found\n");
1398 irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1400 dev_err(&pdev
->dev
, "no irq resource found\n");
1404 esw
= kzalloc(sizeof(struct rt305x_esw
), GFP_KERNEL
);
1406 dev_err(&pdev
->dev
, "no memory for private data\n");
1410 esw
->dev
= &pdev
->dev
;
1411 esw
->irq
= irq
->start
;
1412 esw
->base
= ioremap(res
->start
, resource_size(res
));
1414 dev_err(&pdev
->dev
, "ioremap failed\n");
1419 port_map
= of_get_property(np
, "ralink,portmap", NULL
);
1421 esw
->port_map
= be32_to_cpu(*port_map
);
1423 reg_init
= of_get_property(np
, "ralink,fct2", NULL
);
1425 esw
->reg_initval_fct2
= be32_to_cpu(*reg_init
);
1427 reg_init
= of_get_property(np
, "ralink,fpa2", NULL
);
1429 esw
->reg_initval_fpa2
= be32_to_cpu(*reg_init
);
1431 reg_init
= of_get_property(np
, "ralink,led_polarity", NULL
);
1433 esw
->reg_led_polarity
= be32_to_cpu(*reg_init
);
1435 swdev
= &esw
->swdev
;
1436 swdev
->of_node
= pdev
->dev
.of_node
;
1437 swdev
->name
= "rt305x-esw";
1438 swdev
->alias
= "rt305x";
1439 swdev
->cpu_port
= RT305X_ESW_PORT6
;
1440 swdev
->ports
= RT305X_ESW_NUM_PORTS
;
1441 swdev
->vlans
= RT305X_ESW_NUM_VIDS
;
1442 swdev
->ops
= &esw_ops
;
1444 err
= register_switch(swdev
, NULL
);
1446 dev_err(&pdev
->dev
, "register_switch failed\n");
1450 platform_set_drvdata(pdev
, esw
);
1453 spin_lock_init(&esw
->reg_rw_lock
);
1457 esw_w32(esw
, RT305X_ESW_PORT_ST_CHG
, RT305X_ESW_REG_ISR
);
1458 esw_w32(esw
, ~RT305X_ESW_PORT_ST_CHG
, RT305X_ESW_REG_IMR
);
1459 request_irq(esw
->irq
, esw_interrupt
, 0, "esw", esw
);
1470 static int esw_remove(struct platform_device
*pdev
)
1472 struct rt305x_esw
*esw
;
1474 esw
= platform_get_drvdata(pdev
);
1476 unregister_switch(&esw
->swdev
);
1477 platform_set_drvdata(pdev
, NULL
);
1485 static struct platform_driver esw_driver
= {
1487 .remove
= esw_remove
,
1489 .name
= "rt305x-esw",
1490 .owner
= THIS_MODULE
,
1491 .of_match_table
= ralink_esw_match
,
1495 int __init
rtesw_init(void)
1497 return platform_driver_register(&esw_driver
);
1500 void rtesw_exit(void)
1502 platform_driver_unregister(&esw_driver
);