1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
15 #include <linux/module.h>
16 #include <linux/mii.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/platform_device.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
23 #include <ralink_regs.h>
25 #include "mtk_eth_soc.h"
26 #include "gsw_mt7620.h"
28 void mtk_switch_w32(struct mt7620_gsw
*gsw
, u32 val
, unsigned reg
)
30 iowrite32(val
, gsw
->base
+ reg
);
33 u32
mtk_switch_r32(struct mt7620_gsw
*gsw
, unsigned reg
)
35 return ioread32(gsw
->base
+ reg
);
38 static irqreturn_t
gsw_interrupt_mt7620(int irq
, void *_priv
)
40 struct fe_priv
*priv
= (struct fe_priv
*)_priv
;
41 struct mt7620_gsw
*gsw
= (struct mt7620_gsw
*)priv
->soc
->swpriv
;
43 int i
, max
= (gsw
->port4_ephy
) ? (4) : (3);
45 status
= mtk_switch_r32(gsw
, GSW_REG_ISR
);
46 if (status
& PORT_IRQ_ST_CHG
)
47 for (i
= 0; i
<= max
; i
++) {
48 u32 status
= mtk_switch_r32(gsw
, GSW_REG_PORT_STATUS(i
));
49 int link
= status
& 0x1;
51 if (link
!= priv
->link
[i
])
52 mt7620_print_link_state(priv
, i
, link
,
58 mt7620_handle_carrier(priv
);
59 mtk_switch_w32(gsw
, status
, GSW_REG_ISR
);
64 static void mt7620_hw_init(struct mt7620_gsw
*gsw
)
68 u32 is_BGA
= (rt_sysc_r32(SYSC_REG_CHIP_REV_ID
) >> 16) & 1;
70 /* Internal ethernet requires PCIe RC mode */
71 rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1
) | PCIE_RC_MODE
, SYSC_REG_CFG1
);
73 mtk_switch_w32(gsw
, mtk_switch_r32(gsw
, GSW_REG_CKGCR
) & ~(0x3 << 4), GSW_REG_CKGCR
);
75 /* Enable MIB stats */
76 mtk_switch_w32(gsw
, mtk_switch_r32(gsw
, GSW_REG_MIB_CNT_EN
) | (1 << 1), GSW_REG_MIB_CNT_EN
);
78 if (gsw
->ephy_disable
) {
79 mtk_switch_w32(gsw
, mtk_switch_r32(gsw
, GSW_REG_GPC1
) |
80 (gsw
->ephy_base
<< 16) | (0x1f << 24),
83 pr_info("gsw: internal ephy disabled\n");
84 } else if (gsw
->ephy_base
) {
85 mtk_switch_w32(gsw
, mtk_switch_r32(gsw
, GSW_REG_GPC1
) |
86 (gsw
->ephy_base
<< 16),
88 fe_reset(MT7620A_RESET_EPHY
);
90 pr_info("gsw: ephy base address: %d\n", gsw
->ephy_base
);
94 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 31, 0x4000);
96 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 17, 0x7444);
98 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 19, 0x0114);
100 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 19, 0x0117);
102 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 22, 0x10cf);
103 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 25, 0x6212);
104 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 26, 0x0777);
105 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 29, 0x4000);
106 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 28, 0xc077);
107 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 24, 0x0000);
110 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 31, 0x3000);
111 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 17, 0x4838);
114 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 31, 0x2000);
116 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 21, 0x0515);
117 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 22, 0x0053);
118 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 23, 0x00bf);
119 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 24, 0x0aaf);
120 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 25, 0x0fad);
121 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 26, 0x0fc1);
123 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 21, 0x0517);
124 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 22, 0x0fd2);
125 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 23, 0x00bf);
126 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 24, 0x0aab);
127 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 25, 0x00ae);
128 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 26, 0x0fff);
131 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 31, 0x1000);
132 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 17, 0xe7f8);
134 /* turn on all PHYs */
135 for (i
= 0; i
<= 4; i
++) {
136 val
= _mt7620_mii_read(gsw
, gsw
->ephy_base
+ i
, MII_BMCR
);
138 val
|= BMCR_ANRESTART
| BMCR_ANENABLE
| BMCR_SPEED100
;
139 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ i
, MII_BMCR
, val
);
143 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 31, 0x8000);
144 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 0, 30, 0xa000);
145 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 30, 0xa000);
146 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 2, 30, 0xa000);
147 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 3, 30, 0xa000);
149 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 0, 4, 0x05e1);
150 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 4, 0x05e1);
151 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 2, 4, 0x05e1);
152 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 3, 4, 0x05e1);
155 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 31, 0xa000);
156 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 0, 16, 0x1111);
157 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 1, 16, 0x1010);
158 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 2, 16, 0x1515);
159 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 3, 16, 0x0f0f);
161 /* CPU Port6 Force Link 1G, FC ON */
162 mtk_switch_w32(gsw
, 0x5e33b, GSW_REG_PORT_PMCR(6));
164 /* Set Port 6 as CPU Port */
165 mtk_switch_w32(gsw
, 0x7f7f7fe0, 0x0010);
168 if (gsw
->port4_ephy
) {
169 val
= rt_sysc_r32(SYSC_REG_CFG1
);
172 rt_sysc_w32(val
, SYSC_REG_CFG1
);
173 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 4, 30, 0xa000);
174 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 4, 4, 0x05e1);
175 _mt7620_mii_write(gsw
, gsw
->ephy_base
+ 4, 16, 0x1313);
176 pr_info("gsw: setting port4 to ephy mode\n");
180 static const struct of_device_id mediatek_gsw_match
[] = {
181 { .compatible
= "mediatek,mt7620-gsw" },
184 MODULE_DEVICE_TABLE(of
, mediatek_gsw_match
);
186 int mtk_gsw_init(struct fe_priv
*priv
)
188 struct device_node
*eth_node
= priv
->dev
->of_node
;
189 struct device_node
*phy_node
, *mdiobus_node
;
190 struct device_node
*np
= priv
->switch_np
;
191 struct platform_device
*pdev
= of_find_device_by_node(np
);
192 struct mt7620_gsw
*gsw
;
199 if (!of_device_is_compatible(np
, mediatek_gsw_match
->compatible
))
202 gsw
= platform_get_drvdata(pdev
);
203 priv
->soc
->swpriv
= gsw
;
205 gsw
->ephy_disable
= of_property_read_bool(np
, "mediatek,ephy-disable");
207 mdiobus_node
= of_get_child_by_name(eth_node
, "mdio-bus");
209 for_each_child_of_node(mdiobus_node
, phy_node
) {
210 id
= of_get_property(phy_node
, "reg", NULL
);
211 if (id
&& (be32_to_cpu(*id
) == 0x1f))
212 gsw
->ephy_disable
= true;
215 of_node_put(mdiobus_node
);
218 gsw
->port4_ephy
= !of_property_read_bool(np
, "mediatek,port4-gmac");
220 if (of_property_read_u8(np
, "mediatek,ephy-base", &val
) == 0)
221 gsw
->ephy_base
= val
;
228 request_irq(gsw
->irq
, gsw_interrupt_mt7620
, 0,
230 mtk_switch_w32(gsw
, ~PORT_IRQ_ST_CHG
, GSW_REG_IMR
);
236 static int mt7620_gsw_probe(struct platform_device
*pdev
)
238 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
239 struct mt7620_gsw
*gsw
;
241 gsw
= devm_kzalloc(&pdev
->dev
, sizeof(struct mt7620_gsw
), GFP_KERNEL
);
245 gsw
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
246 if (IS_ERR(gsw
->base
))
247 return PTR_ERR(gsw
->base
);
249 gsw
->dev
= &pdev
->dev
;
251 gsw
->irq
= platform_get_irq(pdev
, 0);
253 platform_set_drvdata(pdev
, gsw
);
258 static int mt7620_gsw_remove(struct platform_device
*pdev
)
260 platform_set_drvdata(pdev
, NULL
);
265 static struct platform_driver gsw_driver
= {
266 .probe
= mt7620_gsw_probe
,
267 .remove
= mt7620_gsw_remove
,
269 .name
= "mt7620-gsw",
270 .owner
= THIS_MODULE
,
271 .of_match_table
= mediatek_gsw_match
,
275 module_platform_driver(gsw_driver
);
277 MODULE_LICENSE("GPL");
278 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
279 MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC");
280 MODULE_VERSION(MTK_FE_DRV_VERSION
);