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367b8d9ac4569f00972e89f3a48e45b09718293b
[openwrt/staging/chunkeey.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / mt7530.c
1 /*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
13 * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
14 */
15
16 #include <linux/if.h>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/list.h>
20 #include <linux/if_ether.h>
21 #include <linux/skbuff.h>
22 #include <linux/netdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/bitops.h>
25 #include <net/genetlink.h>
26 #include <linux/switch.h>
27 #include <linux/delay.h>
28 #include <linux/phy.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/lockdep.h>
32 #include <linux/workqueue.h>
33 #include <linux/of_device.h>
34 #include <asm/byteorder.h>
35
36 #include "mt7530.h"
37
38 #define MT7530_CPU_PORT 6
39 #define MT7530_NUM_PORTS 8
40 #ifdef CONFIG_SOC_MT7621
41 #define MT7530_NUM_VLANS 4095
42 #else
43 #define MT7530_NUM_VLANS 16
44 #endif
45 #define MT7530_MAX_VID 4095
46 #define MT7530_MIN_VID 0
47 #define MT7530_NUM_ARL_RECORDS 2048
48 #define ARL_LINE_LENGTH 30
49
50 #define MT7530_PORT_MIB_TXB_ID 2 /* TxGOC */
51 #define MT7530_PORT_MIB_RXB_ID 6 /* RxGOC */
52
53 #define MT7621_PORT_MIB_TXB_ID 18 /* TxByte */
54 #define MT7621_PORT_MIB_RXB_ID 37 /* RxByte */
55
56 /* registers */
57 #define REG_ESW_WT_MAC_MFC 0x10
58
59 #define REG_ESW_WT_MAC_MFC_MIRROR_ENABLE BIT(3)
60 #define REG_ESW_WT_MAC_MFC_MIRROR_DEST_MASK 0x07
61
62 #define REG_ESW_VLAN_VTCR 0x90
63 #define REG_ESW_VLAN_VAWD1 0x94
64 #define REG_ESW_VLAN_VAWD2 0x98
65 #define REG_ESW_VLAN_VTIM(x) (0x100 + 4 * ((x) / 2))
66
67 #define REG_ESW_WT_MAC_ATC 0x80
68 #define REG_ESW_TABLE_ATRD 0x8C
69 #define REG_ESW_TABLE_TSRA1 0x84
70 #define REG_ESW_TABLE_TSRA2 0x88
71
72 #define REG_MAC_ATC_START 0x8004
73 #define REG_MAC_ATC_NEXT 0x8005
74
75 #define REG_MAC_ATC_BUSY 0x8000U
76 #define REG_MAC_ATC_SRCH_HIT 0x2000U
77 #define REG_MAC_ATC_SRCH_END 0x4000U
78 #define REG_ATRD_VALID 0xff000000U
79 #define REG_ATRD_PORT_MASK 0xff0U
80
81 #define REG_ESW_VLAN_VAWD1_IVL_MAC BIT(30)
82 #define REG_ESW_VLAN_VAWD1_VTAG_EN BIT(28)
83 #define REG_ESW_VLAN_VAWD1_VALID BIT(0)
84
85 /* vlan egress mode */
86 enum {
87 ETAG_CTRL_UNTAG = 0,
88 ETAG_CTRL_TAG = 2,
89 ETAG_CTRL_SWAP = 1,
90 ETAG_CTRL_STACK = 3,
91 };
92
93 #define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
94 #define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
95 #define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
96
97 #define REG_ESW_PORT_PCR_MIRROR_SRC_RX_BIT BIT(8)
98 #define REG_ESW_PORT_PCR_MIRROR_SRC_TX_BIT BIT(9)
99 #define REG_ESW_PORT_PCR_MIRROR_SRC_RX_MASK 0x0100
100 #define REG_ESW_PORT_PCR_MIRROR_SRC_TX_MASK 0x0200
101
102 #define REG_HWTRAP 0x7804
103
104 #define MIB_DESC(_s , _o, _n) \
105 { \
106 .size = (_s), \
107 .offset = (_o), \
108 .name = (_n), \
109 }
110
111 struct mt7xxx_mib_desc {
112 unsigned int size;
113 unsigned int offset;
114 const char *name;
115 };
116
117 static const struct mt7xxx_mib_desc mt7620_mibs[] = {
118 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT0, "PPE_AC_BCNT0"),
119 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT0, "PPE_AC_PCNT0"),
120 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT63, "PPE_AC_BCNT63"),
121 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT63, "PPE_AC_PCNT63"),
122 MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT0, "PPE_MTR_CNT0"),
123 MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT63, "PPE_MTR_CNT63"),
124 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GBCNT, "GDM1_TX_GBCNT"),
125 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GPCNT, "GDM1_TX_GPCNT"),
126 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_SKIPCNT, "GDM1_TX_SKIPCNT"),
127 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_COLCNT, "GDM1_TX_COLCNT"),
128 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GBCNT1, "GDM1_RX_GBCNT1"),
129 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GPCNT1, "GDM1_RX_GPCNT1"),
130 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_OERCNT, "GDM1_RX_OERCNT"),
131 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FERCNT, "GDM1_RX_FERCNT"),
132 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_SERCNT, "GDM1_RX_SERCNT"),
133 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_LERCNT, "GDM1_RX_LERCNT"),
134 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_CERCNT, "GDM1_RX_CERCNT"),
135 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FCCNT, "GDM1_RX_FCCNT"),
136 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GBCNT, "GDM2_TX_GBCNT"),
137 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GPCNT, "GDM2_TX_GPCNT"),
138 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_SKIPCNT, "GDM2_TX_SKIPCNT"),
139 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_COLCNT, "GDM2_TX_COLCNT"),
140 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GBCNT, "GDM2_RX_GBCNT"),
141 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GPCNT, "GDM2_RX_GPCNT"),
142 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_OERCNT, "GDM2_RX_OERCNT"),
143 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FERCNT, "GDM2_RX_FERCNT"),
144 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_SERCNT, "GDM2_RX_SERCNT"),
145 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_LERCNT, "GDM2_RX_LERCNT"),
146 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_CERCNT, "GDM2_RX_CERCNT"),
147 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FCCNT, "GDM2_RX_FCCNT")
148 };
149
150 static const struct mt7xxx_mib_desc mt7620_port_mibs[] = {
151 MIB_DESC(1, MT7620_MIB_STATS_PORT_TGPCN, "TxGPC"),
152 MIB_DESC(1, MT7620_MIB_STATS_PORT_TBOCN, "TxBOC"),
153 MIB_DESC(1, MT7620_MIB_STATS_PORT_TGOCN, "TxGOC"),
154 MIB_DESC(1, MT7620_MIB_STATS_PORT_TEPCN, "TxEPC"),
155 MIB_DESC(1, MT7620_MIB_STATS_PORT_RGPCN, "RxGPC"),
156 MIB_DESC(1, MT7620_MIB_STATS_PORT_RBOCN, "RxBOC"),
157 MIB_DESC(1, MT7620_MIB_STATS_PORT_RGOCN, "RxGOC"),
158 MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC1N, "RxEPC1"),
159 MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC2N, "RxEPC2")
160 };
161
162 static const struct mt7xxx_mib_desc mt7621_mibs[] = {
163 MIB_DESC(1, MT7621_STATS_TDPC, "TxDrop"),
164 MIB_DESC(1, MT7621_STATS_TCRC, "TxCRC"),
165 MIB_DESC(1, MT7621_STATS_TUPC, "TxUni"),
166 MIB_DESC(1, MT7621_STATS_TMPC, "TxMulti"),
167 MIB_DESC(1, MT7621_STATS_TBPC, "TxBroad"),
168 MIB_DESC(1, MT7621_STATS_TCEC, "TxCollision"),
169 MIB_DESC(1, MT7621_STATS_TSCEC, "TxSingleCol"),
170 MIB_DESC(1, MT7621_STATS_TMCEC, "TxMultiCol"),
171 MIB_DESC(1, MT7621_STATS_TDEC, "TxDefer"),
172 MIB_DESC(1, MT7621_STATS_TLCEC, "TxLateCol"),
173 MIB_DESC(1, MT7621_STATS_TXCEC, "TxExcCol"),
174 MIB_DESC(1, MT7621_STATS_TPPC, "TxPause"),
175 MIB_DESC(1, MT7621_STATS_TL64PC, "Tx64Byte"),
176 MIB_DESC(1, MT7621_STATS_TL65PC, "Tx65Byte"),
177 MIB_DESC(1, MT7621_STATS_TL128PC, "Tx128Byte"),
178 MIB_DESC(1, MT7621_STATS_TL256PC, "Tx256Byte"),
179 MIB_DESC(1, MT7621_STATS_TL512PC, "Tx512Byte"),
180 MIB_DESC(1, MT7621_STATS_TL1024PC, "Tx1024Byte"),
181 MIB_DESC(2, MT7621_STATS_TOC, "TxByte"),
182 MIB_DESC(1, MT7621_STATS_RDPC, "RxDrop"),
183 MIB_DESC(1, MT7621_STATS_RFPC, "RxFiltered"),
184 MIB_DESC(1, MT7621_STATS_RUPC, "RxUni"),
185 MIB_DESC(1, MT7621_STATS_RMPC, "RxMulti"),
186 MIB_DESC(1, MT7621_STATS_RBPC, "RxBroad"),
187 MIB_DESC(1, MT7621_STATS_RAEPC, "RxAlignErr"),
188 MIB_DESC(1, MT7621_STATS_RCEPC, "RxCRC"),
189 MIB_DESC(1, MT7621_STATS_RUSPC, "RxUnderSize"),
190 MIB_DESC(1, MT7621_STATS_RFEPC, "RxFragment"),
191 MIB_DESC(1, MT7621_STATS_ROSPC, "RxOverSize"),
192 MIB_DESC(1, MT7621_STATS_RJEPC, "RxJabber"),
193 MIB_DESC(1, MT7621_STATS_RPPC, "RxPause"),
194 MIB_DESC(1, MT7621_STATS_RL64PC, "Rx64Byte"),
195 MIB_DESC(1, MT7621_STATS_RL65PC, "Rx65Byte"),
196 MIB_DESC(1, MT7621_STATS_RL128PC, "Rx128Byte"),
197 MIB_DESC(1, MT7621_STATS_RL256PC, "Rx256Byte"),
198 MIB_DESC(1, MT7621_STATS_RL512PC, "Rx512Byte"),
199 MIB_DESC(1, MT7621_STATS_RL1024PC, "Rx1024Byte"),
200 MIB_DESC(2, MT7621_STATS_ROC, "RxByte"),
201 MIB_DESC(1, MT7621_STATS_RDPC_CTRL, "RxCtrlDrop"),
202 MIB_DESC(1, MT7621_STATS_RDPC_ING, "RxIngDrop"),
203 MIB_DESC(1, MT7621_STATS_RDPC_ARL, "RxARLDrop")
204 };
205
206 enum {
207 /* Global attributes. */
208 MT7530_ATTR_ENABLE_VLAN,
209 };
210
211 struct mt7530_port_entry {
212 u16 pvid;
213 bool mirror_rx;
214 bool mirror_tx;
215 };
216
217 struct mt7530_vlan_entry {
218 u16 vid;
219 u8 member;
220 u8 etags;
221 };
222
223 struct mt7530_priv {
224 void __iomem *base;
225 struct mii_bus *bus;
226 struct switch_dev swdev;
227
228 u8 mirror_dest_port;
229 bool global_vlan_enable;
230 struct mt7530_vlan_entry vlan_entries[MT7530_NUM_VLANS];
231 struct mt7530_port_entry port_entries[MT7530_NUM_PORTS];
232 char arl_buf[MT7530_NUM_ARL_RECORDS * ARL_LINE_LENGTH + 1];
233 };
234
235 struct mt7530_mapping {
236 char *name;
237 u16 pvids[MT7530_NUM_PORTS];
238 u8 members[MT7530_NUM_VLANS];
239 u8 etags[MT7530_NUM_VLANS];
240 u16 vids[MT7530_NUM_VLANS];
241 } mt7530_defaults[] = {
242 {
243 .name = "llllw",
244 .pvids = { 1, 1, 1, 1, 2, 1, 1 },
245 .members = { 0, 0x6f, 0x50 },
246 .etags = { 0, 0x40, 0x40 },
247 .vids = { 0, 1, 2 },
248 }, {
249 .name = "wllll",
250 .pvids = { 2, 1, 1, 1, 1, 1, 1 },
251 .members = { 0, 0x7e, 0x41 },
252 .etags = { 0, 0x40, 0x40 },
253 .vids = { 0, 1, 2 },
254 }, {
255 .name = "lwlll",
256 .pvids = { 1, 2, 1, 1, 1, 1, 1 },
257 .members = { 0, 0x7d, 0x42 },
258 .etags = { 0, 0x40, 0x40 },
259 .vids = { 0, 1, 2 },
260 },
261 };
262
263 struct mt7530_mapping*
264 mt7530_find_mapping(struct device_node *np)
265 {
266 const char *map;
267 int i;
268
269 if (of_property_read_string(np, "mediatek,portmap", &map))
270 return NULL;
271
272 for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
273 if (!strcmp(map, mt7530_defaults[i].name))
274 return &mt7530_defaults[i];
275
276 return NULL;
277 }
278
279 static void
280 mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
281 {
282 int i = 0;
283
284 for (i = 0; i < MT7530_NUM_PORTS; i++)
285 mt7530->port_entries[i].pvid = map->pvids[i];
286
287 for (i = 0; i < MT7530_NUM_VLANS; i++) {
288 mt7530->vlan_entries[i].member = map->members[i];
289 mt7530->vlan_entries[i].etags = map->etags[i];
290 mt7530->vlan_entries[i].vid = map->vids[i];
291 }
292 }
293
294 static int
295 mt7530_reset_switch(struct switch_dev *dev)
296 {
297 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
298 int i;
299
300 memset(priv->port_entries, 0, sizeof(priv->port_entries));
301 memset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));
302
303 /* set default vid of each vlan to the same number of vlan, so the vid
304 * won't need be set explicitly.
305 */
306 for (i = 0; i < MT7530_NUM_VLANS; i++) {
307 priv->vlan_entries[i].vid = i;
308 }
309
310 return 0;
311 }
312
313 static int
314 mt7530_get_vlan_enable(struct switch_dev *dev,
315 const struct switch_attr *attr,
316 struct switch_val *val)
317 {
318 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
319
320 val->value.i = priv->global_vlan_enable;
321
322 return 0;
323 }
324
325 static int
326 mt7530_set_vlan_enable(struct switch_dev *dev,
327 const struct switch_attr *attr,
328 struct switch_val *val)
329 {
330 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
331
332 priv->global_vlan_enable = val->value.i != 0;
333
334 return 0;
335 }
336
337 static u32
338 mt7530_r32(struct mt7530_priv *priv, u32 reg)
339 {
340 u32 val;
341 if (priv->bus) {
342 u16 high, low;
343
344 mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
345 low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
346 high = mdiobus_read(priv->bus, 0x1f, 0x10);
347
348 return (high << 16) | (low & 0xffff);
349 }
350
351 val = ioread32(priv->base + reg);
352 pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
353
354 return val;
355 }
356
357 static void
358 mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
359 {
360 if (priv->bus) {
361 mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
362 mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
363 mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
364 return;
365 }
366
367 pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
368 iowrite32(val, priv->base + reg);
369 }
370
371 static void
372 mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
373 {
374 int i;
375
376 mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
377
378 for (i = 0; i < 20; i++) {
379 u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
380
381 if ((val & BIT(31)) == 0)
382 break;
383
384 udelay(1000);
385 }
386 if (i == 20)
387 printk("mt7530: vtcr timeout\n");
388 }
389
390 static int
391 mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
392 {
393 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
394
395 if (port >= MT7530_NUM_PORTS)
396 return -EINVAL;
397
398 *val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));
399 *val &= 0xfff;
400
401 return 0;
402 }
403
404 static int
405 mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
406 {
407 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
408
409 if (port >= MT7530_NUM_PORTS)
410 return -EINVAL;
411
412 if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
413 return -EINVAL;
414
415 priv->port_entries[port].pvid = pvid;
416
417 return 0;
418 }
419
420 static int
421 mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
422 {
423 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
424 u32 member;
425 u32 etags;
426 int i;
427
428 val->len = 0;
429
430 if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
431 return -EINVAL;
432
433 mt7530_vtcr(priv, 0, val->port_vlan);
434
435 member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
436 member >>= 16;
437 member &= 0xff;
438
439 etags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);
440
441 for (i = 0; i < MT7530_NUM_PORTS; i++) {
442 struct switch_port *p;
443 int etag;
444
445 if (!(member & BIT(i)))
446 continue;
447
448 p = &val->value.ports[val->len++];
449 p->id = i;
450
451 etag = (etags >> (i * 2)) & 0x3;
452
453 if (etag == ETAG_CTRL_TAG)
454 p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
455 else if (etag != ETAG_CTRL_UNTAG)
456 printk("vlan %d port %d egress tag control neither untag nor tag: %d.\n",
457 val->port_vlan, i, etag);
458 }
459
460 return 0;
461 }
462
463 static int
464 mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
465 {
466 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
467 u8 member = 0;
468 u8 etags = 0;
469 int i;
470
471 if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
472 val->len > MT7530_NUM_PORTS)
473 return -EINVAL;
474
475 for (i = 0; i < val->len; i++) {
476 struct switch_port *p = &val->value.ports[i];
477
478 if (p->id >= MT7530_NUM_PORTS)
479 return -EINVAL;
480
481 member |= BIT(p->id);
482
483 if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
484 etags |= BIT(p->id);
485 }
486 priv->vlan_entries[val->port_vlan].member = member;
487 priv->vlan_entries[val->port_vlan].etags = etags;
488
489 return 0;
490 }
491
492 static int
493 mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
494 struct switch_val *val)
495 {
496 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
497 int vlan;
498 u16 vid;
499
500 vlan = val->port_vlan;
501 vid = (u16)val->value.i;
502
503 if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
504 return -EINVAL;
505
506 if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
507 return -EINVAL;
508
509 priv->vlan_entries[vlan].vid = vid;
510 return 0;
511 }
512
513 static int
514 mt7621_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
515 struct switch_val *val)
516 {
517 val->value.i = val->port_vlan;
518 return 0;
519 }
520
521 static int
522 mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
523 struct switch_val *val)
524 {
525 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
526 u32 vid;
527 int vlan;
528
529 vlan = val->port_vlan;
530
531 vid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
532 if (vlan & 1)
533 vid = vid >> 12;
534 vid &= 0xfff;
535
536 val->value.i = vid;
537 return 0;
538 }
539
540 static int
541 mt7530_get_mirror_monitor_port(struct switch_dev *dev, const struct switch_attr *attr,
542 struct switch_val *val)
543 {
544 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
545
546 val->value.i = priv->mirror_dest_port;
547
548 return 0;
549 }
550
551 static int
552 mt7530_set_mirror_monitor_port(struct switch_dev *dev, const struct switch_attr *attr,
553 struct switch_val *val)
554 {
555 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
556
557 priv->mirror_dest_port = val->value.i;
558
559 return 0;
560 }
561
562 static int
563 mt7530_get_port_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,
564 struct switch_val *val)
565 {
566 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
567
568 val->value.i = priv->port_entries[val->port_vlan].mirror_rx;
569
570 return 0;
571 }
572
573 static int
574 mt7530_set_port_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,
575 struct switch_val *val)
576 {
577 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
578
579 priv->port_entries[val->port_vlan].mirror_rx = val->value.i;
580
581 return 0;
582 }
583
584 static int
585 mt7530_get_port_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,
586 struct switch_val *val)
587 {
588 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
589
590 val->value.i = priv->port_entries[val->port_vlan].mirror_tx;
591
592 return 0;
593 }
594
595 static int
596 mt7530_set_port_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,
597 struct switch_val *val)
598 {
599 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
600
601 priv->port_entries[val->port_vlan].mirror_tx = val->value.i;
602
603 return 0;
604 }
605
606 static void
607 mt7530_write_vlan_entry(struct mt7530_priv *priv, int vlan, u16 vid,
608 u8 ports, u8 etags)
609 {
610 int port;
611 u32 val;
612
613 #ifndef CONFIG_SOC_MT7621
614 /* vid of vlan */
615 val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
616 if (vlan % 2 == 0) {
617 val &= 0xfff000;
618 val |= vid;
619 } else {
620 val &= 0xfff;
621 val |= (vid << 12);
622 }
623 mt7530_w32(priv, REG_ESW_VLAN_VTIM(vlan), val);
624 #endif
625
626 /* vlan port membership */
627 if (ports)
628 mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
629 REG_ESW_VLAN_VAWD1_VTAG_EN | (ports << 16) |
630 REG_ESW_VLAN_VAWD1_VALID);
631 else
632 mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
633
634 /* egress mode */
635 val = 0;
636 for (port = 0; port < MT7530_NUM_PORTS; port++) {
637 if (etags & BIT(port))
638 val |= ETAG_CTRL_TAG << (port * 2);
639 else
640 val |= ETAG_CTRL_UNTAG << (port * 2);
641 }
642 mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
643
644 /* write to vlan table */
645 #ifdef CONFIG_SOC_MT7621
646 mt7530_vtcr(priv, 1, vid);
647 #else
648 mt7530_vtcr(priv, 1, vlan);
649 #endif
650 }
651
652 static int
653 mt7530_apply_config(struct switch_dev *dev)
654 {
655 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
656 int i, j;
657 u8 tag_ports;
658 u8 untag_ports;
659 bool is_mirror = false;
660
661 if (!priv->global_vlan_enable) {
662 for (i = 0; i < MT7530_NUM_PORTS; i++)
663 mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00400000);
664
665 mt7530_w32(priv, REG_ESW_PORT_PCR(MT7530_CPU_PORT), 0x00ff0000);
666
667 for (i = 0; i < MT7530_NUM_PORTS; i++)
668 mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x810000c0);
669
670 return 0;
671 }
672
673 /* set all ports as security mode */
674 for (i = 0; i < MT7530_NUM_PORTS; i++)
675 mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);
676
677 /* check if a port is used in tag/untag vlan egress mode */
678 tag_ports = 0;
679 untag_ports = 0;
680
681 for (i = 0; i < MT7530_NUM_VLANS; i++) {
682 u8 member = priv->vlan_entries[i].member;
683 u8 etags = priv->vlan_entries[i].etags;
684
685 if (!member)
686 continue;
687
688 for (j = 0; j < MT7530_NUM_PORTS; j++) {
689 if (!(member & BIT(j)))
690 continue;
691
692 if (etags & BIT(j))
693 tag_ports |= 1u << j;
694 else
695 untag_ports |= 1u << j;
696 }
697 }
698
699 /* set all untag-only ports as transparent and the rest as user port */
700 for (i = 0; i < MT7530_NUM_PORTS; i++) {
701 u32 pvc_mode = 0x81000000;
702
703 if (untag_ports & BIT(i) && !(tag_ports & BIT(i)))
704 pvc_mode = 0x810000c0;
705
706 mt7530_w32(priv, REG_ESW_PORT_PVC(i), pvc_mode);
707 }
708
709 /* first clear the swtich vlan table */
710 for (i = 0; i < MT7530_NUM_VLANS; i++)
711 mt7530_write_vlan_entry(priv, i, i, 0, 0);
712
713 /* now program only vlans with members to avoid
714 clobbering remapped entries in later iterations */
715 for (i = 0; i < MT7530_NUM_VLANS; i++) {
716 u16 vid = priv->vlan_entries[i].vid;
717 u8 member = priv->vlan_entries[i].member;
718 u8 etags = priv->vlan_entries[i].etags;
719
720 if (member)
721 mt7530_write_vlan_entry(priv, i, vid, member, etags);
722 }
723
724 /* Port Default PVID */
725 for (i = 0; i < MT7530_NUM_PORTS; i++) {
726 int vlan = priv->port_entries[i].pvid;
727 u16 pvid = 0;
728 u32 val;
729
730 if (vlan < MT7530_NUM_VLANS && priv->vlan_entries[vlan].member)
731 pvid = priv->vlan_entries[vlan].vid;
732
733 val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));
734 val &= ~0xfff;
735 val |= pvid;
736 mt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);
737 }
738
739 /* set mirroring source port */
740 for (i = 0; i < MT7530_NUM_PORTS; i++) {
741 u32 val = mt7530_r32(priv, REG_ESW_PORT_PCR(i));
742 if (priv->port_entries[i].mirror_rx) {
743 val |= REG_ESW_PORT_PCR_MIRROR_SRC_RX_BIT;
744 is_mirror = true;
745 }
746
747 if (priv->port_entries[i].mirror_tx) {
748 val |= REG_ESW_PORT_PCR_MIRROR_SRC_TX_BIT;
749 is_mirror = true;
750 }
751
752 mt7530_w32(priv, REG_ESW_PORT_PCR(i), val);
753 }
754
755 /* set mirroring monitor port */
756 if (is_mirror) {
757 u32 val = mt7530_r32(priv, REG_ESW_WT_MAC_MFC);
758 val |= REG_ESW_WT_MAC_MFC_MIRROR_ENABLE;
759 val &= ~REG_ESW_WT_MAC_MFC_MIRROR_DEST_MASK;
760 val |= priv->mirror_dest_port;
761 mt7530_w32(priv, REG_ESW_WT_MAC_MFC, val);
762 }
763
764 return 0;
765 }
766
767 static int
768 mt7530_get_port_link(struct switch_dev *dev, int port,
769 struct switch_port_link *link)
770 {
771 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
772 u32 speed, pmsr;
773
774 if (port < 0 || port >= MT7530_NUM_PORTS)
775 return -EINVAL;
776
777 pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
778
779 link->link = pmsr & 1;
780 link->duplex = (pmsr >> 1) & 1;
781 speed = (pmsr >> 2) & 3;
782
783 switch (speed) {
784 case 0:
785 link->speed = SWITCH_PORT_SPEED_10;
786 break;
787 case 1:
788 link->speed = SWITCH_PORT_SPEED_100;
789 break;
790 case 2:
791 case 3: /* forced gige speed can be 2 or 3 */
792 link->speed = SWITCH_PORT_SPEED_1000;
793 break;
794 default:
795 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
796 break;
797 }
798
799 return 0;
800 }
801
802 static u64 get_mib_counter(struct mt7530_priv *priv, int i, int port)
803 {
804 unsigned int port_base;
805 u64 lo;
806
807 port_base = MT7621_MIB_COUNTER_BASE +
808 MT7621_MIB_COUNTER_PORT_OFFSET * port;
809
810 lo = mt7530_r32(priv, port_base + mt7621_mibs[i].offset);
811 if (mt7621_mibs[i].size == 2) {
812 u64 hi;
813
814 hi = mt7530_r32(priv, port_base + mt7621_mibs[i].offset + 4);
815 lo |= hi << 32;
816 }
817
818 return lo;
819 }
820
821 static int mt7621_sw_get_port_mib(struct switch_dev *dev,
822 const struct switch_attr *attr,
823 struct switch_val *val)
824 {
825 static char buf[4096];
826 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
827 int i, len = 0;
828
829 if (val->port_vlan >= MT7530_NUM_PORTS)
830 return -EINVAL;
831
832 len += snprintf(buf + len, sizeof(buf) - len,
833 "Port %d MIB counters\n", val->port_vlan);
834
835 for (i = 0; i < ARRAY_SIZE(mt7621_mibs); ++i) {
836 u64 counter;
837 len += snprintf(buf + len, sizeof(buf) - len,
838 "%-11s: ", mt7621_mibs[i].name);
839 counter = get_mib_counter(priv, i, val->port_vlan);
840 len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
841 counter);
842 }
843
844 val->value.s = buf;
845 val->len = len;
846 return 0;
847 }
848
849 static u64 get_mib_counter_7620(struct mt7530_priv *priv, int i)
850 {
851 return mt7530_r32(priv, MT7620_MIB_COUNTER_BASE + mt7620_mibs[i].offset);
852 }
853
854 static u64 get_mib_counter_port_7620(struct mt7530_priv *priv, int i, int port)
855 {
856 return mt7530_r32(priv,
857 MT7620_MIB_COUNTER_BASE_PORT +
858 (MT7620_MIB_COUNTER_PORT_OFFSET * port) +
859 mt7620_port_mibs[i].offset);
860 }
861
862 static int mt7530_sw_get_mib(struct switch_dev *dev,
863 const struct switch_attr *attr,
864 struct switch_val *val)
865 {
866 static char buf[4096];
867 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
868 int i, len = 0;
869
870 len += snprintf(buf + len, sizeof(buf) - len, "Switch MIB counters\n");
871
872 for (i = 0; i < ARRAY_SIZE(mt7620_mibs); ++i) {
873 u64 counter;
874 len += snprintf(buf + len, sizeof(buf) - len,
875 "%-11s: ", mt7620_mibs[i].name);
876 counter = get_mib_counter_7620(priv, i);
877 len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
878 counter);
879 }
880
881 val->value.s = buf;
882 val->len = len;
883 return 0;
884 }
885
886 static char *mt7530_print_arl_table_row(u32 atrd,
887 u32 mac1,
888 u32 mac2,
889 char *buf,
890 size_t *size)
891 {
892 int ret;
893 size_t port;
894 size_t i;
895 u8 port_map;
896 u8 mac[ETH_ALEN];
897
898 mac1 = ntohl(mac1);
899 mac2 = ntohl(mac2);
900 port_map = (u8)((atrd & REG_ATRD_PORT_MASK) >> 4);
901 memcpy(mac, &mac1, sizeof(mac1));
902 memcpy(mac + sizeof(mac1), &mac2, sizeof(mac) - sizeof(mac1));
903 for (port = 0, i = 1; port < MT7530_NUM_PORTS; ++port, i <<= 1) {
904 if (port_map & i) {
905 ret = snprintf(buf, *size, "Port %d: MAC %pM\n", port, mac);
906 if (ret >= *size || ret <= 0) {
907 *buf = 0;
908 buf = NULL;
909 goto out;
910 }
911 buf += ret;
912 *size = *size - ret;
913 }
914 }
915 out:
916 return buf;
917 }
918
919 static int mt7530_get_arl_table(struct switch_dev *dev,
920 const struct switch_attr *attr,
921 struct switch_val *val)
922 {
923 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
924 char *buf = priv->arl_buf;
925 size_t size = sizeof(priv->arl_buf);
926 size_t count = 0;
927 size_t retry_times = 100;
928 int ret;
929 u32 atc;
930
931 ret = snprintf(buf, size, "address resolution table\n");
932 if (ret >= size || ret <= 0) {
933 priv->arl_buf[0] = 0;
934 goto out;
935 }
936 buf += ret;
937 size = size - ret;
938
939 mt7530_w32(priv, REG_ESW_WT_MAC_ATC, REG_MAC_ATC_START);
940
941 do {
942 atc = mt7530_r32(priv, REG_ESW_WT_MAC_ATC);
943 if (atc & REG_MAC_ATC_SRCH_HIT && !(atc & REG_MAC_ATC_BUSY)) {
944 u32 atrd;
945
946 ++count;
947 atrd = mt7530_r32(priv, REG_ESW_TABLE_ATRD);
948 if (atrd & REG_ATRD_VALID) {
949 u32 mac1;
950 u32 mac2;
951
952 mac1 = mt7530_r32(priv, REG_ESW_TABLE_TSRA1);
953 mac2 = mt7530_r32(priv, REG_ESW_TABLE_TSRA2);
954
955 if (!(atc & REG_MAC_ATC_SRCH_END))
956 mt7530_w32(priv, REG_ESW_WT_MAC_ATC, REG_MAC_ATC_NEXT);
957
958 buf = mt7530_print_arl_table_row(atrd, mac1, mac2, buf, &size);
959 if (!buf) {
960 pr_warn("%s: too many addresses\n", __func__);
961 goto out;
962 }
963 } else if (!(atc & REG_MAC_ATC_SRCH_END)) {
964 mt7530_w32(priv, REG_ESW_WT_MAC_ATC, REG_MAC_ATC_NEXT);
965 }
966 } else {
967 --retry_times;
968 usleep_range(1000, 5000);
969 }
970 } while (!(atc & REG_MAC_ATC_SRCH_END) &&
971 count < MT7530_NUM_ARL_RECORDS &&
972 retry_times > 0);
973 out:
974 val->value.s = priv->arl_buf;
975 val->len = strlen(priv->arl_buf);
976
977 return 0;
978 }
979
980 static int mt7530_sw_get_port_mib(struct switch_dev *dev,
981 const struct switch_attr *attr,
982 struct switch_val *val)
983 {
984 static char buf[4096];
985 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
986 int i, len = 0;
987
988 if (val->port_vlan >= MT7530_NUM_PORTS)
989 return -EINVAL;
990
991 len += snprintf(buf + len, sizeof(buf) - len,
992 "Port %d MIB counters\n", val->port_vlan);
993
994 for (i = 0; i < ARRAY_SIZE(mt7620_port_mibs); ++i) {
995 u64 counter;
996 len += snprintf(buf + len, sizeof(buf) - len,
997 "%-11s: ", mt7620_port_mibs[i].name);
998 counter = get_mib_counter_port_7620(priv, i, val->port_vlan);
999 len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
1000 counter);
1001 }
1002
1003 val->value.s = buf;
1004 val->len = len;
1005 return 0;
1006 }
1007
1008 static int mt7530_get_port_stats(struct switch_dev *dev, int port,
1009 struct switch_port_stats *stats)
1010 {
1011 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
1012
1013 if (port < 0 || port >= MT7530_NUM_PORTS)
1014 return -EINVAL;
1015
1016 stats->tx_bytes = get_mib_counter_port_7620(priv, MT7530_PORT_MIB_TXB_ID, port);
1017 stats->rx_bytes = get_mib_counter_port_7620(priv, MT7530_PORT_MIB_RXB_ID, port);
1018
1019 return 0;
1020 }
1021
1022 static int mt7621_get_port_stats(struct switch_dev *dev, int port,
1023 struct switch_port_stats *stats)
1024 {
1025 struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
1026
1027 if (port < 0 || port >= MT7530_NUM_PORTS)
1028 return -EINVAL;
1029
1030 stats->tx_bytes = get_mib_counter(priv, MT7621_PORT_MIB_TXB_ID, port);
1031 stats->rx_bytes = get_mib_counter(priv, MT7621_PORT_MIB_RXB_ID, port);
1032
1033 return 0;
1034 }
1035
1036 static const struct switch_attr mt7530_global[] = {
1037 {
1038 .type = SWITCH_TYPE_INT,
1039 .name = "enable_vlan",
1040 .description = "VLAN mode (1:enabled)",
1041 .max = 1,
1042 .id = MT7530_ATTR_ENABLE_VLAN,
1043 .get = mt7530_get_vlan_enable,
1044 .set = mt7530_set_vlan_enable,
1045 }, {
1046 .type = SWITCH_TYPE_STRING,
1047 .name = "mib",
1048 .description = "Get MIB counters for switch",
1049 .get = mt7530_sw_get_mib,
1050 .set = NULL,
1051 }, {
1052 .type = SWITCH_TYPE_INT,
1053 .name = "mirror_monitor_port",
1054 .description = "Mirror monitor port",
1055 .set = mt7530_set_mirror_monitor_port,
1056 .get = mt7530_get_mirror_monitor_port,
1057 .max = MT7530_NUM_PORTS - 1
1058 },
1059 {
1060 .type = SWITCH_TYPE_STRING,
1061 .name = "arl_table",
1062 .description = "Get ARL table",
1063 .set = NULL,
1064 .get = mt7530_get_arl_table,
1065 },
1066 };
1067
1068 static const struct switch_attr mt7621_port[] = {
1069 {
1070 .type = SWITCH_TYPE_STRING,
1071 .name = "mib",
1072 .description = "Get MIB counters for port",
1073 .get = mt7621_sw_get_port_mib,
1074 .set = NULL,
1075 }, {
1076 .type = SWITCH_TYPE_INT,
1077 .name = "enable_mirror_rx",
1078 .description = "Enable mirroring of RX packets",
1079 .set = mt7530_set_port_mirror_rx,
1080 .get = mt7530_get_port_mirror_rx,
1081 .max = 1,
1082 }, {
1083 .type = SWITCH_TYPE_INT,
1084 .name = "enable_mirror_tx",
1085 .description = "Enable mirroring of TX packets",
1086 .set = mt7530_set_port_mirror_tx,
1087 .get = mt7530_get_port_mirror_tx,
1088 .max = 1,
1089 },
1090 };
1091
1092 static const struct switch_attr mt7621_vlan[] = {
1093 {
1094 .type = SWITCH_TYPE_INT,
1095 .name = "vid",
1096 .description = "VLAN ID (0-4094)",
1097 .set = mt7530_set_vid,
1098 .get = mt7621_get_vid,
1099 .max = 4094,
1100 },
1101 };
1102
1103 static const struct switch_attr mt7530_port[] = {
1104 {
1105 .type = SWITCH_TYPE_STRING,
1106 .name = "mib",
1107 .description = "Get MIB counters for port",
1108 .get = mt7530_sw_get_port_mib,
1109 .set = NULL,
1110 }, {
1111 .type = SWITCH_TYPE_INT,
1112 .name = "enable_mirror_rx",
1113 .description = "Enable mirroring of RX packets",
1114 .set = mt7530_set_port_mirror_rx,
1115 .get = mt7530_get_port_mirror_rx,
1116 .max = 1,
1117 }, {
1118 .type = SWITCH_TYPE_INT,
1119 .name = "enable_mirror_tx",
1120 .description = "Enable mirroring of TX packets",
1121 .set = mt7530_set_port_mirror_tx,
1122 .get = mt7530_get_port_mirror_tx,
1123 .max = 1,
1124 },
1125 };
1126
1127 static const struct switch_attr mt7530_vlan[] = {
1128 {
1129 .type = SWITCH_TYPE_INT,
1130 .name = "vid",
1131 .description = "VLAN ID (0-4094)",
1132 .set = mt7530_set_vid,
1133 .get = mt7530_get_vid,
1134 .max = 4094,
1135 },
1136 };
1137
1138 static const struct switch_dev_ops mt7621_ops = {
1139 .attr_global = {
1140 .attr = mt7530_global,
1141 .n_attr = ARRAY_SIZE(mt7530_global),
1142 },
1143 .attr_port = {
1144 .attr = mt7621_port,
1145 .n_attr = ARRAY_SIZE(mt7621_port),
1146 },
1147 .attr_vlan = {
1148 .attr = mt7621_vlan,
1149 .n_attr = ARRAY_SIZE(mt7621_vlan),
1150 },
1151 .get_vlan_ports = mt7530_get_vlan_ports,
1152 .set_vlan_ports = mt7530_set_vlan_ports,
1153 .get_port_pvid = mt7530_get_port_pvid,
1154 .set_port_pvid = mt7530_set_port_pvid,
1155 .get_port_link = mt7530_get_port_link,
1156 .get_port_stats = mt7621_get_port_stats,
1157 .apply_config = mt7530_apply_config,
1158 .reset_switch = mt7530_reset_switch,
1159 };
1160
1161 static const struct switch_dev_ops mt7530_ops = {
1162 .attr_global = {
1163 .attr = mt7530_global,
1164 .n_attr = ARRAY_SIZE(mt7530_global),
1165 },
1166 .attr_port = {
1167 .attr = mt7530_port,
1168 .n_attr = ARRAY_SIZE(mt7530_port),
1169 },
1170 .attr_vlan = {
1171 .attr = mt7530_vlan,
1172 .n_attr = ARRAY_SIZE(mt7530_vlan),
1173 },
1174 .get_vlan_ports = mt7530_get_vlan_ports,
1175 .set_vlan_ports = mt7530_set_vlan_ports,
1176 .get_port_pvid = mt7530_get_port_pvid,
1177 .set_port_pvid = mt7530_set_port_pvid,
1178 .get_port_link = mt7530_get_port_link,
1179 .get_port_stats = mt7530_get_port_stats,
1180 .apply_config = mt7530_apply_config,
1181 .reset_switch = mt7530_reset_switch,
1182 };
1183
1184 int
1185 mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan)
1186 {
1187 struct switch_dev *swdev;
1188 struct mt7530_priv *mt7530;
1189 struct mt7530_mapping *map;
1190 int ret;
1191
1192 mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
1193 if (!mt7530)
1194 return -ENOMEM;
1195
1196 mt7530->base = base;
1197 mt7530->bus = bus;
1198 mt7530->global_vlan_enable = vlan;
1199
1200 swdev = &mt7530->swdev;
1201 if (bus) {
1202 swdev->alias = "mt7530";
1203 swdev->name = "mt7530";
1204 } else if (IS_ENABLED(CONFIG_SOC_MT7621)) {
1205 swdev->alias = "mt7621";
1206 swdev->name = "mt7621";
1207 } else {
1208 swdev->alias = "mt7620";
1209 swdev->name = "mt7620";
1210 }
1211 swdev->cpu_port = MT7530_CPU_PORT;
1212 swdev->ports = MT7530_NUM_PORTS;
1213 swdev->vlans = MT7530_NUM_VLANS;
1214 if (IS_ENABLED(CONFIG_SOC_MT7621))
1215 swdev->ops = &mt7621_ops;
1216 else
1217 swdev->ops = &mt7530_ops;
1218
1219 ret = register_switch(swdev, NULL);
1220 if (ret) {
1221 dev_err(dev, "failed to register mt7530\n");
1222 return ret;
1223 }
1224
1225
1226 map = mt7530_find_mapping(dev->of_node);
1227 if (map)
1228 mt7530_apply_mapping(mt7530, map);
1229 mt7530_apply_config(swdev);
1230
1231 /* magic vodoo */
1232 if (!IS_ENABLED(CONFIG_SOC_MT7621) && bus && mt7530_r32(mt7530, REG_HWTRAP) != 0x1117edf) {
1233 dev_info(dev, "fixing up MHWTRAP register - bootloader probably played with it\n");
1234 mt7530_w32(mt7530, REG_HWTRAP, 0x1117edf);
1235 }
1236 dev_info(dev, "loaded %s driver\n", swdev->name);
1237
1238 return 0;
1239 }
Staging tree of Christian Lamparter