2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
13 * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/list.h>
20 #include <linux/if_ether.h>
21 #include <linux/skbuff.h>
22 #include <linux/netdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/bitops.h>
25 #include <net/genetlink.h>
26 #include <linux/switch.h>
27 #include <linux/delay.h>
28 #include <linux/phy.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/lockdep.h>
32 #include <linux/workqueue.h>
33 #include <linux/of_device.h>
34 #include <asm/byteorder.h>
38 #define MT7530_CPU_PORT 6
39 #define MT7530_NUM_PORTS 8
40 #ifdef CONFIG_SOC_MT7621
41 #define MT7530_NUM_VLANS 4095
43 #define MT7530_NUM_VLANS 16
45 #define MT7530_MAX_VID 4095
46 #define MT7530_MIN_VID 0
47 #define MT7530_NUM_ARL_RECORDS 2048
48 #define ARL_LINE_LENGTH 30
50 #define MT7530_PORT_MIB_TXB_ID 2 /* TxGOC */
51 #define MT7530_PORT_MIB_RXB_ID 6 /* RxGOC */
53 #define MT7621_PORT_MIB_TXB_ID 18 /* TxByte */
54 #define MT7621_PORT_MIB_RXB_ID 37 /* RxByte */
57 #define REG_ESW_WT_MAC_MFC 0x10
59 #define REG_ESW_WT_MAC_MFC_MIRROR_ENABLE BIT(3)
60 #define REG_ESW_WT_MAC_MFC_MIRROR_DEST_MASK 0x07
62 #define REG_ESW_VLAN_VTCR 0x90
63 #define REG_ESW_VLAN_VAWD1 0x94
64 #define REG_ESW_VLAN_VAWD2 0x98
65 #define REG_ESW_VLAN_VTIM(x) (0x100 + 4 * ((x) / 2))
67 #define REG_ESW_WT_MAC_ATC 0x80
68 #define REG_ESW_TABLE_ATRD 0x8C
69 #define REG_ESW_TABLE_TSRA1 0x84
70 #define REG_ESW_TABLE_TSRA2 0x88
72 #define REG_MAC_ATC_START 0x8004
73 #define REG_MAC_ATC_NEXT 0x8005
75 #define REG_MAC_ATC_BUSY 0x8000U
76 #define REG_MAC_ATC_SRCH_HIT 0x2000U
77 #define REG_MAC_ATC_SRCH_END 0x4000U
78 #define REG_ATRD_VALID 0xff000000U
79 #define REG_ATRD_PORT_MASK 0xff0U
81 #define REG_ESW_VLAN_VAWD1_IVL_MAC BIT(30)
82 #define REG_ESW_VLAN_VAWD1_VTAG_EN BIT(28)
83 #define REG_ESW_VLAN_VAWD1_VALID BIT(0)
85 /* vlan egress mode */
93 #define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
94 #define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
95 #define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
97 #define REG_ESW_PORT_PCR_MIRROR_SRC_RX_BIT BIT(8)
98 #define REG_ESW_PORT_PCR_MIRROR_SRC_TX_BIT BIT(9)
99 #define REG_ESW_PORT_PCR_MIRROR_SRC_RX_MASK 0x0100
100 #define REG_ESW_PORT_PCR_MIRROR_SRC_TX_MASK 0x0200
102 #define REG_HWTRAP 0x7804
104 #define MIB_DESC(_s , _o, _n) \
111 struct mt7xxx_mib_desc
{
117 static const struct mt7xxx_mib_desc mt7620_mibs
[] = {
118 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT0
, "PPE_AC_BCNT0"),
119 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT0
, "PPE_AC_PCNT0"),
120 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT63
, "PPE_AC_BCNT63"),
121 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT63
, "PPE_AC_PCNT63"),
122 MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT0
, "PPE_MTR_CNT0"),
123 MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT63
, "PPE_MTR_CNT63"),
124 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GBCNT
, "GDM1_TX_GBCNT"),
125 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GPCNT
, "GDM1_TX_GPCNT"),
126 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_SKIPCNT
, "GDM1_TX_SKIPCNT"),
127 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_COLCNT
, "GDM1_TX_COLCNT"),
128 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GBCNT1
, "GDM1_RX_GBCNT1"),
129 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GPCNT1
, "GDM1_RX_GPCNT1"),
130 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_OERCNT
, "GDM1_RX_OERCNT"),
131 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FERCNT
, "GDM1_RX_FERCNT"),
132 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_SERCNT
, "GDM1_RX_SERCNT"),
133 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_LERCNT
, "GDM1_RX_LERCNT"),
134 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_CERCNT
, "GDM1_RX_CERCNT"),
135 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FCCNT
, "GDM1_RX_FCCNT"),
136 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GBCNT
, "GDM2_TX_GBCNT"),
137 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GPCNT
, "GDM2_TX_GPCNT"),
138 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_SKIPCNT
, "GDM2_TX_SKIPCNT"),
139 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_COLCNT
, "GDM2_TX_COLCNT"),
140 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GBCNT
, "GDM2_RX_GBCNT"),
141 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GPCNT
, "GDM2_RX_GPCNT"),
142 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_OERCNT
, "GDM2_RX_OERCNT"),
143 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FERCNT
, "GDM2_RX_FERCNT"),
144 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_SERCNT
, "GDM2_RX_SERCNT"),
145 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_LERCNT
, "GDM2_RX_LERCNT"),
146 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_CERCNT
, "GDM2_RX_CERCNT"),
147 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FCCNT
, "GDM2_RX_FCCNT")
150 static const struct mt7xxx_mib_desc mt7620_port_mibs
[] = {
151 MIB_DESC(1, MT7620_MIB_STATS_PORT_TGPCN
, "TxGPC"),
152 MIB_DESC(1, MT7620_MIB_STATS_PORT_TBOCN
, "TxBOC"),
153 MIB_DESC(1, MT7620_MIB_STATS_PORT_TGOCN
, "TxGOC"),
154 MIB_DESC(1, MT7620_MIB_STATS_PORT_TEPCN
, "TxEPC"),
155 MIB_DESC(1, MT7620_MIB_STATS_PORT_RGPCN
, "RxGPC"),
156 MIB_DESC(1, MT7620_MIB_STATS_PORT_RBOCN
, "RxBOC"),
157 MIB_DESC(1, MT7620_MIB_STATS_PORT_RGOCN
, "RxGOC"),
158 MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC1N
, "RxEPC1"),
159 MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC2N
, "RxEPC2")
162 static const struct mt7xxx_mib_desc mt7621_mibs
[] = {
163 MIB_DESC(1, MT7621_STATS_TDPC
, "TxDrop"),
164 MIB_DESC(1, MT7621_STATS_TCRC
, "TxCRC"),
165 MIB_DESC(1, MT7621_STATS_TUPC
, "TxUni"),
166 MIB_DESC(1, MT7621_STATS_TMPC
, "TxMulti"),
167 MIB_DESC(1, MT7621_STATS_TBPC
, "TxBroad"),
168 MIB_DESC(1, MT7621_STATS_TCEC
, "TxCollision"),
169 MIB_DESC(1, MT7621_STATS_TSCEC
, "TxSingleCol"),
170 MIB_DESC(1, MT7621_STATS_TMCEC
, "TxMultiCol"),
171 MIB_DESC(1, MT7621_STATS_TDEC
, "TxDefer"),
172 MIB_DESC(1, MT7621_STATS_TLCEC
, "TxLateCol"),
173 MIB_DESC(1, MT7621_STATS_TXCEC
, "TxExcCol"),
174 MIB_DESC(1, MT7621_STATS_TPPC
, "TxPause"),
175 MIB_DESC(1, MT7621_STATS_TL64PC
, "Tx64Byte"),
176 MIB_DESC(1, MT7621_STATS_TL65PC
, "Tx65Byte"),
177 MIB_DESC(1, MT7621_STATS_TL128PC
, "Tx128Byte"),
178 MIB_DESC(1, MT7621_STATS_TL256PC
, "Tx256Byte"),
179 MIB_DESC(1, MT7621_STATS_TL512PC
, "Tx512Byte"),
180 MIB_DESC(1, MT7621_STATS_TL1024PC
, "Tx1024Byte"),
181 MIB_DESC(2, MT7621_STATS_TOC
, "TxByte"),
182 MIB_DESC(1, MT7621_STATS_RDPC
, "RxDrop"),
183 MIB_DESC(1, MT7621_STATS_RFPC
, "RxFiltered"),
184 MIB_DESC(1, MT7621_STATS_RUPC
, "RxUni"),
185 MIB_DESC(1, MT7621_STATS_RMPC
, "RxMulti"),
186 MIB_DESC(1, MT7621_STATS_RBPC
, "RxBroad"),
187 MIB_DESC(1, MT7621_STATS_RAEPC
, "RxAlignErr"),
188 MIB_DESC(1, MT7621_STATS_RCEPC
, "RxCRC"),
189 MIB_DESC(1, MT7621_STATS_RUSPC
, "RxUnderSize"),
190 MIB_DESC(1, MT7621_STATS_RFEPC
, "RxFragment"),
191 MIB_DESC(1, MT7621_STATS_ROSPC
, "RxOverSize"),
192 MIB_DESC(1, MT7621_STATS_RJEPC
, "RxJabber"),
193 MIB_DESC(1, MT7621_STATS_RPPC
, "RxPause"),
194 MIB_DESC(1, MT7621_STATS_RL64PC
, "Rx64Byte"),
195 MIB_DESC(1, MT7621_STATS_RL65PC
, "Rx65Byte"),
196 MIB_DESC(1, MT7621_STATS_RL128PC
, "Rx128Byte"),
197 MIB_DESC(1, MT7621_STATS_RL256PC
, "Rx256Byte"),
198 MIB_DESC(1, MT7621_STATS_RL512PC
, "Rx512Byte"),
199 MIB_DESC(1, MT7621_STATS_RL1024PC
, "Rx1024Byte"),
200 MIB_DESC(2, MT7621_STATS_ROC
, "RxByte"),
201 MIB_DESC(1, MT7621_STATS_RDPC_CTRL
, "RxCtrlDrop"),
202 MIB_DESC(1, MT7621_STATS_RDPC_ING
, "RxIngDrop"),
203 MIB_DESC(1, MT7621_STATS_RDPC_ARL
, "RxARLDrop")
207 /* Global attributes. */
208 MT7530_ATTR_ENABLE_VLAN
,
211 struct mt7530_port_entry
{
217 struct mt7530_vlan_entry
{
226 struct switch_dev swdev
;
229 bool global_vlan_enable
;
230 struct mt7530_vlan_entry vlan_entries
[MT7530_NUM_VLANS
];
231 struct mt7530_port_entry port_entries
[MT7530_NUM_PORTS
];
232 char arl_buf
[MT7530_NUM_ARL_RECORDS
* ARL_LINE_LENGTH
+ 1];
235 struct mt7530_mapping
{
237 u16 pvids
[MT7530_NUM_PORTS
];
238 u8 members
[MT7530_NUM_VLANS
];
239 u8 etags
[MT7530_NUM_VLANS
];
240 u16 vids
[MT7530_NUM_VLANS
];
241 } mt7530_defaults
[] = {
244 .pvids
= { 1, 1, 1, 1, 2, 1, 1 },
245 .members
= { 0, 0x6f, 0x50 },
246 .etags
= { 0, 0x40, 0x40 },
250 .pvids
= { 2, 1, 1, 1, 1, 1, 1 },
251 .members
= { 0, 0x7e, 0x41 },
252 .etags
= { 0, 0x40, 0x40 },
256 .pvids
= { 1, 2, 1, 1, 1, 1, 1 },
257 .members
= { 0, 0x7d, 0x42 },
258 .etags
= { 0, 0x40, 0x40 },
263 struct mt7530_mapping
*
264 mt7530_find_mapping(struct device_node
*np
)
269 if (of_property_read_string(np
, "mediatek,portmap", &map
))
272 for (i
= 0; i
< ARRAY_SIZE(mt7530_defaults
); i
++)
273 if (!strcmp(map
, mt7530_defaults
[i
].name
))
274 return &mt7530_defaults
[i
];
280 mt7530_apply_mapping(struct mt7530_priv
*mt7530
, struct mt7530_mapping
*map
)
284 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++)
285 mt7530
->port_entries
[i
].pvid
= map
->pvids
[i
];
287 for (i
= 0; i
< MT7530_NUM_VLANS
; i
++) {
288 mt7530
->vlan_entries
[i
].member
= map
->members
[i
];
289 mt7530
->vlan_entries
[i
].etags
= map
->etags
[i
];
290 mt7530
->vlan_entries
[i
].vid
= map
->vids
[i
];
295 mt7530_reset_switch(struct switch_dev
*dev
)
297 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
300 memset(priv
->port_entries
, 0, sizeof(priv
->port_entries
));
301 memset(priv
->vlan_entries
, 0, sizeof(priv
->vlan_entries
));
303 /* set default vid of each vlan to the same number of vlan, so the vid
304 * won't need be set explicitly.
306 for (i
= 0; i
< MT7530_NUM_VLANS
; i
++) {
307 priv
->vlan_entries
[i
].vid
= i
;
314 mt7530_get_vlan_enable(struct switch_dev
*dev
,
315 const struct switch_attr
*attr
,
316 struct switch_val
*val
)
318 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
320 val
->value
.i
= priv
->global_vlan_enable
;
326 mt7530_set_vlan_enable(struct switch_dev
*dev
,
327 const struct switch_attr
*attr
,
328 struct switch_val
*val
)
330 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
332 priv
->global_vlan_enable
= val
->value
.i
!= 0;
338 mt7530_r32(struct mt7530_priv
*priv
, u32 reg
)
344 mdiobus_write(priv
->bus
, 0x1f, 0x1f, (reg
>> 6) & 0x3ff);
345 low
= mdiobus_read(priv
->bus
, 0x1f, (reg
>> 2) & 0xf);
346 high
= mdiobus_read(priv
->bus
, 0x1f, 0x10);
348 return (high
<< 16) | (low
& 0xffff);
351 val
= ioread32(priv
->base
+ reg
);
352 pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg
, val
);
358 mt7530_w32(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
361 mdiobus_write(priv
->bus
, 0x1f, 0x1f, (reg
>> 6) & 0x3ff);
362 mdiobus_write(priv
->bus
, 0x1f, (reg
>> 2) & 0xf, val
& 0xffff);
363 mdiobus_write(priv
->bus
, 0x1f, 0x10, val
>> 16);
367 pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg
, val
);
368 iowrite32(val
, priv
->base
+ reg
);
372 mt7530_vtcr(struct mt7530_priv
*priv
, u32 cmd
, u32 val
)
376 mt7530_w32(priv
, REG_ESW_VLAN_VTCR
, BIT(31) | (cmd
<< 12) | val
);
378 for (i
= 0; i
< 20; i
++) {
379 u32 val
= mt7530_r32(priv
, REG_ESW_VLAN_VTCR
);
381 if ((val
& BIT(31)) == 0)
387 printk("mt7530: vtcr timeout\n");
391 mt7530_get_port_pvid(struct switch_dev
*dev
, int port
, int *val
)
393 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
395 if (port
>= MT7530_NUM_PORTS
)
398 *val
= mt7530_r32(priv
, REG_ESW_PORT_PPBV1(port
));
405 mt7530_set_port_pvid(struct switch_dev
*dev
, int port
, int pvid
)
407 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
409 if (port
>= MT7530_NUM_PORTS
)
412 if (pvid
< MT7530_MIN_VID
|| pvid
> MT7530_MAX_VID
)
415 priv
->port_entries
[port
].pvid
= pvid
;
421 mt7530_get_vlan_ports(struct switch_dev
*dev
, struct switch_val
*val
)
423 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
430 if (val
->port_vlan
< 0 || val
->port_vlan
>= MT7530_NUM_VLANS
)
433 mt7530_vtcr(priv
, 0, val
->port_vlan
);
435 member
= mt7530_r32(priv
, REG_ESW_VLAN_VAWD1
);
439 etags
= mt7530_r32(priv
, REG_ESW_VLAN_VAWD2
);
441 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
442 struct switch_port
*p
;
445 if (!(member
& BIT(i
)))
448 p
= &val
->value
.ports
[val
->len
++];
451 etag
= (etags
>> (i
* 2)) & 0x3;
453 if (etag
== ETAG_CTRL_TAG
)
454 p
->flags
|= BIT(SWITCH_PORT_FLAG_TAGGED
);
455 else if (etag
!= ETAG_CTRL_UNTAG
)
456 printk("vlan %d port %d egress tag control neither untag nor tag: %d.\n",
457 val
->port_vlan
, i
, etag
);
464 mt7530_set_vlan_ports(struct switch_dev
*dev
, struct switch_val
*val
)
466 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
471 if (val
->port_vlan
< 0 || val
->port_vlan
>= MT7530_NUM_VLANS
||
472 val
->len
> MT7530_NUM_PORTS
)
475 for (i
= 0; i
< val
->len
; i
++) {
476 struct switch_port
*p
= &val
->value
.ports
[i
];
478 if (p
->id
>= MT7530_NUM_PORTS
)
481 member
|= BIT(p
->id
);
483 if (p
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
))
486 priv
->vlan_entries
[val
->port_vlan
].member
= member
;
487 priv
->vlan_entries
[val
->port_vlan
].etags
= etags
;
493 mt7530_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
494 struct switch_val
*val
)
496 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
500 vlan
= val
->port_vlan
;
501 vid
= (u16
)val
->value
.i
;
503 if (vlan
< 0 || vlan
>= MT7530_NUM_VLANS
)
506 if (vid
< MT7530_MIN_VID
|| vid
> MT7530_MAX_VID
)
509 priv
->vlan_entries
[vlan
].vid
= vid
;
514 mt7621_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
515 struct switch_val
*val
)
517 val
->value
.i
= val
->port_vlan
;
522 mt7530_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
523 struct switch_val
*val
)
525 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
529 vlan
= val
->port_vlan
;
531 vid
= mt7530_r32(priv
, REG_ESW_VLAN_VTIM(vlan
));
541 mt7530_get_mirror_monitor_port(struct switch_dev
*dev
, const struct switch_attr
*attr
,
542 struct switch_val
*val
)
544 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
546 val
->value
.i
= priv
->mirror_dest_port
;
552 mt7530_set_mirror_monitor_port(struct switch_dev
*dev
, const struct switch_attr
*attr
,
553 struct switch_val
*val
)
555 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
557 priv
->mirror_dest_port
= val
->value
.i
;
563 mt7530_get_port_mirror_rx(struct switch_dev
*dev
, const struct switch_attr
*attr
,
564 struct switch_val
*val
)
566 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
568 val
->value
.i
= priv
->port_entries
[val
->port_vlan
].mirror_rx
;
574 mt7530_set_port_mirror_rx(struct switch_dev
*dev
, const struct switch_attr
*attr
,
575 struct switch_val
*val
)
577 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
579 priv
->port_entries
[val
->port_vlan
].mirror_rx
= val
->value
.i
;
585 mt7530_get_port_mirror_tx(struct switch_dev
*dev
, const struct switch_attr
*attr
,
586 struct switch_val
*val
)
588 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
590 val
->value
.i
= priv
->port_entries
[val
->port_vlan
].mirror_tx
;
596 mt7530_set_port_mirror_tx(struct switch_dev
*dev
, const struct switch_attr
*attr
,
597 struct switch_val
*val
)
599 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
601 priv
->port_entries
[val
->port_vlan
].mirror_tx
= val
->value
.i
;
607 mt7530_write_vlan_entry(struct mt7530_priv
*priv
, int vlan
, u16 vid
,
613 #ifndef CONFIG_SOC_MT7621
615 val
= mt7530_r32(priv
, REG_ESW_VLAN_VTIM(vlan
));
623 mt7530_w32(priv
, REG_ESW_VLAN_VTIM(vlan
), val
);
626 /* vlan port membership */
628 mt7530_w32(priv
, REG_ESW_VLAN_VAWD1
, REG_ESW_VLAN_VAWD1_IVL_MAC
|
629 REG_ESW_VLAN_VAWD1_VTAG_EN
| (ports
<< 16) |
630 REG_ESW_VLAN_VAWD1_VALID
);
632 mt7530_w32(priv
, REG_ESW_VLAN_VAWD1
, 0);
636 for (port
= 0; port
< MT7530_NUM_PORTS
; port
++) {
637 if (etags
& BIT(port
))
638 val
|= ETAG_CTRL_TAG
<< (port
* 2);
640 val
|= ETAG_CTRL_UNTAG
<< (port
* 2);
642 mt7530_w32(priv
, REG_ESW_VLAN_VAWD2
, val
);
644 /* write to vlan table */
645 #ifdef CONFIG_SOC_MT7621
646 mt7530_vtcr(priv
, 1, vid
);
648 mt7530_vtcr(priv
, 1, vlan
);
653 mt7530_apply_config(struct switch_dev
*dev
)
655 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
659 bool is_mirror
= false;
661 if (!priv
->global_vlan_enable
) {
662 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++)
663 mt7530_w32(priv
, REG_ESW_PORT_PCR(i
), 0x00400000);
665 mt7530_w32(priv
, REG_ESW_PORT_PCR(MT7530_CPU_PORT
), 0x00ff0000);
667 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++)
668 mt7530_w32(priv
, REG_ESW_PORT_PVC(i
), 0x810000c0);
673 /* set all ports as security mode */
674 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++)
675 mt7530_w32(priv
, REG_ESW_PORT_PCR(i
), 0x00ff0003);
677 /* check if a port is used in tag/untag vlan egress mode */
681 for (i
= 0; i
< MT7530_NUM_VLANS
; i
++) {
682 u8 member
= priv
->vlan_entries
[i
].member
;
683 u8 etags
= priv
->vlan_entries
[i
].etags
;
688 for (j
= 0; j
< MT7530_NUM_PORTS
; j
++) {
689 if (!(member
& BIT(j
)))
693 tag_ports
|= 1u << j
;
695 untag_ports
|= 1u << j
;
699 /* set all untag-only ports as transparent and the rest as user port */
700 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
701 u32 pvc_mode
= 0x81000000;
703 if (untag_ports
& BIT(i
) && !(tag_ports
& BIT(i
)))
704 pvc_mode
= 0x810000c0;
706 mt7530_w32(priv
, REG_ESW_PORT_PVC(i
), pvc_mode
);
709 /* first clear the swtich vlan table */
710 for (i
= 0; i
< MT7530_NUM_VLANS
; i
++)
711 mt7530_write_vlan_entry(priv
, i
, i
, 0, 0);
713 /* now program only vlans with members to avoid
714 clobbering remapped entries in later iterations */
715 for (i
= 0; i
< MT7530_NUM_VLANS
; i
++) {
716 u16 vid
= priv
->vlan_entries
[i
].vid
;
717 u8 member
= priv
->vlan_entries
[i
].member
;
718 u8 etags
= priv
->vlan_entries
[i
].etags
;
721 mt7530_write_vlan_entry(priv
, i
, vid
, member
, etags
);
724 /* Port Default PVID */
725 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
726 int vlan
= priv
->port_entries
[i
].pvid
;
730 if (vlan
< MT7530_NUM_VLANS
&& priv
->vlan_entries
[vlan
].member
)
731 pvid
= priv
->vlan_entries
[vlan
].vid
;
733 val
= mt7530_r32(priv
, REG_ESW_PORT_PPBV1(i
));
736 mt7530_w32(priv
, REG_ESW_PORT_PPBV1(i
), val
);
739 /* set mirroring source port */
740 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
741 u32 val
= mt7530_r32(priv
, REG_ESW_PORT_PCR(i
));
742 if (priv
->port_entries
[i
].mirror_rx
) {
743 val
|= REG_ESW_PORT_PCR_MIRROR_SRC_RX_BIT
;
747 if (priv
->port_entries
[i
].mirror_tx
) {
748 val
|= REG_ESW_PORT_PCR_MIRROR_SRC_TX_BIT
;
752 mt7530_w32(priv
, REG_ESW_PORT_PCR(i
), val
);
755 /* set mirroring monitor port */
757 u32 val
= mt7530_r32(priv
, REG_ESW_WT_MAC_MFC
);
758 val
|= REG_ESW_WT_MAC_MFC_MIRROR_ENABLE
;
759 val
&= ~REG_ESW_WT_MAC_MFC_MIRROR_DEST_MASK
;
760 val
|= priv
->mirror_dest_port
;
761 mt7530_w32(priv
, REG_ESW_WT_MAC_MFC
, val
);
768 mt7530_get_port_link(struct switch_dev
*dev
, int port
,
769 struct switch_port_link
*link
)
771 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
774 if (port
< 0 || port
>= MT7530_NUM_PORTS
)
777 pmsr
= mt7530_r32(priv
, 0x3008 + (0x100 * port
));
779 link
->link
= pmsr
& 1;
780 link
->duplex
= (pmsr
>> 1) & 1;
781 speed
= (pmsr
>> 2) & 3;
785 link
->speed
= SWITCH_PORT_SPEED_10
;
788 link
->speed
= SWITCH_PORT_SPEED_100
;
791 case 3: /* forced gige speed can be 2 or 3 */
792 link
->speed
= SWITCH_PORT_SPEED_1000
;
795 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
802 static u64
get_mib_counter(struct mt7530_priv
*priv
, int i
, int port
)
804 unsigned int port_base
;
807 port_base
= MT7621_MIB_COUNTER_BASE
+
808 MT7621_MIB_COUNTER_PORT_OFFSET
* port
;
810 lo
= mt7530_r32(priv
, port_base
+ mt7621_mibs
[i
].offset
);
811 if (mt7621_mibs
[i
].size
== 2) {
814 hi
= mt7530_r32(priv
, port_base
+ mt7621_mibs
[i
].offset
+ 4);
821 static int mt7621_sw_get_port_mib(struct switch_dev
*dev
,
822 const struct switch_attr
*attr
,
823 struct switch_val
*val
)
825 static char buf
[4096];
826 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
829 if (val
->port_vlan
>= MT7530_NUM_PORTS
)
832 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
833 "Port %d MIB counters\n", val
->port_vlan
);
835 for (i
= 0; i
< ARRAY_SIZE(mt7621_mibs
); ++i
) {
837 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
838 "%-11s: ", mt7621_mibs
[i
].name
);
839 counter
= get_mib_counter(priv
, i
, val
->port_vlan
);
840 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
, "%llu\n",
849 static u64
get_mib_counter_7620(struct mt7530_priv
*priv
, int i
)
851 return mt7530_r32(priv
, MT7620_MIB_COUNTER_BASE
+ mt7620_mibs
[i
].offset
);
854 static u64
get_mib_counter_port_7620(struct mt7530_priv
*priv
, int i
, int port
)
856 return mt7530_r32(priv
,
857 MT7620_MIB_COUNTER_BASE_PORT
+
858 (MT7620_MIB_COUNTER_PORT_OFFSET
* port
) +
859 mt7620_port_mibs
[i
].offset
);
862 static int mt7530_sw_get_mib(struct switch_dev
*dev
,
863 const struct switch_attr
*attr
,
864 struct switch_val
*val
)
866 static char buf
[4096];
867 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
870 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
, "Switch MIB counters\n");
872 for (i
= 0; i
< ARRAY_SIZE(mt7620_mibs
); ++i
) {
874 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
875 "%-11s: ", mt7620_mibs
[i
].name
);
876 counter
= get_mib_counter_7620(priv
, i
);
877 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
, "%llu\n",
886 static char *mt7530_print_arl_table_row(u32 atrd
,
900 port_map
= (u8
)((atrd
& REG_ATRD_PORT_MASK
) >> 4);
901 memcpy(mac
, &mac1
, sizeof(mac1
));
902 memcpy(mac
+ sizeof(mac1
), &mac2
, sizeof(mac
) - sizeof(mac1
));
903 for (port
= 0, i
= 1; port
< MT7530_NUM_PORTS
; ++port
, i
<<= 1) {
905 ret
= snprintf(buf
, *size
, "Port %d: MAC %pM\n", port
, mac
);
906 if (ret
>= *size
|| ret
<= 0) {
919 static int mt7530_get_arl_table(struct switch_dev
*dev
,
920 const struct switch_attr
*attr
,
921 struct switch_val
*val
)
923 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
924 char *buf
= priv
->arl_buf
;
925 size_t size
= sizeof(priv
->arl_buf
);
927 size_t retry_times
= 100;
931 ret
= snprintf(buf
, size
, "address resolution table\n");
932 if (ret
>= size
|| ret
<= 0) {
933 priv
->arl_buf
[0] = 0;
939 mt7530_w32(priv
, REG_ESW_WT_MAC_ATC
, REG_MAC_ATC_START
);
942 atc
= mt7530_r32(priv
, REG_ESW_WT_MAC_ATC
);
943 if (atc
& REG_MAC_ATC_SRCH_HIT
&& !(atc
& REG_MAC_ATC_BUSY
)) {
947 atrd
= mt7530_r32(priv
, REG_ESW_TABLE_ATRD
);
948 if (atrd
& REG_ATRD_VALID
) {
952 mac1
= mt7530_r32(priv
, REG_ESW_TABLE_TSRA1
);
953 mac2
= mt7530_r32(priv
, REG_ESW_TABLE_TSRA2
);
955 if (!(atc
& REG_MAC_ATC_SRCH_END
))
956 mt7530_w32(priv
, REG_ESW_WT_MAC_ATC
, REG_MAC_ATC_NEXT
);
958 buf
= mt7530_print_arl_table_row(atrd
, mac1
, mac2
, buf
, &size
);
960 pr_warn("%s: too many addresses\n", __func__
);
963 } else if (!(atc
& REG_MAC_ATC_SRCH_END
)) {
964 mt7530_w32(priv
, REG_ESW_WT_MAC_ATC
, REG_MAC_ATC_NEXT
);
968 usleep_range(1000, 5000);
970 } while (!(atc
& REG_MAC_ATC_SRCH_END
) &&
971 count
< MT7530_NUM_ARL_RECORDS
&&
974 val
->value
.s
= priv
->arl_buf
;
975 val
->len
= strlen(priv
->arl_buf
);
980 static int mt7530_sw_get_port_mib(struct switch_dev
*dev
,
981 const struct switch_attr
*attr
,
982 struct switch_val
*val
)
984 static char buf
[4096];
985 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
988 if (val
->port_vlan
>= MT7530_NUM_PORTS
)
991 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
992 "Port %d MIB counters\n", val
->port_vlan
);
994 for (i
= 0; i
< ARRAY_SIZE(mt7620_port_mibs
); ++i
) {
996 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
997 "%-11s: ", mt7620_port_mibs
[i
].name
);
998 counter
= get_mib_counter_port_7620(priv
, i
, val
->port_vlan
);
999 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
, "%llu\n",
1008 static int mt7530_get_port_stats(struct switch_dev
*dev
, int port
,
1009 struct switch_port_stats
*stats
)
1011 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
1013 if (port
< 0 || port
>= MT7530_NUM_PORTS
)
1016 stats
->tx_bytes
= get_mib_counter_port_7620(priv
, MT7530_PORT_MIB_TXB_ID
, port
);
1017 stats
->rx_bytes
= get_mib_counter_port_7620(priv
, MT7530_PORT_MIB_RXB_ID
, port
);
1022 static int mt7621_get_port_stats(struct switch_dev
*dev
, int port
,
1023 struct switch_port_stats
*stats
)
1025 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
1027 if (port
< 0 || port
>= MT7530_NUM_PORTS
)
1030 stats
->tx_bytes
= get_mib_counter(priv
, MT7621_PORT_MIB_TXB_ID
, port
);
1031 stats
->rx_bytes
= get_mib_counter(priv
, MT7621_PORT_MIB_RXB_ID
, port
);
1036 static const struct switch_attr mt7530_global
[] = {
1038 .type
= SWITCH_TYPE_INT
,
1039 .name
= "enable_vlan",
1040 .description
= "VLAN mode (1:enabled)",
1042 .id
= MT7530_ATTR_ENABLE_VLAN
,
1043 .get
= mt7530_get_vlan_enable
,
1044 .set
= mt7530_set_vlan_enable
,
1046 .type
= SWITCH_TYPE_STRING
,
1048 .description
= "Get MIB counters for switch",
1049 .get
= mt7530_sw_get_mib
,
1052 .type
= SWITCH_TYPE_INT
,
1053 .name
= "mirror_monitor_port",
1054 .description
= "Mirror monitor port",
1055 .set
= mt7530_set_mirror_monitor_port
,
1056 .get
= mt7530_get_mirror_monitor_port
,
1057 .max
= MT7530_NUM_PORTS
- 1
1060 .type
= SWITCH_TYPE_STRING
,
1061 .name
= "arl_table",
1062 .description
= "Get ARL table",
1064 .get
= mt7530_get_arl_table
,
1068 static const struct switch_attr mt7621_port
[] = {
1070 .type
= SWITCH_TYPE_STRING
,
1072 .description
= "Get MIB counters for port",
1073 .get
= mt7621_sw_get_port_mib
,
1076 .type
= SWITCH_TYPE_INT
,
1077 .name
= "enable_mirror_rx",
1078 .description
= "Enable mirroring of RX packets",
1079 .set
= mt7530_set_port_mirror_rx
,
1080 .get
= mt7530_get_port_mirror_rx
,
1083 .type
= SWITCH_TYPE_INT
,
1084 .name
= "enable_mirror_tx",
1085 .description
= "Enable mirroring of TX packets",
1086 .set
= mt7530_set_port_mirror_tx
,
1087 .get
= mt7530_get_port_mirror_tx
,
1092 static const struct switch_attr mt7621_vlan
[] = {
1094 .type
= SWITCH_TYPE_INT
,
1096 .description
= "VLAN ID (0-4094)",
1097 .set
= mt7530_set_vid
,
1098 .get
= mt7621_get_vid
,
1103 static const struct switch_attr mt7530_port
[] = {
1105 .type
= SWITCH_TYPE_STRING
,
1107 .description
= "Get MIB counters for port",
1108 .get
= mt7530_sw_get_port_mib
,
1111 .type
= SWITCH_TYPE_INT
,
1112 .name
= "enable_mirror_rx",
1113 .description
= "Enable mirroring of RX packets",
1114 .set
= mt7530_set_port_mirror_rx
,
1115 .get
= mt7530_get_port_mirror_rx
,
1118 .type
= SWITCH_TYPE_INT
,
1119 .name
= "enable_mirror_tx",
1120 .description
= "Enable mirroring of TX packets",
1121 .set
= mt7530_set_port_mirror_tx
,
1122 .get
= mt7530_get_port_mirror_tx
,
1127 static const struct switch_attr mt7530_vlan
[] = {
1129 .type
= SWITCH_TYPE_INT
,
1131 .description
= "VLAN ID (0-4094)",
1132 .set
= mt7530_set_vid
,
1133 .get
= mt7530_get_vid
,
1138 static const struct switch_dev_ops mt7621_ops
= {
1140 .attr
= mt7530_global
,
1141 .n_attr
= ARRAY_SIZE(mt7530_global
),
1144 .attr
= mt7621_port
,
1145 .n_attr
= ARRAY_SIZE(mt7621_port
),
1148 .attr
= mt7621_vlan
,
1149 .n_attr
= ARRAY_SIZE(mt7621_vlan
),
1151 .get_vlan_ports
= mt7530_get_vlan_ports
,
1152 .set_vlan_ports
= mt7530_set_vlan_ports
,
1153 .get_port_pvid
= mt7530_get_port_pvid
,
1154 .set_port_pvid
= mt7530_set_port_pvid
,
1155 .get_port_link
= mt7530_get_port_link
,
1156 .get_port_stats
= mt7621_get_port_stats
,
1157 .apply_config
= mt7530_apply_config
,
1158 .reset_switch
= mt7530_reset_switch
,
1161 static const struct switch_dev_ops mt7530_ops
= {
1163 .attr
= mt7530_global
,
1164 .n_attr
= ARRAY_SIZE(mt7530_global
),
1167 .attr
= mt7530_port
,
1168 .n_attr
= ARRAY_SIZE(mt7530_port
),
1171 .attr
= mt7530_vlan
,
1172 .n_attr
= ARRAY_SIZE(mt7530_vlan
),
1174 .get_vlan_ports
= mt7530_get_vlan_ports
,
1175 .set_vlan_ports
= mt7530_set_vlan_ports
,
1176 .get_port_pvid
= mt7530_get_port_pvid
,
1177 .set_port_pvid
= mt7530_set_port_pvid
,
1178 .get_port_link
= mt7530_get_port_link
,
1179 .get_port_stats
= mt7530_get_port_stats
,
1180 .apply_config
= mt7530_apply_config
,
1181 .reset_switch
= mt7530_reset_switch
,
1185 mt7530_probe(struct device
*dev
, void __iomem
*base
, struct mii_bus
*bus
, int vlan
)
1187 struct switch_dev
*swdev
;
1188 struct mt7530_priv
*mt7530
;
1189 struct mt7530_mapping
*map
;
1192 mt7530
= devm_kzalloc(dev
, sizeof(struct mt7530_priv
), GFP_KERNEL
);
1196 mt7530
->base
= base
;
1198 mt7530
->global_vlan_enable
= vlan
;
1200 swdev
= &mt7530
->swdev
;
1202 swdev
->alias
= "mt7530";
1203 swdev
->name
= "mt7530";
1204 } else if (IS_ENABLED(CONFIG_SOC_MT7621
)) {
1205 swdev
->alias
= "mt7621";
1206 swdev
->name
= "mt7621";
1208 swdev
->alias
= "mt7620";
1209 swdev
->name
= "mt7620";
1211 swdev
->cpu_port
= MT7530_CPU_PORT
;
1212 swdev
->ports
= MT7530_NUM_PORTS
;
1213 swdev
->vlans
= MT7530_NUM_VLANS
;
1214 if (IS_ENABLED(CONFIG_SOC_MT7621
))
1215 swdev
->ops
= &mt7621_ops
;
1217 swdev
->ops
= &mt7530_ops
;
1219 ret
= register_switch(swdev
, NULL
);
1221 dev_err(dev
, "failed to register mt7530\n");
1226 map
= mt7530_find_mapping(dev
->of_node
);
1228 mt7530_apply_mapping(mt7530
, map
);
1229 mt7530_apply_config(swdev
);
1232 if (!IS_ENABLED(CONFIG_SOC_MT7621
) && bus
&& mt7530_r32(mt7530
, REG_HWTRAP
) != 0x1117edf) {
1233 dev_info(dev
, "fixing up MHWTRAP register - bootloader probably played with it\n");
1234 mt7530_w32(mt7530
, REG_HWTRAP
, 0x1117edf);
1236 dev_info(dev
, "loaded %s driver\n", swdev
->name
);