1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
32 #include <linux/bug.h>
33 #include <linux/netfilter.h>
34 #include <net/netfilter/nf_flow_table.h>
35 #include <linux/of_gpio.h>
36 #include <linux/gpio.h>
37 #include <linux/gpio/consumer.h>
39 #include <asm/mach-ralink/ralink_regs.h>
41 #include "mtk_eth_soc.h"
45 #define MAX_RX_LENGTH 1536
46 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
47 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
48 #define DMA_DUMMY_DESC 0xffffffff
49 #define FE_DEFAULT_MSG_ENABLE \
59 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
60 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
61 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
62 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
64 #define SYSC_REG_RSTCTRL 0x34
66 static int fe_msg_level
= -1;
67 module_param_named(msg_level
, fe_msg_level
, int, 0);
68 MODULE_PARM_DESC(msg_level
, "Message level (-1=defaults,0=none,...,16=all)");
70 static const u16 fe_reg_table_default
[FE_REG_COUNT
] = {
71 [FE_REG_PDMA_GLO_CFG
] = FE_PDMA_GLO_CFG
,
72 [FE_REG_PDMA_RST_CFG
] = FE_PDMA_RST_CFG
,
73 [FE_REG_DLY_INT_CFG
] = FE_DLY_INT_CFG
,
74 [FE_REG_TX_BASE_PTR0
] = FE_TX_BASE_PTR0
,
75 [FE_REG_TX_MAX_CNT0
] = FE_TX_MAX_CNT0
,
76 [FE_REG_TX_CTX_IDX0
] = FE_TX_CTX_IDX0
,
77 [FE_REG_TX_DTX_IDX0
] = FE_TX_DTX_IDX0
,
78 [FE_REG_RX_BASE_PTR0
] = FE_RX_BASE_PTR0
,
79 [FE_REG_RX_MAX_CNT0
] = FE_RX_MAX_CNT0
,
80 [FE_REG_RX_CALC_IDX0
] = FE_RX_CALC_IDX0
,
81 [FE_REG_RX_DRX_IDX0
] = FE_RX_DRX_IDX0
,
82 [FE_REG_FE_INT_ENABLE
] = FE_FE_INT_ENABLE
,
83 [FE_REG_FE_INT_STATUS
] = FE_FE_INT_STATUS
,
84 [FE_REG_FE_DMA_VID_BASE
] = FE_DMA_VID0
,
85 [FE_REG_FE_COUNTER_BASE
] = FE_GDMA1_TX_GBCNT
,
86 [FE_REG_FE_RST_GL
] = FE_FE_RST_GL
,
89 static const u16
*fe_reg_table
= fe_reg_table_default
;
93 void (*action
)(struct fe_priv
*);
96 static void __iomem
*fe_base
;
98 void fe_w32(u32 val
, unsigned reg
)
100 __raw_writel(val
, fe_base
+ reg
);
103 u32
fe_r32(unsigned reg
)
105 return __raw_readl(fe_base
+ reg
);
108 void fe_reg_w32(u32 val
, enum fe_reg reg
)
110 fe_w32(val
, fe_reg_table
[reg
]);
113 u32
fe_reg_r32(enum fe_reg reg
)
115 return fe_r32(fe_reg_table
[reg
]);
118 void fe_m32(struct fe_priv
*eth
, u32 clear
, u32 set
, unsigned reg
)
122 spin_lock(ð
->page_lock
);
123 val
= __raw_readl(fe_base
+ reg
);
126 __raw_writel(val
, fe_base
+ reg
);
127 spin_unlock(ð
->page_lock
);
130 void fe_reset(u32 reset_bits
)
134 t
= rt_sysc_r32(SYSC_REG_RSTCTRL
);
136 rt_sysc_w32(t
, SYSC_REG_RSTCTRL
);
137 usleep_range(10, 20);
140 rt_sysc_w32(t
, SYSC_REG_RSTCTRL
);
141 usleep_range(10, 20);
144 void fe_reset_fe(struct fe_priv
*priv
)
149 reset_control_assert(priv
->rst_fe
);
150 usleep_range(60, 120);
151 reset_control_deassert(priv
->rst_fe
);
152 usleep_range(60, 120);
155 static inline void fe_int_disable(u32 mask
)
157 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE
) & ~mask
,
158 FE_REG_FE_INT_ENABLE
);
160 fe_reg_r32(FE_REG_FE_INT_ENABLE
);
163 static inline void fe_int_enable(u32 mask
)
165 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE
) | mask
,
166 FE_REG_FE_INT_ENABLE
);
168 fe_reg_r32(FE_REG_FE_INT_ENABLE
);
171 static inline void fe_hw_set_macaddr(struct fe_priv
*priv
, unsigned char *mac
)
175 spin_lock_irqsave(&priv
->page_lock
, flags
);
176 fe_w32((mac
[0] << 8) | mac
[1], FE_GDMA1_MAC_ADRH
);
177 fe_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
179 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
182 static int fe_set_mac_address(struct net_device
*dev
, void *p
)
184 int ret
= eth_mac_addr(dev
, p
);
187 struct fe_priv
*priv
= netdev_priv(dev
);
189 if (priv
->soc
->set_mac
)
190 priv
->soc
->set_mac(priv
, dev
->dev_addr
);
192 fe_hw_set_macaddr(priv
, p
);
198 static inline int fe_max_frag_size(int mtu
)
200 /* make sure buf_size will be at least MAX_RX_LENGTH */
201 if (mtu
+ FE_RX_ETH_HLEN
< MAX_RX_LENGTH
)
202 mtu
= MAX_RX_LENGTH
- FE_RX_ETH_HLEN
;
204 return SKB_DATA_ALIGN(FE_RX_HLEN
+ mtu
) +
205 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
208 static inline int fe_max_buf_size(int frag_size
)
210 int buf_size
= frag_size
- NET_SKB_PAD
- NET_IP_ALIGN
-
211 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
213 BUG_ON(buf_size
< MAX_RX_LENGTH
);
217 static inline void fe_get_rxd(struct fe_rx_dma
*rxd
, struct fe_rx_dma
*dma_rxd
)
219 rxd
->rxd1
= dma_rxd
->rxd1
;
220 rxd
->rxd2
= dma_rxd
->rxd2
;
221 rxd
->rxd3
= dma_rxd
->rxd3
;
222 rxd
->rxd4
= dma_rxd
->rxd4
;
225 static inline void fe_set_txd(struct fe_tx_dma
*txd
, struct fe_tx_dma
*dma_txd
)
227 dma_txd
->txd1
= txd
->txd1
;
228 dma_txd
->txd3
= txd
->txd3
;
229 dma_txd
->txd4
= txd
->txd4
;
230 /* clean dma done flag last */
231 dma_txd
->txd2
= txd
->txd2
;
234 static void fe_clean_rx(struct fe_priv
*priv
)
236 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
241 for (i
= 0; i
< ring
->rx_ring_size
; i
++)
242 if (ring
->rx_data
[i
]) {
243 if (ring
->rx_dma
&& ring
->rx_dma
[i
].rxd1
)
244 dma_unmap_single(priv
->dev
,
245 ring
->rx_dma
[i
].rxd1
,
248 skb_free_frag(ring
->rx_data
[i
]);
251 kfree(ring
->rx_data
);
252 ring
->rx_data
= NULL
;
256 dma_free_coherent(priv
->dev
,
257 ring
->rx_ring_size
* sizeof(*ring
->rx_dma
),
263 if (!ring
->frag_cache
.va
)
266 page
= virt_to_page(ring
->frag_cache
.va
);
267 __page_frag_cache_drain(page
, ring
->frag_cache
.pagecnt_bias
);
268 memset(&ring
->frag_cache
, 0, sizeof(ring
->frag_cache
));
271 static int fe_alloc_rx(struct fe_priv
*priv
)
273 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
276 ring
->rx_data
= kcalloc(ring
->rx_ring_size
, sizeof(*ring
->rx_data
),
281 for (i
= 0; i
< ring
->rx_ring_size
; i
++) {
282 ring
->rx_data
[i
] = page_frag_alloc(&ring
->frag_cache
,
285 if (!ring
->rx_data
[i
])
289 ring
->rx_dma
= dma_alloc_coherent(priv
->dev
,
290 ring
->rx_ring_size
* sizeof(*ring
->rx_dma
),
292 GFP_ATOMIC
| __GFP_ZERO
);
296 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
300 for (i
= 0; i
< ring
->rx_ring_size
; i
++) {
301 dma_addr_t dma_addr
= dma_map_single(priv
->dev
,
302 ring
->rx_data
[i
] + NET_SKB_PAD
+ pad
,
305 if (unlikely(dma_mapping_error(priv
->dev
, dma_addr
)))
307 ring
->rx_dma
[i
].rxd1
= (unsigned int)dma_addr
;
309 if (priv
->flags
& FE_FLAG_RX_SG_DMA
)
310 ring
->rx_dma
[i
].rxd2
= RX_DMA_PLEN0(ring
->rx_buf_size
);
312 ring
->rx_dma
[i
].rxd2
= RX_DMA_LSO
;
314 ring
->rx_calc_idx
= ring
->rx_ring_size
- 1;
315 /* make sure that all changes to the dma ring are flushed before we
320 fe_reg_w32(ring
->rx_phys
, FE_REG_RX_BASE_PTR0
);
321 fe_reg_w32(ring
->rx_ring_size
, FE_REG_RX_MAX_CNT0
);
322 fe_reg_w32(ring
->rx_calc_idx
, FE_REG_RX_CALC_IDX0
);
323 fe_reg_w32(FE_PST_DRX_IDX0
, FE_REG_PDMA_RST_CFG
);
331 static void fe_txd_unmap(struct device
*dev
, struct fe_tx_buf
*tx_buf
)
333 if (dma_unmap_len(tx_buf
, dma_len0
))
335 dma_unmap_addr(tx_buf
, dma_addr0
),
336 dma_unmap_len(tx_buf
, dma_len0
),
339 if (dma_unmap_len(tx_buf
, dma_len1
))
341 dma_unmap_addr(tx_buf
, dma_addr1
),
342 dma_unmap_len(tx_buf
, dma_len1
),
345 dma_unmap_len_set(tx_buf
, dma_addr0
, 0);
346 dma_unmap_len_set(tx_buf
, dma_addr1
, 0);
347 if (tx_buf
->skb
&& (tx_buf
->skb
!= (struct sk_buff
*)DMA_DUMMY_DESC
))
348 dev_kfree_skb_any(tx_buf
->skb
);
352 static void fe_clean_tx(struct fe_priv
*priv
)
355 struct device
*dev
= priv
->dev
;
356 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
359 for (i
= 0; i
< ring
->tx_ring_size
; i
++)
360 fe_txd_unmap(dev
, &ring
->tx_buf
[i
]);
366 dma_free_coherent(dev
,
367 ring
->tx_ring_size
* sizeof(*ring
->tx_dma
),
373 netdev_reset_queue(priv
->netdev
);
376 static int fe_alloc_tx(struct fe_priv
*priv
)
379 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
381 ring
->tx_free_idx
= 0;
382 ring
->tx_next_idx
= 0;
383 ring
->tx_thresh
= max((unsigned long)ring
->tx_ring_size
>> 2,
386 ring
->tx_buf
= kcalloc(ring
->tx_ring_size
, sizeof(*ring
->tx_buf
),
391 ring
->tx_dma
= dma_alloc_coherent(priv
->dev
,
392 ring
->tx_ring_size
* sizeof(*ring
->tx_dma
),
394 GFP_ATOMIC
| __GFP_ZERO
);
398 for (i
= 0; i
< ring
->tx_ring_size
; i
++) {
399 if (priv
->soc
->tx_dma
)
400 priv
->soc
->tx_dma(&ring
->tx_dma
[i
]);
401 ring
->tx_dma
[i
].txd2
= TX_DMA_DESP2_DEF
;
403 /* make sure that all changes to the dma ring are flushed before we
408 fe_reg_w32(ring
->tx_phys
, FE_REG_TX_BASE_PTR0
);
409 fe_reg_w32(ring
->tx_ring_size
, FE_REG_TX_MAX_CNT0
);
410 fe_reg_w32(0, FE_REG_TX_CTX_IDX0
);
411 fe_reg_w32(FE_PST_DTX_IDX0
, FE_REG_PDMA_RST_CFG
);
419 static int fe_init_dma(struct fe_priv
*priv
)
423 err
= fe_alloc_tx(priv
);
427 err
= fe_alloc_rx(priv
);
434 static void fe_free_dma(struct fe_priv
*priv
)
440 void fe_stats_update(struct fe_priv
*priv
)
442 struct fe_hw_stats
*hwstats
= priv
->hw_stats
;
443 unsigned int base
= fe_reg_table
[FE_REG_FE_COUNTER_BASE
];
446 u64_stats_update_begin(&hwstats
->syncp
);
448 if (IS_ENABLED(CONFIG_SOC_MT7621
)) {
449 hwstats
->rx_bytes
+= fe_r32(base
);
450 stats
= fe_r32(base
+ 0x04);
452 hwstats
->rx_bytes
+= (stats
<< 32);
453 hwstats
->rx_packets
+= fe_r32(base
+ 0x08);
454 hwstats
->rx_overflow
+= fe_r32(base
+ 0x10);
455 hwstats
->rx_fcs_errors
+= fe_r32(base
+ 0x14);
456 hwstats
->rx_short_errors
+= fe_r32(base
+ 0x18);
457 hwstats
->rx_long_errors
+= fe_r32(base
+ 0x1c);
458 hwstats
->rx_checksum_errors
+= fe_r32(base
+ 0x20);
459 hwstats
->rx_flow_control_packets
+= fe_r32(base
+ 0x24);
460 hwstats
->tx_skip
+= fe_r32(base
+ 0x28);
461 hwstats
->tx_collisions
+= fe_r32(base
+ 0x2c);
462 hwstats
->tx_bytes
+= fe_r32(base
+ 0x30);
463 stats
= fe_r32(base
+ 0x34);
465 hwstats
->tx_bytes
+= (stats
<< 32);
466 hwstats
->tx_packets
+= fe_r32(base
+ 0x38);
468 hwstats
->tx_bytes
+= fe_r32(base
);
469 hwstats
->tx_packets
+= fe_r32(base
+ 0x04);
470 hwstats
->tx_skip
+= fe_r32(base
+ 0x08);
471 hwstats
->tx_collisions
+= fe_r32(base
+ 0x0c);
472 hwstats
->rx_bytes
+= fe_r32(base
+ 0x20);
473 hwstats
->rx_packets
+= fe_r32(base
+ 0x24);
474 hwstats
->rx_overflow
+= fe_r32(base
+ 0x28);
475 hwstats
->rx_fcs_errors
+= fe_r32(base
+ 0x2c);
476 hwstats
->rx_short_errors
+= fe_r32(base
+ 0x30);
477 hwstats
->rx_long_errors
+= fe_r32(base
+ 0x34);
478 hwstats
->rx_checksum_errors
+= fe_r32(base
+ 0x38);
479 hwstats
->rx_flow_control_packets
+= fe_r32(base
+ 0x3c);
482 u64_stats_update_end(&hwstats
->syncp
);
485 static void fe_get_stats64(struct net_device
*dev
,
486 struct rtnl_link_stats64
*storage
)
488 struct fe_priv
*priv
= netdev_priv(dev
);
489 struct fe_hw_stats
*hwstats
= priv
->hw_stats
;
490 unsigned int base
= fe_reg_table
[FE_REG_FE_COUNTER_BASE
];
494 netdev_stats_to_stats64(storage
, &dev
->stats
);
498 if (netif_running(dev
) && netif_device_present(dev
)) {
499 if (spin_trylock_bh(&hwstats
->stats_lock
)) {
500 fe_stats_update(priv
);
501 spin_unlock_bh(&hwstats
->stats_lock
);
506 start
= u64_stats_fetch_begin_irq(&hwstats
->syncp
);
507 storage
->rx_packets
= hwstats
->rx_packets
;
508 storage
->tx_packets
= hwstats
->tx_packets
;
509 storage
->rx_bytes
= hwstats
->rx_bytes
;
510 storage
->tx_bytes
= hwstats
->tx_bytes
;
511 storage
->collisions
= hwstats
->tx_collisions
;
512 storage
->rx_length_errors
= hwstats
->rx_short_errors
+
513 hwstats
->rx_long_errors
;
514 storage
->rx_over_errors
= hwstats
->rx_overflow
;
515 storage
->rx_crc_errors
= hwstats
->rx_fcs_errors
;
516 storage
->rx_errors
= hwstats
->rx_checksum_errors
;
517 storage
->tx_aborted_errors
= hwstats
->tx_skip
;
518 } while (u64_stats_fetch_retry_irq(&hwstats
->syncp
, start
));
520 storage
->tx_errors
= priv
->netdev
->stats
.tx_errors
;
521 storage
->rx_dropped
= priv
->netdev
->stats
.rx_dropped
;
522 storage
->tx_dropped
= priv
->netdev
->stats
.tx_dropped
;
525 static int fe_vlan_rx_add_vid(struct net_device
*dev
,
526 __be16 proto
, u16 vid
)
528 struct fe_priv
*priv
= netdev_priv(dev
);
529 u32 idx
= (vid
& 0xf);
532 if (!((fe_reg_table
[FE_REG_FE_DMA_VID_BASE
]) &&
533 (dev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)))
536 if (test_bit(idx
, &priv
->vlan_map
)) {
537 netdev_warn(dev
, "disable tx vlan offload\n");
538 dev
->wanted_features
&= ~NETIF_F_HW_VLAN_CTAG_TX
;
539 netdev_update_features(dev
);
541 vlan_cfg
= fe_r32(fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
545 vlan_cfg
|= (vid
<< 16);
547 vlan_cfg
&= 0xffff0000;
550 fe_w32(vlan_cfg
, fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
552 set_bit(idx
, &priv
->vlan_map
);
558 static int fe_vlan_rx_kill_vid(struct net_device
*dev
,
559 __be16 proto
, u16 vid
)
561 struct fe_priv
*priv
= netdev_priv(dev
);
562 u32 idx
= (vid
& 0xf);
564 if (!((fe_reg_table
[FE_REG_FE_DMA_VID_BASE
]) &&
565 (dev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)))
568 clear_bit(idx
, &priv
->vlan_map
);
573 static inline u32
fe_empty_txd(struct fe_tx_ring
*ring
)
576 return (u32
)(ring
->tx_ring_size
-
577 ((ring
->tx_next_idx
- ring
->tx_free_idx
) &
578 (ring
->tx_ring_size
- 1)));
581 struct fe_map_state
{
583 struct fe_tx_dma txd
;
589 static void fe_tx_dma_write_desc(struct fe_tx_ring
*ring
, struct fe_map_state
*st
)
591 fe_set_txd(&st
->txd
, &ring
->tx_dma
[st
->ring_idx
]);
592 memset(&st
->txd
, 0, sizeof(st
->txd
));
593 st
->txd
.txd4
= st
->def_txd4
;
594 st
->ring_idx
= NEXT_TX_DESP_IDX(st
->ring_idx
);
597 static int __fe_tx_dma_map_page(struct fe_tx_ring
*ring
, struct fe_map_state
*st
,
598 struct page
*page
, size_t offset
, size_t size
)
600 struct device
*dev
= st
->dev
;
601 struct fe_tx_buf
*tx_buf
;
602 dma_addr_t mapped_addr
;
604 mapped_addr
= dma_map_page(dev
, page
, offset
, size
, DMA_TO_DEVICE
);
605 if (unlikely(dma_mapping_error(dev
, mapped_addr
)))
608 if (st
->i
&& !(st
->i
& 1))
609 fe_tx_dma_write_desc(ring
, st
);
611 tx_buf
= &ring
->tx_buf
[st
->ring_idx
];
613 st
->txd
.txd3
= mapped_addr
;
614 st
->txd
.txd2
|= TX_DMA_PLEN1(size
);
615 dma_unmap_addr_set(tx_buf
, dma_addr1
, mapped_addr
);
616 dma_unmap_len_set(tx_buf
, dma_len1
, size
);
618 tx_buf
->skb
= (struct sk_buff
*)DMA_DUMMY_DESC
;
619 st
->txd
.txd1
= mapped_addr
;
620 st
->txd
.txd2
= TX_DMA_PLEN0(size
);
621 dma_unmap_addr_set(tx_buf
, dma_addr0
, mapped_addr
);
622 dma_unmap_len_set(tx_buf
, dma_len0
, size
);
629 static int fe_tx_dma_map_page(struct fe_tx_ring
*ring
, struct fe_map_state
*st
,
630 struct page
*page
, size_t offset
, size_t size
)
636 cur_size
= min_t(size_t, size
, TX_DMA_BUF_LEN
);
638 ret
= __fe_tx_dma_map_page(ring
, st
, page
, offset
, cur_size
);
649 static int fe_tx_dma_map_skb(struct fe_tx_ring
*ring
, struct fe_map_state
*st
,
652 struct page
*page
= virt_to_page(skb
->data
);
653 size_t offset
= offset_in_page(skb
->data
);
654 size_t size
= skb_headlen(skb
);
656 return fe_tx_dma_map_page(ring
, st
, page
, offset
, size
);
659 static inline struct sk_buff
*
660 fe_next_frag(struct sk_buff
*head
, struct sk_buff
*skb
)
665 if (skb_has_frag_list(skb
))
666 return skb_shinfo(skb
)->frag_list
;
672 static int fe_tx_map_dma(struct sk_buff
*skb
, struct net_device
*dev
,
673 int tx_num
, struct fe_tx_ring
*ring
)
675 struct fe_priv
*priv
= netdev_priv(dev
);
676 struct fe_map_state st
= {
678 .ring_idx
= ring
->tx_next_idx
,
680 struct sk_buff
*head
= skb
;
681 struct fe_tx_buf
*tx_buf
;
682 unsigned int nr_frags
;
685 /* init tx descriptor */
686 if (priv
->soc
->tx_dma
)
687 priv
->soc
->tx_dma(&st
.txd
);
689 st
.txd
.txd4
= TX_DMA_DESP4_DEF
;
690 st
.def_txd4
= st
.txd
.txd4
;
692 /* TX Checksum offload */
693 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
694 st
.txd
.txd4
|= TX_DMA_CHKSUM
;
696 /* VLAN header offload */
697 if (skb_vlan_tag_present(skb
)) {
698 u16 tag
= skb_vlan_tag_get(skb
);
700 if (IS_ENABLED(CONFIG_SOC_MT7621
))
701 st
.txd
.txd4
|= TX_DMA_INS_VLAN_MT7621
| tag
;
703 st
.txd
.txd4
|= TX_DMA_INS_VLAN
|
704 ((tag
>> VLAN_PRIO_SHIFT
) << 4) |
708 /* TSO: fill MSS info in tcp checksum field */
709 if (skb_is_gso(skb
)) {
710 if (skb_cow_head(skb
, 0)) {
711 netif_warn(priv
, tx_err
, dev
,
712 "GSO expand head fail.\n");
715 if (skb_shinfo(skb
)->gso_type
&
716 (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
717 st
.txd
.txd4
|= TX_DMA_TSO
;
718 tcp_hdr(skb
)->check
= htons(skb_shinfo(skb
)->gso_size
);
723 if (skb_headlen(skb
) && fe_tx_dma_map_skb(ring
, &st
, skb
))
727 nr_frags
= skb_shinfo(skb
)->nr_frags
;
728 for (i
= 0; i
< nr_frags
; i
++) {
731 frag
= &skb_shinfo(skb
)->frags
[i
];
732 if (fe_tx_dma_map_page(ring
, &st
, skb_frag_page(frag
),
733 skb_frag_off(frag
), skb_frag_size(frag
)))
737 skb
= fe_next_frag(head
, skb
);
741 /* set last segment */
743 st
.txd
.txd2
|= TX_DMA_LS0
;
745 st
.txd
.txd2
|= TX_DMA_LS1
;
747 /* store skb to cleanup */
748 tx_buf
= &ring
->tx_buf
[st
.ring_idx
];
751 netdev_sent_queue(dev
, head
->len
);
752 skb_tx_timestamp(head
);
754 fe_tx_dma_write_desc(ring
, &st
);
755 ring
->tx_next_idx
= st
.ring_idx
;
757 /* make sure that all changes to the dma ring are flushed before we
761 if (unlikely(fe_empty_txd(ring
) <= ring
->tx_thresh
)) {
762 netif_stop_queue(dev
);
764 if (unlikely(fe_empty_txd(ring
) > ring
->tx_thresh
))
765 netif_wake_queue(dev
);
768 if (netif_xmit_stopped(netdev_get_tx_queue(dev
, 0)) || !netdev_xmit_more())
769 fe_reg_w32(ring
->tx_next_idx
, FE_REG_TX_CTX_IDX0
);
774 j
= ring
->tx_next_idx
;
775 for (i
= 0; i
< tx_num
; i
++) {
777 fe_txd_unmap(priv
->dev
, &ring
->tx_buf
[j
]);
778 ring
->tx_dma
[j
].txd2
= TX_DMA_DESP2_DEF
;
780 j
= NEXT_TX_DESP_IDX(j
);
782 /* make sure that all changes to the dma ring are flushed before we
791 static inline int fe_skb_padto(struct sk_buff
*skb
, struct fe_priv
*priv
)
797 if (unlikely(skb
->len
< VLAN_ETH_ZLEN
)) {
798 if ((priv
->flags
& FE_FLAG_PADDING_64B
) &&
799 !(priv
->flags
& FE_FLAG_PADDING_BUG
))
802 if (skb_vlan_tag_present(skb
))
804 else if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
))
806 else if (!(priv
->flags
& FE_FLAG_PADDING_64B
))
811 if (skb
->len
< len
) {
812 ret
= skb_pad(skb
, len
- skb
->len
);
816 skb_set_tail_pointer(skb
, len
);
823 static inline int fe_cal_txd_req(struct sk_buff
*skb
)
825 struct sk_buff
*head
= skb
;
831 if (skb_is_gso(skb
)) {
832 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
833 frag
= &skb_shinfo(skb
)->frags
[i
];
834 nfrags
+= DIV_ROUND_UP(skb_frag_size(frag
), TX_DMA_BUF_LEN
);
837 nfrags
+= skb_shinfo(skb
)->nr_frags
;
840 skb
= fe_next_frag(head
, skb
);
844 return DIV_ROUND_UP(nfrags
, 2);
847 static int fe_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
849 struct fe_priv
*priv
= netdev_priv(dev
);
850 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
851 struct net_device_stats
*stats
= &dev
->stats
;
855 if (fe_skb_padto(skb
, priv
)) {
856 netif_warn(priv
, tx_err
, dev
, "tx padding failed!\n");
860 tx_num
= fe_cal_txd_req(skb
);
861 if (unlikely(fe_empty_txd(ring
) <= tx_num
)) {
862 netif_stop_queue(dev
);
863 netif_err(priv
, tx_queued
, dev
,
864 "Tx Ring full when queue awake!\n");
865 return NETDEV_TX_BUSY
;
868 if (fe_tx_map_dma(skb
, dev
, tx_num
, ring
) < 0) {
872 stats
->tx_bytes
+= len
;
878 static int fe_poll_rx(struct napi_struct
*napi
, int budget
,
879 struct fe_priv
*priv
, u32 rx_intr
)
881 struct net_device
*netdev
= priv
->netdev
;
882 struct net_device_stats
*stats
= &netdev
->stats
;
883 struct fe_soc_data
*soc
= priv
->soc
;
884 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
885 int idx
= ring
->rx_calc_idx
;
889 struct fe_rx_dma
*rxd
, trxd
;
892 if (netdev
->features
& NETIF_F_RXCSUM
)
893 checksum_bit
= soc
->checksum_bit
;
897 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
902 while (done
< budget
) {
906 idx
= NEXT_RX_DESP_IDX(idx
);
907 rxd
= &ring
->rx_dma
[idx
];
908 data
= ring
->rx_data
[idx
];
910 fe_get_rxd(&trxd
, rxd
);
911 if (!(trxd
.rxd2
& RX_DMA_DONE
))
914 /* alloc new buffer */
915 new_data
= page_frag_alloc(&ring
->frag_cache
, ring
->frag_size
,
917 if (unlikely(!new_data
)) {
921 dma_addr
= dma_map_single(priv
->dev
,
922 new_data
+ NET_SKB_PAD
+ pad
,
925 if (unlikely(dma_mapping_error(priv
->dev
, dma_addr
))) {
926 skb_free_frag(new_data
);
931 skb
= build_skb(data
, ring
->frag_size
);
932 if (unlikely(!skb
)) {
933 skb_free_frag(new_data
);
936 skb_reserve(skb
, NET_SKB_PAD
+ NET_IP_ALIGN
);
938 dma_unmap_single(priv
->dev
, trxd
.rxd1
,
939 ring
->rx_buf_size
, DMA_FROM_DEVICE
);
940 pktlen
= RX_DMA_GET_PLEN0(trxd
.rxd2
);
942 skb_put(skb
, pktlen
);
943 if (trxd
.rxd4
& checksum_bit
)
944 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
946 skb_checksum_none_assert(skb
);
947 skb
->protocol
= eth_type_trans(skb
, netdev
);
949 if (netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
&&
950 RX_DMA_VID(trxd
.rxd3
))
951 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
),
952 RX_DMA_VID(trxd
.rxd3
));
955 stats
->rx_bytes
+= pktlen
;
957 napi_gro_receive(napi
, skb
);
959 ring
->rx_data
[idx
] = new_data
;
960 rxd
->rxd1
= (unsigned int)dma_addr
;
963 if (priv
->flags
& FE_FLAG_RX_SG_DMA
)
964 rxd
->rxd2
= RX_DMA_PLEN0(ring
->rx_buf_size
);
966 rxd
->rxd2
= RX_DMA_LSO
;
968 ring
->rx_calc_idx
= idx
;
969 /* make sure that all changes to the dma ring are flushed before
973 fe_reg_w32(ring
->rx_calc_idx
, FE_REG_RX_CALC_IDX0
);
978 fe_reg_w32(rx_intr
, FE_REG_FE_INT_STATUS
);
983 static int fe_poll_tx(struct fe_priv
*priv
, int budget
, u32 tx_intr
,
986 struct net_device
*netdev
= priv
->netdev
;
987 unsigned int bytes_compl
= 0;
989 struct fe_tx_buf
*tx_buf
;
992 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
994 idx
= ring
->tx_free_idx
;
995 hwidx
= fe_reg_r32(FE_REG_TX_DTX_IDX0
);
997 while ((idx
!= hwidx
) && budget
) {
998 tx_buf
= &ring
->tx_buf
[idx
];
1004 if (skb
!= (struct sk_buff
*)DMA_DUMMY_DESC
) {
1005 bytes_compl
+= skb
->len
;
1009 fe_txd_unmap(priv
->dev
, tx_buf
);
1010 idx
= NEXT_TX_DESP_IDX(idx
);
1012 ring
->tx_free_idx
= idx
;
1015 /* read hw index again make sure no new tx packet */
1016 hwidx
= fe_reg_r32(FE_REG_TX_DTX_IDX0
);
1018 fe_reg_w32(tx_intr
, FE_REG_FE_INT_STATUS
);
1026 netdev_completed_queue(netdev
, done
, bytes_compl
);
1028 if (unlikely(netif_queue_stopped(netdev
) &&
1029 (fe_empty_txd(ring
) > ring
->tx_thresh
)))
1030 netif_wake_queue(netdev
);
1036 static int fe_poll(struct napi_struct
*napi
, int budget
)
1038 struct fe_priv
*priv
= container_of(napi
, struct fe_priv
, rx_napi
);
1039 struct fe_hw_stats
*hwstat
= priv
->hw_stats
;
1040 int tx_done
, rx_done
, tx_again
;
1041 u32 status
, fe_status
, status_reg
, mask
;
1042 u32 tx_intr
, rx_intr
, status_intr
;
1044 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1046 tx_intr
= priv
->soc
->tx_int
;
1047 rx_intr
= priv
->soc
->rx_int
;
1048 status_intr
= priv
->soc
->status_int
;
1053 if (fe_reg_table
[FE_REG_FE_INT_STATUS2
]) {
1054 fe_status
= fe_reg_r32(FE_REG_FE_INT_STATUS2
);
1055 status_reg
= FE_REG_FE_INT_STATUS2
;
1057 status_reg
= FE_REG_FE_INT_STATUS
;
1060 if (status
& tx_intr
)
1061 tx_done
= fe_poll_tx(priv
, budget
, tx_intr
, &tx_again
);
1063 if (status
& rx_intr
)
1064 rx_done
= fe_poll_rx(napi
, budget
, priv
, rx_intr
);
1066 if (unlikely(fe_status
& status_intr
)) {
1067 if (hwstat
&& spin_trylock(&hwstat
->stats_lock
)) {
1068 fe_stats_update(priv
);
1069 spin_unlock(&hwstat
->stats_lock
);
1071 fe_reg_w32(status_intr
, status_reg
);
1074 if (unlikely(netif_msg_intr(priv
))) {
1075 mask
= fe_reg_r32(FE_REG_FE_INT_ENABLE
);
1076 netdev_info(priv
->netdev
,
1077 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1078 tx_done
, rx_done
, status
, mask
);
1081 if (!tx_again
&& (rx_done
< budget
)) {
1082 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1083 if (status
& (tx_intr
| rx_intr
)) {
1084 /* let napi poll again */
1089 napi_complete_done(napi
, rx_done
);
1090 fe_int_enable(tx_intr
| rx_intr
);
1099 #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)
1100 static void fe_tx_timeout(struct net_device
*dev
)
1102 static void fe_tx_timeout(struct net_device
*dev
, unsigned int txqueue
)
1105 struct fe_priv
*priv
= netdev_priv(dev
);
1106 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
1108 priv
->netdev
->stats
.tx_errors
++;
1109 netif_err(priv
, tx_err
, dev
,
1110 "transmit timed out\n");
1111 netif_info(priv
, drv
, dev
, "dma_cfg:%08x\n",
1112 fe_reg_r32(FE_REG_PDMA_GLO_CFG
));
1113 netif_info(priv
, drv
, dev
, "tx_ring=%d, "
1114 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1115 0, fe_reg_r32(FE_REG_TX_BASE_PTR0
),
1116 fe_reg_r32(FE_REG_TX_MAX_CNT0
),
1117 fe_reg_r32(FE_REG_TX_CTX_IDX0
),
1118 fe_reg_r32(FE_REG_TX_DTX_IDX0
),
1121 netif_info(priv
, drv
, dev
,
1122 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1123 0, fe_reg_r32(FE_REG_RX_BASE_PTR0
),
1124 fe_reg_r32(FE_REG_RX_MAX_CNT0
),
1125 fe_reg_r32(FE_REG_RX_CALC_IDX0
),
1126 fe_reg_r32(FE_REG_RX_DRX_IDX0
));
1128 if (!test_and_set_bit(FE_FLAG_RESET_PENDING
, priv
->pending_flags
))
1129 schedule_work(&priv
->pending_work
);
1132 static irqreturn_t
fe_handle_irq(int irq
, void *dev
)
1134 struct fe_priv
*priv
= netdev_priv(dev
);
1135 u32 status
, int_mask
;
1137 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1139 if (unlikely(!status
))
1142 int_mask
= (priv
->soc
->rx_int
| priv
->soc
->tx_int
);
1143 if (likely(status
& int_mask
)) {
1144 if (likely(napi_schedule_prep(&priv
->rx_napi
))) {
1145 fe_int_disable(int_mask
);
1146 __napi_schedule(&priv
->rx_napi
);
1149 fe_reg_w32(status
, FE_REG_FE_INT_STATUS
);
1155 #ifdef CONFIG_NET_POLL_CONTROLLER
1156 static void fe_poll_controller(struct net_device
*dev
)
1158 struct fe_priv
*priv
= netdev_priv(dev
);
1159 u32 int_mask
= priv
->soc
->tx_int
| priv
->soc
->rx_int
;
1161 fe_int_disable(int_mask
);
1162 fe_handle_irq(dev
->irq
, dev
);
1163 fe_int_enable(int_mask
);
1167 int fe_set_clock_cycle(struct fe_priv
*priv
)
1169 unsigned long sysclk
= priv
->sysclk
;
1171 sysclk
/= FE_US_CYC_CNT_DIVISOR
;
1172 sysclk
<<= FE_US_CYC_CNT_SHIFT
;
1174 fe_w32((fe_r32(FE_FE_GLO_CFG
) &
1175 ~(FE_US_CYC_CNT_MASK
<< FE_US_CYC_CNT_SHIFT
)) |
1181 void fe_fwd_config(struct fe_priv
*priv
)
1185 fwd_cfg
= fe_r32(FE_GDMA1_FWD_CFG
);
1187 /* disable jumbo frame */
1188 if (priv
->flags
& FE_FLAG_JUMBO_FRAME
)
1189 fwd_cfg
&= ~FE_GDM1_JMB_EN
;
1191 /* set unicast/multicast/broadcast frame to cpu */
1194 fe_w32(fwd_cfg
, FE_GDMA1_FWD_CFG
);
1197 static void fe_rxcsum_config(bool enable
)
1200 fe_w32(fe_r32(FE_GDMA1_FWD_CFG
) | (FE_GDM1_ICS_EN
|
1201 FE_GDM1_TCS_EN
| FE_GDM1_UCS_EN
),
1204 fe_w32(fe_r32(FE_GDMA1_FWD_CFG
) & ~(FE_GDM1_ICS_EN
|
1205 FE_GDM1_TCS_EN
| FE_GDM1_UCS_EN
),
1209 static void fe_txcsum_config(bool enable
)
1212 fe_w32(fe_r32(FE_CDMA_CSG_CFG
) | (FE_ICS_GEN_EN
|
1213 FE_TCS_GEN_EN
| FE_UCS_GEN_EN
),
1216 fe_w32(fe_r32(FE_CDMA_CSG_CFG
) & ~(FE_ICS_GEN_EN
|
1217 FE_TCS_GEN_EN
| FE_UCS_GEN_EN
),
1221 void fe_csum_config(struct fe_priv
*priv
)
1223 struct net_device
*dev
= priv_netdev(priv
);
1225 fe_txcsum_config((dev
->features
& NETIF_F_IP_CSUM
));
1226 fe_rxcsum_config((dev
->features
& NETIF_F_RXCSUM
));
1229 static int fe_hw_init(struct net_device
*dev
)
1231 struct fe_priv
*priv
= netdev_priv(dev
);
1234 err
= devm_request_irq(priv
->dev
, dev
->irq
, fe_handle_irq
, 0,
1235 dev_name(priv
->dev
), dev
);
1239 if (priv
->soc
->set_mac
)
1240 priv
->soc
->set_mac(priv
, dev
->dev_addr
);
1242 fe_hw_set_macaddr(priv
, dev
->dev_addr
);
1244 /* disable delay interrupt */
1245 fe_reg_w32(0, FE_REG_DLY_INT_CFG
);
1247 fe_int_disable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1249 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1250 if (fe_reg_table
[FE_REG_FE_DMA_VID_BASE
])
1251 for (i
= 0; i
< 16; i
+= 2)
1252 fe_w32(((i
+ 1) << 16) + i
,
1253 fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
1256 if (priv
->soc
->fwd_config(priv
))
1257 netdev_err(dev
, "unable to get clock\n");
1259 if (fe_reg_table
[FE_REG_FE_RST_GL
]) {
1260 fe_reg_w32(1, FE_REG_FE_RST_GL
);
1261 fe_reg_w32(0, FE_REG_FE_RST_GL
);
1267 static int fe_open(struct net_device
*dev
)
1269 struct fe_priv
*priv
= netdev_priv(dev
);
1270 unsigned long flags
;
1274 err
= fe_init_dma(priv
);
1280 spin_lock_irqsave(&priv
->page_lock
, flags
);
1282 val
= FE_TX_WB_DDONE
| FE_RX_DMA_EN
| FE_TX_DMA_EN
;
1283 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
1284 val
|= FE_RX_2B_OFFSET
;
1285 val
|= priv
->soc
->pdma_glo_cfg
;
1286 fe_reg_w32(val
, FE_REG_PDMA_GLO_CFG
);
1288 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
1291 priv
->phy
->start(priv
);
1293 if (priv
->soc
->has_carrier
&& priv
->soc
->has_carrier(priv
))
1294 netif_carrier_on(dev
);
1296 napi_enable(&priv
->rx_napi
);
1297 fe_int_enable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1298 netif_start_queue(dev
);
1303 static int fe_stop(struct net_device
*dev
)
1305 struct fe_priv
*priv
= netdev_priv(dev
);
1306 unsigned long flags
;
1309 netif_tx_disable(dev
);
1310 fe_int_disable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1311 napi_disable(&priv
->rx_napi
);
1314 priv
->phy
->stop(priv
);
1316 spin_lock_irqsave(&priv
->page_lock
, flags
);
1318 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG
) &
1319 ~(FE_TX_WB_DDONE
| FE_RX_DMA_EN
| FE_TX_DMA_EN
),
1320 FE_REG_PDMA_GLO_CFG
);
1321 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
1324 for (i
= 0; i
< 10; i
++) {
1325 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG
) &
1326 (FE_TX_DMA_BUSY
| FE_RX_DMA_BUSY
)) {
1338 static void fe_reset_phy(struct fe_priv
*priv
)
1341 struct gpio_desc
*phy_reset
;
1343 phy_reset
= devm_gpiod_get_optional(priv
->dev
, "phy-reset",
1348 if (IS_ERR(phy_reset
)) {
1349 dev_err(priv
->dev
, "Error acquiring reset gpio pins: %ld\n",
1350 PTR_ERR(phy_reset
));
1354 err
= of_property_read_u32(priv
->dev
->of_node
, "phy-reset-duration",
1356 if (!err
&& msec
> 1000)
1362 usleep_range(msec
* 1000, msec
* 1000 + 1000);
1364 gpiod_set_value(phy_reset
, 0);
1367 static int __init
fe_init(struct net_device
*dev
)
1369 struct fe_priv
*priv
= netdev_priv(dev
);
1370 struct device_node
*port
;
1371 const char *mac_addr
;
1374 if (priv
->soc
->reset_fe
)
1375 priv
->soc
->reset_fe(priv
);
1379 if (priv
->soc
->switch_init
)
1380 if (priv
->soc
->switch_init(priv
)) {
1381 netdev_err(dev
, "failed to initialize switch core\n");
1387 mac_addr
= of_get_mac_address(priv
->dev
->of_node
);
1388 if (!IS_ERR_OR_NULL(mac_addr
))
1389 ether_addr_copy(dev
->dev_addr
, mac_addr
);
1391 /* If the mac address is invalid, use random mac address */
1392 if (!is_valid_ether_addr(dev
->dev_addr
)) {
1393 eth_hw_addr_random(dev
);
1394 dev_err(priv
->dev
, "generated random MAC address %pM\n",
1398 err
= fe_mdio_init(priv
);
1402 if (priv
->soc
->port_init
)
1403 for_each_child_of_node(priv
->dev
->of_node
, port
)
1404 if (of_device_is_compatible(port
, "mediatek,eth-port") &&
1405 of_device_is_available(port
))
1406 priv
->soc
->port_init(priv
, port
);
1409 err
= priv
->phy
->connect(priv
);
1411 goto err_phy_disconnect
;
1414 err
= fe_hw_init(dev
);
1416 goto err_phy_disconnect
;
1418 if ((priv
->flags
& FE_FLAG_HAS_SWITCH
) && priv
->soc
->switch_config
)
1419 priv
->soc
->switch_config(priv
);
1425 priv
->phy
->disconnect(priv
);
1426 fe_mdio_cleanup(priv
);
1431 static void fe_uninit(struct net_device
*dev
)
1433 struct fe_priv
*priv
= netdev_priv(dev
);
1436 priv
->phy
->disconnect(priv
);
1437 fe_mdio_cleanup(priv
);
1439 fe_reg_w32(0, FE_REG_FE_INT_ENABLE
);
1440 free_irq(dev
->irq
, dev
);
1443 static int fe_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1445 struct fe_priv
*priv
= netdev_priv(dev
);
1451 return phy_mii_ioctl(priv
->phy_dev
, ifr
, cmd
);
1454 static int fe_change_mtu(struct net_device
*dev
, int new_mtu
)
1456 struct fe_priv
*priv
= netdev_priv(dev
);
1457 int frag_size
, old_mtu
;
1463 if (!(priv
->flags
& FE_FLAG_JUMBO_FRAME
))
1466 /* return early if the buffer sizes will not change */
1467 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
1469 if (old_mtu
> ETH_DATA_LEN
&& new_mtu
> ETH_DATA_LEN
)
1472 if (new_mtu
<= ETH_DATA_LEN
)
1473 priv
->rx_ring
.frag_size
= fe_max_frag_size(ETH_DATA_LEN
);
1475 priv
->rx_ring
.frag_size
= PAGE_SIZE
;
1476 priv
->rx_ring
.rx_buf_size
= fe_max_buf_size(priv
->rx_ring
.frag_size
);
1478 if (!netif_running(dev
))
1482 if (!IS_ENABLED(CONFIG_SOC_MT7621
)) {
1483 fwd_cfg
= fe_r32(FE_GDMA1_FWD_CFG
);
1484 if (new_mtu
<= ETH_DATA_LEN
) {
1485 fwd_cfg
&= ~FE_GDM1_JMB_EN
;
1487 frag_size
= fe_max_frag_size(new_mtu
);
1488 fwd_cfg
&= ~(FE_GDM1_JMB_LEN_MASK
<< FE_GDM1_JMB_LEN_SHIFT
);
1489 fwd_cfg
|= (DIV_ROUND_UP(frag_size
, 1024) <<
1490 FE_GDM1_JMB_LEN_SHIFT
) | FE_GDM1_JMB_EN
;
1492 fe_w32(fwd_cfg
, FE_GDMA1_FWD_CFG
);
1495 return fe_open(dev
);
1498 static const struct net_device_ops fe_netdev_ops
= {
1499 .ndo_init
= fe_init
,
1500 .ndo_uninit
= fe_uninit
,
1501 .ndo_open
= fe_open
,
1502 .ndo_stop
= fe_stop
,
1503 .ndo_start_xmit
= fe_start_xmit
,
1504 .ndo_set_mac_address
= fe_set_mac_address
,
1505 .ndo_validate_addr
= eth_validate_addr
,
1506 .ndo_do_ioctl
= fe_do_ioctl
,
1507 .ndo_change_mtu
= fe_change_mtu
,
1508 .ndo_tx_timeout
= fe_tx_timeout
,
1509 .ndo_get_stats64
= fe_get_stats64
,
1510 .ndo_vlan_rx_add_vid
= fe_vlan_rx_add_vid
,
1511 .ndo_vlan_rx_kill_vid
= fe_vlan_rx_kill_vid
,
1512 #ifdef CONFIG_NET_POLL_CONTROLLER
1513 .ndo_poll_controller
= fe_poll_controller
,
1517 static void fe_reset_pending(struct fe_priv
*priv
)
1519 struct net_device
*dev
= priv
->netdev
;
1527 netif_alert(priv
, ifup
, dev
,
1528 "Driver up/down cycle failed, closing device.\n");
1534 static const struct fe_work_t fe_work
[] = {
1535 {FE_FLAG_RESET_PENDING
, fe_reset_pending
},
1538 static void fe_pending_work(struct work_struct
*work
)
1540 struct fe_priv
*priv
= container_of(work
, struct fe_priv
, pending_work
);
1544 for (i
= 0; i
< ARRAY_SIZE(fe_work
); i
++) {
1545 pending
= test_and_clear_bit(fe_work
[i
].bitnr
,
1546 priv
->pending_flags
);
1548 fe_work
[i
].action(priv
);
1552 static int fe_probe(struct platform_device
*pdev
)
1554 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1555 const struct of_device_id
*match
;
1556 struct fe_soc_data
*soc
;
1557 struct net_device
*netdev
;
1558 struct fe_priv
*priv
;
1560 int err
, napi_weight
;
1562 device_reset(&pdev
->dev
);
1564 match
= of_match_device(of_fe_match
, &pdev
->dev
);
1565 soc
= (struct fe_soc_data
*)match
->data
;
1568 fe_reg_table
= soc
->reg_table
;
1570 soc
->reg_table
= fe_reg_table
;
1572 fe_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1573 if (IS_ERR(fe_base
)) {
1574 err
= -EADDRNOTAVAIL
;
1578 netdev
= alloc_etherdev(sizeof(*priv
));
1580 dev_err(&pdev
->dev
, "alloc_etherdev failed\n");
1585 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
1586 netdev
->netdev_ops
= &fe_netdev_ops
;
1587 netdev
->base_addr
= (unsigned long)fe_base
;
1589 netdev
->irq
= platform_get_irq(pdev
, 0);
1590 if (netdev
->irq
< 0) {
1591 dev_err(&pdev
->dev
, "no IRQ resource found\n");
1596 priv
= netdev_priv(netdev
);
1597 spin_lock_init(&priv
->page_lock
);
1598 priv
->rst_fe
= devm_reset_control_get(&pdev
->dev
, "fe");
1599 if (IS_ERR(priv
->rst_fe
))
1600 priv
->rst_fe
= NULL
;
1603 soc
->init_data(soc
, netdev
);
1604 netdev
->vlan_features
= netdev
->hw_features
&
1605 ~(NETIF_F_HW_VLAN_CTAG_TX
|
1606 NETIF_F_HW_VLAN_CTAG_RX
);
1607 netdev
->features
|= netdev
->hw_features
;
1609 if (IS_ENABLED(CONFIG_SOC_MT7621
))
1610 netdev
->max_mtu
= 2048;
1612 /* fake rx vlan filter func. to support tx vlan offload func */
1613 if (fe_reg_table
[FE_REG_FE_DMA_VID_BASE
])
1614 netdev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
1616 if (fe_reg_table
[FE_REG_FE_COUNTER_BASE
]) {
1617 priv
->hw_stats
= kzalloc(sizeof(*priv
->hw_stats
), GFP_KERNEL
);
1618 if (!priv
->hw_stats
) {
1622 spin_lock_init(&priv
->hw_stats
->stats_lock
);
1625 sysclk
= devm_clk_get(&pdev
->dev
, NULL
);
1626 if (!IS_ERR(sysclk
)) {
1627 priv
->sysclk
= clk_get_rate(sysclk
);
1628 } else if ((priv
->flags
& FE_FLAG_CALIBRATE_CLK
)) {
1629 dev_err(&pdev
->dev
, "this soc needs a clk for calibration\n");
1634 priv
->switch_np
= of_parse_phandle(pdev
->dev
.of_node
, "mediatek,switch", 0);
1635 if ((priv
->flags
& FE_FLAG_HAS_SWITCH
) && !priv
->switch_np
) {
1636 dev_err(&pdev
->dev
, "failed to read switch phandle\n");
1641 priv
->netdev
= netdev
;
1642 priv
->dev
= &pdev
->dev
;
1644 priv
->msg_enable
= netif_msg_init(fe_msg_level
, FE_DEFAULT_MSG_ENABLE
);
1645 priv
->rx_ring
.frag_size
= fe_max_frag_size(ETH_DATA_LEN
);
1646 priv
->rx_ring
.rx_buf_size
= fe_max_buf_size(priv
->rx_ring
.frag_size
);
1647 priv
->tx_ring
.tx_ring_size
= NUM_DMA_DESC
;
1648 priv
->rx_ring
.rx_ring_size
= NUM_DMA_DESC
;
1649 INIT_WORK(&priv
->pending_work
, fe_pending_work
);
1650 u64_stats_init(&priv
->hw_stats
->syncp
);
1653 if (priv
->flags
& FE_FLAG_NAPI_WEIGHT
) {
1655 priv
->tx_ring
.tx_ring_size
*= 4;
1656 priv
->rx_ring
.rx_ring_size
*= 4;
1658 netif_napi_add(netdev
, &priv
->rx_napi
, fe_poll
, napi_weight
);
1659 fe_set_ethtool_ops(netdev
);
1661 err
= register_netdev(netdev
);
1663 dev_err(&pdev
->dev
, "error bringing up device\n");
1667 platform_set_drvdata(pdev
, netdev
);
1669 netif_info(priv
, probe
, netdev
, "mediatek frame engine at 0x%08lx, irq %d\n",
1670 netdev
->base_addr
, netdev
->irq
);
1675 free_netdev(netdev
);
1677 devm_iounmap(&pdev
->dev
, fe_base
);
1682 static int fe_remove(struct platform_device
*pdev
)
1684 struct net_device
*dev
= platform_get_drvdata(pdev
);
1685 struct fe_priv
*priv
= netdev_priv(dev
);
1687 netif_napi_del(&priv
->rx_napi
);
1688 kfree(priv
->hw_stats
);
1690 cancel_work_sync(&priv
->pending_work
);
1692 unregister_netdev(dev
);
1694 platform_set_drvdata(pdev
, NULL
);
1699 static struct platform_driver fe_driver
= {
1701 .remove
= fe_remove
,
1703 .name
= "mtk_soc_eth",
1704 .owner
= THIS_MODULE
,
1705 .of_match_table
= of_fe_match
,
1709 module_platform_driver(fe_driver
);
1711 MODULE_LICENSE("GPL");
1712 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1713 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1714 MODULE_VERSION(MTK_FE_DRV_VERSION
);