1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
18 #include <linux/mii.h>
19 #include <linux/interrupt.h>
20 #include <linux/netdevice.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/phy.h>
23 #include <linux/ethtool.h>
26 FE_REG_PDMA_GLO_CFG
= 0,
39 FE_REG_FE_DMA_VID_BASE
,
40 FE_REG_FE_COUNTER_BASE
,
42 FE_REG_FE_INT_STATUS2
,
47 FE_FLAG_RESET_PENDING
,
51 #define MTK_FE_DRV_VERSION "0.2"
53 /* power of 2 to let NEXT_TX_DESP_IDX work */
54 #define NUM_DMA_DESC BIT(10)
55 #define MAX_DMA_DESC 0xfff
57 #define FE_DELAY_EN_INT 0x80
58 #define FE_DELAY_MAX_INT 0x04
59 #define FE_DELAY_MAX_TOUT 0x04
60 #define FE_DELAY_TIME 20
61 #define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | \
63 #define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
64 #define FE_PSE_FQFC_CFG_INIT 0x80504000
65 #define FE_PSE_FQFC_CFG_256Q 0xff908000
68 #define FE_CNT_PPE_AF BIT(31)
69 #define FE_CNT_GDM_AF BIT(29)
70 #define FE_PSE_P2_FC BIT(26)
71 #define FE_PSE_BUF_DROP BIT(24)
72 #define FE_GDM_OTHER_DROP BIT(23)
73 #define FE_PSE_P1_FC BIT(22)
74 #define FE_PSE_P0_FC BIT(21)
75 #define FE_PSE_FQ_EMPTY BIT(20)
76 #define FE_GE1_STA_CHG BIT(18)
77 #define FE_TX_COHERENT BIT(17)
78 #define FE_RX_COHERENT BIT(16)
79 #define FE_TX_DONE_INT3 BIT(11)
80 #define FE_TX_DONE_INT2 BIT(10)
81 #define FE_TX_DONE_INT1 BIT(9)
82 #define FE_TX_DONE_INT0 BIT(8)
83 #define FE_RX_DONE_INT0 BIT(2)
84 #define FE_TX_DLY_INT BIT(1)
85 #define FE_RX_DLY_INT BIT(0)
87 #define FE_RX_DONE_INT FE_RX_DONE_INT0
88 #define FE_TX_DONE_INT (FE_TX_DONE_INT0 | FE_TX_DONE_INT1 | \
89 FE_TX_DONE_INT2 | FE_TX_DONE_INT3)
91 #define RT5350_RX_DLY_INT BIT(30)
92 #define RT5350_TX_DLY_INT BIT(28)
93 #define RT5350_RX_DONE_INT1 BIT(17)
94 #define RT5350_RX_DONE_INT0 BIT(16)
95 #define RT5350_TX_DONE_INT3 BIT(3)
96 #define RT5350_TX_DONE_INT2 BIT(2)
97 #define RT5350_TX_DONE_INT1 BIT(1)
98 #define RT5350_TX_DONE_INT0 BIT(0)
100 #define RT5350_RX_DONE_INT (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1)
101 #define RT5350_TX_DONE_INT (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \
102 RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3)
105 #define FE_FE_OFFSET 0x0000
106 #define FE_GDMA_OFFSET 0x0020
107 #define FE_PSE_OFFSET 0x0040
108 #define FE_GDMA2_OFFSET 0x0060
109 #define FE_CDMA_OFFSET 0x0080
110 #define FE_DMA_VID0 0x00a8
111 #define FE_PDMA_OFFSET 0x0100
112 #define FE_PPE_OFFSET 0x0200
113 #define FE_CMTABLE_OFFSET 0x0400
114 #define FE_POLICYTABLE_OFFSET 0x1000
116 #define RT5350_PDMA_OFFSET 0x0800
117 #define RT5350_SDM_OFFSET 0x0c00
119 #define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
120 #define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
121 #define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
122 #define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
123 #define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
124 #define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
125 #define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
126 #define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
128 #define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
129 #define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
130 #define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
131 #define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
132 #define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
134 #define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
135 #define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
136 #define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
137 #define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
138 #define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
140 #define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
141 #define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
142 #define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
143 #define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
145 #define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
146 #define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
148 #ifdef CONFIG_SOC_MT7621
149 #define MT7620A_GDMA_OFFSET 0x0500
151 #define MT7620A_GDMA_OFFSET 0x0600
153 #define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
154 #define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
155 #define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
156 #define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
157 #define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
159 #define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
160 #define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
161 #define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
162 #define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
163 #define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
164 #define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
165 #define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
166 #define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
167 #define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
168 #define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
169 #define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
170 #define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
171 #define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
172 #define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
173 #define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
174 #define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
175 #define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
176 #define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
177 #define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
178 #define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
179 #define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
180 #define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
181 #define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
182 #define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
183 #define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
184 #define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
185 #define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
186 #define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
187 #define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
188 #define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
190 #define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
191 #define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
192 #define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
193 #define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
194 #define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
195 #define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
196 #define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
197 #define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
198 #define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
199 #define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
200 #define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
201 #define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
202 #define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
203 #define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
204 #define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
205 #define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
206 #define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
207 #define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
208 #define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
209 #define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
210 #define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
211 #define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
212 #define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
213 #define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
214 #define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
215 #define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
216 #define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
217 #define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
219 /* Switch DMA configuration */
220 #define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00)
221 #define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04)
222 #define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08)
223 #define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C)
224 #define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10)
225 #define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100)
226 #define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104)
227 #define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108)
228 #define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C)
229 #define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110)
231 #define RT5350_SDM_ICS_EN BIT(16)
232 #define RT5350_SDM_TCS_EN BIT(17)
233 #define RT5350_SDM_UCS_EN BIT(18)
235 /* MDIO_CFG register bits */
236 #define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
237 #define FE_MDIO_CFG_GP1_BP_EN BIT(16)
238 #define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
239 #define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
240 #define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
241 #define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
242 #define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
243 #define FE_MDIO_CFG_GP1_FC_TX BIT(11)
244 #define FE_MDIO_CFG_GP1_FC_RX BIT(10)
245 #define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
246 #define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
247 #define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
248 #define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
249 #define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
250 #define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
251 #define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
252 #define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
253 #define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
254 #define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
255 #define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
256 #define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
257 #define FE_MDIO_CFG_TX_CLK_SKEW_0 0
258 #define FE_MDIO_CFG_TX_CLK_SKEW_200 1
259 #define FE_MDIO_CFG_TX_CLK_SKEW_400 2
260 #define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
263 #define FE_GDM1_JMB_LEN_MASK 0xf
264 #define FE_GDM1_JMB_LEN_SHIFT 28
265 #define FE_GDM1_ICS_EN BIT(22)
266 #define FE_GDM1_TCS_EN BIT(21)
267 #define FE_GDM1_UCS_EN BIT(20)
268 #define FE_GDM1_JMB_EN BIT(19)
269 #define FE_GDM1_STRPCRC BIT(16)
270 #define FE_GDM1_UFRC_P_CPU (0 << 12)
271 #define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
272 #define FE_GDM1_UFRC_P_PPE (6 << 12)
275 #define FE_ICS_GEN_EN BIT(2)
276 #define FE_UCS_GEN_EN BIT(1)
277 #define FE_TCS_GEN_EN BIT(0)
280 #define FE_PST_DRX_IDX0 BIT(16)
281 #define FE_PST_DTX_IDX3 BIT(3)
282 #define FE_PST_DTX_IDX2 BIT(2)
283 #define FE_PST_DTX_IDX1 BIT(1)
284 #define FE_PST_DTX_IDX0 BIT(0)
286 #define FE_RX_2B_OFFSET BIT(31)
287 #define FE_TX_WB_DDONE BIT(6)
288 #define FE_RX_DMA_BUSY BIT(3)
289 #define FE_TX_DMA_BUSY BIT(1)
290 #define FE_RX_DMA_EN BIT(2)
291 #define FE_TX_DMA_EN BIT(0)
293 #define FE_PDMA_SIZE_4DWORDS (0 << 4)
294 #define FE_PDMA_SIZE_8DWORDS (1 << 4)
295 #define FE_PDMA_SIZE_16DWORDS (2 << 4)
297 #define FE_US_CYC_CNT_MASK 0xff
298 #define FE_US_CYC_CNT_SHIFT 0x8
299 #define FE_US_CYC_CNT_DIVISOR 1000000
302 #define RX_DMA_DONE BIT(31)
303 #define RX_DMA_LSO BIT(30)
304 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
305 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
306 #define RX_DMA_TAG BIT(15)
308 #define RX_DMA_TPID(_x) (((_x) >> 16) & 0xffff)
309 #define RX_DMA_VID(_x) ((_x) & 0xffff)
311 #define RX_DMA_L4VALID BIT(30)
318 } __packed
__aligned(4);
320 #define TX_DMA_BUF_LEN 0x3fff
321 #define TX_DMA_PLEN0_MASK (TX_DMA_BUF_LEN << 16)
322 #define TX_DMA_PLEN0(_x) (((_x) & TX_DMA_BUF_LEN) << 16)
323 #define TX_DMA_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
324 #define TX_DMA_GET_PLEN0(_x) (((_x) >> 16) & TX_DMA_BUF_LEN)
325 #define TX_DMA_GET_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
326 #define TX_DMA_LS1 BIT(14)
327 #define TX_DMA_LS0 BIT(30)
328 #define TX_DMA_DONE BIT(31)
330 #define TX_DMA_INS_VLAN_MT7621 BIT(16)
331 #define TX_DMA_INS_VLAN BIT(7)
332 #define TX_DMA_INS_PPPOE BIT(12)
333 #define TX_DMA_QN(_x) ((_x) << 16)
334 #define TX_DMA_PN(_x) ((_x) << 24)
335 #define TX_DMA_QN_MASK TX_DMA_QN(0x7)
336 #define TX_DMA_PN_MASK TX_DMA_PN(0x7)
337 #define TX_DMA_UDF BIT(20)
338 #define TX_DMA_CHKSUM (0x7 << 29)
339 #define TX_DMA_TSO BIT(28)
341 /* frame engine counters */
342 #define FE_PPE_AC_BCNT0 (FE_CMTABLE_OFFSET + 0x00)
343 #define FE_GDMA1_TX_GBCNT (FE_CMTABLE_OFFSET + 0x300)
344 #define FE_GDMA2_TX_GBCNT (FE_GDMA1_TX_GBCNT + 0x40)
346 /* phy device flags */
347 #define FE_PHY_FLAG_PORT BIT(0)
348 #define FE_PHY_FLAG_ATTACH BIT(1)
355 } __packed
__aligned(4);
360 /* make sure that phy operations are atomic */
363 struct phy_device
*phy
[8];
364 struct device_node
*phy_node
[8];
365 const __be32
*phy_fixed
[8];
370 int (*connect
)(struct fe_priv
*priv
);
371 void (*disconnect
)(struct fe_priv
*priv
);
372 void (*start
)(struct fe_priv
*priv
);
373 void (*stop
)(struct fe_priv
*priv
);
377 const u16
*reg_table
;
379 void (*init_data
)(struct fe_soc_data
*data
, struct net_device
*netdev
);
380 void (*set_mac
)(struct fe_priv
*priv
, const unsigned char *mac
);
381 int (*fwd_config
)(struct fe_priv
*priv
);
382 void (*tx_dma
)(struct fe_tx_dma
*txd
);
383 int (*switch_init
)(struct fe_priv
*priv
);
384 int (*switch_config
)(struct fe_priv
*priv
);
385 void (*port_init
)(struct fe_priv
*priv
, struct device_node
*port
);
386 int (*has_carrier
)(struct fe_priv
*priv
);
387 int (*mdio_init
)(struct fe_priv
*priv
);
388 void (*mdio_cleanup
)(struct fe_priv
*priv
);
389 int (*mdio_write
)(struct mii_bus
*bus
, int phy_addr
, int phy_reg
,
391 int (*mdio_read
)(struct mii_bus
*bus
, int phy_addr
, int phy_reg
);
392 void (*mdio_adjust_link
)(struct fe_priv
*priv
, int port
);
402 #define FE_FLAG_PADDING_64B BIT(0)
403 #define FE_FLAG_PADDING_BUG BIT(1)
404 #define FE_FLAG_JUMBO_FRAME BIT(2)
405 #define FE_FLAG_RX_2B_OFFSET BIT(3)
406 #define FE_FLAG_RX_SG_DMA BIT(4)
407 #define FE_FLAG_NAPI_WEIGHT BIT(6)
408 #define FE_FLAG_CALIBRATE_CLK BIT(7)
409 #define FE_FLAG_HAS_SWITCH BIT(8)
411 #define FE_STAT_REG_DECLARE \
420 _FE(rx_short_errors) \
421 _FE(rx_long_errors) \
422 _FE(rx_checksum_errors) \
423 _FE(rx_flow_control_packets)
426 /* make sure that stats operations are atomic */
427 spinlock_t stats_lock
;
429 struct u64_stats_sync syncp
;
430 #define _FE(x) u64 x;
437 DEFINE_DMA_UNMAP_ADDR(dma_addr0
);
438 DEFINE_DMA_UNMAP_ADDR(dma_addr1
);
444 struct fe_tx_dma
*tx_dma
;
445 struct fe_tx_buf
*tx_buf
;
454 struct page_frag_cache frag_cache
;
455 struct fe_rx_dma
*rx_dma
;
465 /* make sure that register operations are atomic */
466 spinlock_t page_lock
;
468 struct fe_soc_data
*soc
;
469 struct net_device
*netdev
;
470 struct device_node
*switch_np
;
475 unsigned long sysclk
;
477 struct fe_rx_ring rx_ring
;
478 struct napi_struct rx_napi
;
480 struct fe_tx_ring tx_ring
;
483 struct mii_bus
*mii_bus
;
484 struct phy_device
*phy_dev
;
489 struct fe_hw_stats
*hw_stats
;
490 unsigned long vlan_map
;
491 struct work_struct pending_work
;
492 DECLARE_BITMAP(pending_flags
, FE_FLAG_MAX
);
494 struct reset_control
*resets
;
495 struct mtk_foe_entry
*foe_table
;
496 dma_addr_t foe_table_phys
;
497 struct flow_offload __rcu
**foe_flow_table
;
500 extern const struct of_device_id of_fe_match
[];
502 void fe_w32(u32 val
, unsigned reg
);
503 void fe_m32(struct fe_priv
*priv
, u32 clear
, u32 set
, unsigned reg
);
504 u32
fe_r32(unsigned reg
);
506 int fe_set_clock_cycle(struct fe_priv
*priv
);
507 void fe_csum_config(struct fe_priv
*priv
);
508 void fe_stats_update(struct fe_priv
*priv
);
509 void fe_fwd_config(struct fe_priv
*priv
);
510 void fe_reg_w32(u32 val
, enum fe_reg reg
);
511 u32
fe_reg_r32(enum fe_reg reg
);
513 static inline void *priv_netdev(struct fe_priv
*priv
)
515 return (char *)priv
- ALIGN(sizeof(struct net_device
), NETDEV_ALIGN
);
519 #endif /* FE_ETH_H */