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ralink: support netconsole
[openwrt/staging/dedeckeh.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
34 #include <linux/io.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "ralink_soc_eth.h"
39 #include "esw_rt3052.h"
40 #include "mdio.h"
41 #include "ralink_ethtool.h"
42
43 #define TX_TIMEOUT (2 * HZ)
44 #define MAX_RX_LENGTH 1536
45 #define FE_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
46 #define FE_RX_HLEN (FE_RX_OFFSET + VLAN_ETH_HLEN + VLAN_HLEN + \
47 ETH_FCS_LEN)
48 #define DMA_DUMMY_DESC 0xffffffff
49 #define FE_DEFAULT_MSG_ENABLE \
50 (NETIF_MSG_DRV | \
51 NETIF_MSG_PROBE | \
52 NETIF_MSG_LINK | \
53 NETIF_MSG_TIMER | \
54 NETIF_MSG_IFDOWN | \
55 NETIF_MSG_IFUP | \
56 NETIF_MSG_RX_ERR | \
57 NETIF_MSG_TX_ERR)
58
59 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
60 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
61 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
62 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
63
64 static int fe_msg_level = -1;
65 module_param_named(msg_level, fe_msg_level, int, 0);
66 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
67
68 static const u32 fe_reg_table_default[FE_REG_COUNT] = {
69 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
70 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
71 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
72 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
73 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
74 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
75 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
76 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
77 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
78 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
79 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
80 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
81 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
82 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
83 };
84
85 static const u32 *fe_reg_table = fe_reg_table_default;
86
87 static void __iomem *fe_base = 0;
88
89 void fe_w32(u32 val, unsigned reg)
90 {
91 __raw_writel(val, fe_base + reg);
92 }
93
94 u32 fe_r32(unsigned reg)
95 {
96 return __raw_readl(fe_base + reg);
97 }
98
99 void fe_reg_w32(u32 val, enum fe_reg reg)
100 {
101 fe_w32(val, fe_reg_table[reg]);
102 }
103
104 u32 fe_reg_r32(enum fe_reg reg)
105 {
106 return fe_r32(fe_reg_table[reg]);
107 }
108
109 static inline void fe_int_disable(u32 mask)
110 {
111 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
112 FE_REG_FE_INT_ENABLE);
113 /* flush write */
114 fe_reg_r32(FE_REG_FE_INT_ENABLE);
115 }
116
117 static inline void fe_int_enable(u32 mask)
118 {
119 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
120 FE_REG_FE_INT_ENABLE);
121 /* flush write */
122 fe_reg_r32(FE_REG_FE_INT_ENABLE);
123 }
124
125 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
126 {
127 unsigned long flags;
128
129 spin_lock_irqsave(&priv->page_lock, flags);
130 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
131 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
132 FE_GDMA1_MAC_ADRL);
133 spin_unlock_irqrestore(&priv->page_lock, flags);
134 }
135
136 static int fe_set_mac_address(struct net_device *dev, void *p)
137 {
138 int ret = eth_mac_addr(dev, p);
139
140 if (!ret) {
141 struct fe_priv *priv = netdev_priv(dev);
142
143 if (priv->soc->set_mac)
144 priv->soc->set_mac(priv, dev->dev_addr);
145 else
146 fe_hw_set_macaddr(priv, p);
147 }
148
149 return ret;
150 }
151
152 static inline int fe_max_frag_size(int mtu)
153 {
154 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
155 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
156 }
157
158 static inline int fe_max_buf_size(int frag_size)
159 {
160 return frag_size - FE_RX_HLEN -
161 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
162 }
163
164 static void fe_clean_rx(struct fe_priv *priv)
165 {
166 int i;
167
168 if (priv->rx_data) {
169 for (i = 0; i < NUM_DMA_DESC; i++)
170 if (priv->rx_data[i]) {
171 if (priv->rx_dma && priv->rx_dma[i].rxd1)
172 dma_unmap_single(&priv->netdev->dev,
173 priv->rx_dma[i].rxd1,
174 priv->rx_buf_size,
175 DMA_FROM_DEVICE);
176 put_page(virt_to_head_page(priv->rx_data[i]));
177 }
178
179 kfree(priv->rx_data);
180 priv->rx_data = NULL;
181 }
182
183 if (priv->rx_dma) {
184 dma_free_coherent(&priv->netdev->dev,
185 NUM_DMA_DESC * sizeof(*priv->rx_dma),
186 priv->rx_dma,
187 priv->rx_phys);
188 priv->rx_dma = NULL;
189 }
190 }
191
192 static int fe_alloc_rx(struct fe_priv *priv)
193 {
194 struct net_device *netdev = priv->netdev;
195 int i;
196
197 priv->rx_data = kcalloc(NUM_DMA_DESC, sizeof(*priv->rx_data),
198 GFP_KERNEL);
199 if (!priv->rx_data)
200 goto no_rx_mem;
201
202 for (i = 0; i < NUM_DMA_DESC; i++) {
203 priv->rx_data[i] = netdev_alloc_frag(priv->frag_size);
204 if (!priv->rx_data[i])
205 goto no_rx_mem;
206 }
207
208 priv->rx_dma = dma_alloc_coherent(&netdev->dev,
209 NUM_DMA_DESC * sizeof(*priv->rx_dma),
210 &priv->rx_phys,
211 GFP_ATOMIC | __GFP_ZERO);
212 if (!priv->rx_dma)
213 goto no_rx_mem;
214
215 for (i = 0; i < NUM_DMA_DESC; i++) {
216 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
217 priv->rx_data[i] + FE_RX_OFFSET,
218 priv->rx_buf_size,
219 DMA_FROM_DEVICE);
220 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
221 goto no_rx_mem;
222 priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
223
224 if (priv->soc->rx_dma)
225 priv->soc->rx_dma(priv, i, priv->rx_buf_size);
226 else
227 priv->rx_dma[i].rxd2 = RX_DMA_LSO;
228 }
229 wmb();
230
231 fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
232 fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
233 fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
234 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
235
236 return 0;
237
238 no_rx_mem:
239 return -ENOMEM;
240 }
241
242 static void fe_clean_tx(struct fe_priv *priv)
243 {
244 int i;
245
246 if (priv->tx_skb) {
247 for (i = 0; i < NUM_DMA_DESC; i++) {
248 if (priv->tx_skb[i])
249 dev_kfree_skb_any(priv->tx_skb[i]);
250 }
251 kfree(priv->tx_skb);
252 priv->tx_skb = NULL;
253 }
254
255 if (priv->tx_dma) {
256 dma_free_coherent(&priv->netdev->dev,
257 NUM_DMA_DESC * sizeof(*priv->tx_dma),
258 priv->tx_dma,
259 priv->tx_phys);
260 priv->tx_dma = NULL;
261 }
262 }
263
264 static int fe_alloc_tx(struct fe_priv *priv)
265 {
266 int i;
267
268 priv->tx_free_idx = 0;
269
270 priv->tx_skb = kcalloc(NUM_DMA_DESC, sizeof(*priv->tx_skb),
271 GFP_KERNEL);
272 if (!priv->tx_skb)
273 goto no_tx_mem;
274
275 priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
276 NUM_DMA_DESC * sizeof(*priv->tx_dma),
277 &priv->tx_phys,
278 GFP_ATOMIC | __GFP_ZERO);
279 if (!priv->tx_dma)
280 goto no_tx_mem;
281
282 for (i = 0; i < NUM_DMA_DESC; i++) {
283 if (priv->soc->tx_dma) {
284 priv->soc->tx_dma(priv, i, NULL);
285 continue;
286 }
287 priv->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
288 }
289 wmb();
290
291 fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
292 fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
293 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
294 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
295
296 return 0;
297
298 no_tx_mem:
299 return -ENOMEM;
300 }
301
302 static int fe_init_dma(struct fe_priv *priv)
303 {
304 int err;
305
306 err = fe_alloc_tx(priv);
307 if (err)
308 return err;
309
310 err = fe_alloc_rx(priv);
311 if (err)
312 return err;
313
314 return 0;
315 }
316
317 static void fe_free_dma(struct fe_priv *priv)
318 {
319 fe_clean_tx(priv);
320 fe_clean_rx(priv);
321
322 netdev_reset_queue(priv->netdev);
323 }
324
325 static inline void txd_unmap_single(struct device *dev, struct fe_tx_dma *txd)
326 {
327 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
328 dma_unmap_single(dev, txd->txd1,
329 TX_DMA_GET_PLEN0(txd->txd2),
330 DMA_TO_DEVICE);
331 }
332
333 static inline void txd_unmap_page0(struct device *dev, struct fe_tx_dma *txd)
334 {
335 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
336 dma_unmap_page(dev, txd->txd1,
337 TX_DMA_GET_PLEN0(txd->txd2),
338 DMA_TO_DEVICE);
339 }
340
341 static inline void txd_unmap_page1(struct device *dev, struct fe_tx_dma *txd)
342 {
343 if (txd->txd3 && TX_DMA_GET_PLEN1(txd->txd2))
344 dma_unmap_page(dev, txd->txd3,
345 TX_DMA_GET_PLEN1(txd->txd2),
346 DMA_TO_DEVICE);
347 }
348
349 void fe_stats_update(struct fe_priv *priv)
350 {
351 struct fe_hw_stats *hwstats = priv->hw_stats;
352 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
353
354 u64_stats_update_begin(&hwstats->syncp);
355
356 hwstats->tx_bytes += fe_r32(base);
357 hwstats->tx_packets += fe_r32(base + 0x04);
358 hwstats->tx_skip += fe_r32(base + 0x08);
359 hwstats->tx_collisions += fe_r32(base + 0x0c);
360 hwstats->rx_bytes += fe_r32(base + 0x20);
361 hwstats->rx_packets += fe_r32(base + 0x24);
362 hwstats->rx_overflow += fe_r32(base + 0x28);
363 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
364 hwstats->rx_short_errors += fe_r32(base + 0x30);
365 hwstats->rx_long_errors += fe_r32(base + 0x34);
366 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
367 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
368
369 u64_stats_update_end(&hwstats->syncp);
370 }
371
372 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
373 struct rtnl_link_stats64 *storage)
374 {
375 struct fe_priv *priv = netdev_priv(dev);
376 struct fe_hw_stats *hwstats = priv->hw_stats;
377 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
378 unsigned int start;
379
380 if (!base) {
381 netdev_stats_to_stats64(storage, &dev->stats);
382 return storage;
383 }
384
385 if (netif_running(dev) && netif_device_present(dev)) {
386 if (spin_trylock(&hwstats->stats_lock)) {
387 fe_stats_update(priv);
388 spin_unlock(&hwstats->stats_lock);
389 }
390 }
391
392 do {
393 start = u64_stats_fetch_begin_bh(&hwstats->syncp);
394 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
395 storage->rx_packets = dev->stats.rx_packets;
396 storage->tx_packets = dev->stats.tx_packets;
397 storage->rx_bytes = dev->stats.rx_bytes;
398 storage->tx_bytes = dev->stats.tx_bytes;
399 } else {
400 storage->rx_packets = dev->stats.rx_packets;
401 storage->tx_packets = dev->stats.tx_packets;
402 storage->rx_bytes = dev->stats.rx_bytes;
403 storage->tx_bytes = dev->stats.tx_bytes;
404 }
405 storage->collisions = hwstats->tx_collisions;
406 storage->rx_length_errors = hwstats->rx_short_errors +
407 hwstats->rx_long_errors;
408 storage->rx_over_errors = hwstats->rx_overflow;
409 storage->rx_crc_errors = hwstats->rx_fcs_errors;
410 storage->rx_errors = hwstats->rx_checksum_errors;
411 storage->tx_aborted_errors = hwstats->tx_skip;
412 } while (u64_stats_fetch_retry_bh(&hwstats->syncp, start));
413
414 storage->tx_errors = priv->netdev->stats.tx_errors;
415 storage->rx_dropped = priv->netdev->stats.rx_dropped;
416 storage->tx_dropped = priv->netdev->stats.tx_dropped;
417
418 return storage;
419 }
420
421 static int fe_vlan_rx_add_vid(struct net_device *dev,
422 __be16 proto, u16 vid)
423 {
424 struct fe_priv *priv = netdev_priv(dev);
425 u32 idx = (vid & 0xf);
426 u32 vlan_cfg;
427
428 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
429 (dev->features | NETIF_F_HW_VLAN_CTAG_TX)))
430 return 0;
431
432 if (test_bit(idx, &priv->vlan_map)) {
433 netdev_warn(dev, "disable tx vlan offload\n");
434 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
435 netdev_update_features(dev);
436 } else {
437 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
438 ((idx >> 1) << 2));
439 if (idx & 0x1) {
440 vlan_cfg &= 0xffff;
441 vlan_cfg |= (vid << 16);
442 } else {
443 vlan_cfg &= 0xffff0000;
444 vlan_cfg |= vid;
445 }
446 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
447 ((idx >> 1) << 2));
448 set_bit(idx, &priv->vlan_map);
449 }
450
451 return 0;
452 }
453
454 static int fe_vlan_rx_kill_vid(struct net_device *dev,
455 __be16 proto, u16 vid)
456 {
457 struct fe_priv *priv = netdev_priv(dev);
458 u32 idx = (vid & 0xf);
459
460 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
461 (dev->features | NETIF_F_HW_VLAN_CTAG_TX)))
462 return 0;
463
464 clear_bit(idx, &priv->vlan_map);
465
466 return 0;
467 }
468
469 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
470 int idx)
471 {
472 struct fe_priv *priv = netdev_priv(dev);
473 struct skb_frag_struct *frag;
474 struct fe_tx_dma *txd;
475 dma_addr_t mapped_addr;
476 unsigned int nr_frags;
477 u32 def_txd4, txd2;
478 int i, j, unmap_idx, tx_num;
479
480 txd = &priv->tx_dma[idx];
481 nr_frags = skb_shinfo(skb)->nr_frags;
482 tx_num = 1 + (nr_frags >> 1);
483
484 /* init tx descriptor */
485 if (priv->soc->tx_dma)
486 priv->soc->tx_dma(priv, idx, skb);
487 else
488 txd->txd4 = TX_DMA_DESP4_DEF;
489 def_txd4 = txd->txd4;
490
491 /* use dma_unmap_single to free it */
492 txd->txd4 |= priv->soc->tx_udf_bit;
493
494 /* TX Checksum offload */
495 if (skb->ip_summed == CHECKSUM_PARTIAL)
496 txd->txd4 |= TX_DMA_CHKSUM;
497
498 /* VLAN header offload */
499 if (vlan_tx_tag_present(skb)) {
500 if (IS_ENABLED(CONFIG_SOC_MT7620))
501 txd->txd4 |= TX_DMA_INS_VLAN |
502 ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
503 (vlan_tx_tag_get(skb) & 0xF);
504 else
505 txd->txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
506 }
507
508 /* TSO: fill MSS info in tcp checksum field */
509 if (skb_is_gso(skb)) {
510 if (skb_cow_head(skb, 0)) {
511 netif_warn(priv, tx_err, dev,
512 "GSO expand head fail.\n");
513 goto err_out;
514 }
515 if (skb_shinfo(skb)->gso_type &
516 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
517 txd->txd4 |= TX_DMA_TSO;
518 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
519 }
520 }
521
522 mapped_addr = dma_map_single(&dev->dev, skb->data,
523 skb_headlen(skb), DMA_TO_DEVICE);
524 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
525 goto err_out;
526 txd->txd1 = mapped_addr;
527 txd2 = TX_DMA_PLEN0(skb_headlen(skb));
528
529 /* TX SG offload */
530 j = idx;
531 for (i = 0; i < nr_frags; i++) {
532
533 frag = &skb_shinfo(skb)->frags[i];
534 mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0,
535 skb_frag_size(frag), DMA_TO_DEVICE);
536 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
537 goto err_dma;
538
539 if (i & 0x1) {
540 j = NEXT_TX_DESP_IDX(j);
541 txd = &priv->tx_dma[j];
542 txd->txd1 = mapped_addr;
543 txd2 = TX_DMA_PLEN0(frag->size);
544 txd->txd4 = def_txd4;
545 } else {
546 txd->txd3 = mapped_addr;
547 txd2 |= TX_DMA_PLEN1(frag->size);
548 if (i != (nr_frags -1))
549 txd->txd2 = txd2;
550 priv->tx_skb[j] = (struct sk_buff *) DMA_DUMMY_DESC;
551 }
552 }
553
554 /* set last segment */
555 if (nr_frags & 0x1)
556 txd->txd2 = (txd2 | TX_DMA_LS1);
557 else
558 txd->txd2 = (txd2 | TX_DMA_LS0);
559
560 /* store skb to cleanup */
561 priv->tx_skb[j] = skb;
562
563 wmb();
564 j = NEXT_TX_DESP_IDX(j);
565 fe_reg_w32(j, FE_REG_TX_CTX_IDX0);
566
567 return 0;
568
569 err_dma:
570 /* unmap dma */
571 txd = &priv->tx_dma[idx];
572 txd_unmap_single(&dev->dev, txd);
573
574 j = idx;
575 unmap_idx = i;
576 for (i = 0; i < unmap_idx; i++) {
577 if (i & 0x1) {
578 j = NEXT_TX_DESP_IDX(j);
579 txd = &priv->tx_dma[j];
580 txd_unmap_page0(&dev->dev, txd);
581 } else {
582 txd_unmap_page1(&dev->dev, txd);
583 }
584 }
585
586 err_out:
587 /* reinit descriptors and skb */
588 j = idx;
589 for (i = 0; i < tx_num; i++) {
590 priv->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;
591 priv->tx_skb[j] = NULL;
592 j = NEXT_TX_DESP_IDX(j);
593 }
594 wmb();
595
596 return -1;
597 }
598
599 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
600 unsigned int len;
601 int ret;
602
603 ret = 0;
604 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
605 if ((priv->flags & FE_FLAG_PADDING_64B) &&
606 !(priv->flags & FE_FLAG_PADDING_BUG))
607 return ret;
608
609 if (vlan_tx_tag_present(skb))
610 len = ETH_ZLEN;
611 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
612 len = VLAN_ETH_ZLEN;
613 else if(!(priv->flags & FE_FLAG_PADDING_64B))
614 len = ETH_ZLEN;
615 else
616 return ret;
617
618 if (skb->len < len) {
619 if ((ret = skb_pad(skb, len - skb->len)) < 0)
620 return ret;
621 skb->len = len;
622 skb_set_tail_pointer(skb, len);
623 }
624 }
625
626 return ret;
627 }
628
629 static inline u32 fe_empty_txd(struct fe_priv *priv, u32 tx_fill_idx)
630 {
631 return (u32)(NUM_DMA_DESC - ((tx_fill_idx - priv->tx_free_idx) &
632 (NUM_DMA_DESC - 1)));
633 }
634
635 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
636 {
637 struct fe_priv *priv = netdev_priv(dev);
638 struct net_device_stats *stats = &dev->stats;
639 u32 tx;
640 int tx_num;
641
642 if (fe_skb_padto(skb, priv)) {
643 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
644 return NETDEV_TX_OK;
645 }
646
647 spin_lock(&priv->page_lock);
648 tx_num = 1 + (skb_shinfo(skb)->nr_frags >> 1);
649 tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
650 if (unlikely(fe_empty_txd(priv, tx) <= tx_num))
651 {
652 netif_stop_queue(dev);
653 spin_unlock(&priv->page_lock);
654 netif_err(priv, tx_queued,dev,
655 "Tx Ring full when queue awake!\n");
656 return NETDEV_TX_BUSY;
657 }
658
659 if (fe_tx_map_dma(skb, dev, tx) < 0) {
660 kfree_skb(skb);
661
662 stats->tx_dropped++;
663 } else {
664 netdev_sent_queue(dev, skb->len);
665 skb_tx_timestamp(skb);
666
667 stats->tx_packets++;
668 stats->tx_bytes += skb->len;
669 }
670
671 spin_unlock(&priv->page_lock);
672
673 return NETDEV_TX_OK;
674 }
675
676 static inline void fe_rx_vlan(struct sk_buff *skb)
677 {
678 struct ethhdr *ehdr;
679 u16 vlanid;
680
681 if (!__vlan_get_tag(skb, &vlanid)) {
682 /* pop the vlan tag */
683 ehdr = (struct ethhdr *)skb->data;
684 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
685 skb_pull(skb, VLAN_HLEN);
686 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
687 }
688 }
689
690 static int fe_poll_rx(struct napi_struct *napi, int budget,
691 struct fe_priv *priv)
692 {
693 struct net_device *netdev = priv->netdev;
694 struct net_device_stats *stats = &netdev->stats;
695 struct fe_soc_data *soc = priv->soc;
696 u32 checksum_bit;
697 int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
698 struct sk_buff *skb;
699 u8 *data, *new_data;
700 struct fe_rx_dma *rxd;
701 int done = 0;
702 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
703
704 if (netdev->features & NETIF_F_RXCSUM)
705 checksum_bit = soc->checksum_bit;
706 else
707 checksum_bit = 0;
708
709 while (done < budget) {
710 unsigned int pktlen;
711 dma_addr_t dma_addr;
712 idx = NEXT_RX_DESP_IDX(idx);
713 rxd = &priv->rx_dma[idx];
714 data = priv->rx_data[idx];
715
716 if (!(rxd->rxd2 & RX_DMA_DONE))
717 break;
718
719 /* alloc new buffer */
720 new_data = netdev_alloc_frag(priv->frag_size);
721 if (unlikely(!new_data)) {
722 stats->rx_dropped++;
723 goto release_desc;
724 }
725 dma_addr = dma_map_single(&netdev->dev,
726 new_data + FE_RX_OFFSET,
727 priv->rx_buf_size,
728 DMA_FROM_DEVICE);
729 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
730 put_page(virt_to_head_page(new_data));
731 goto release_desc;
732 }
733
734 /* receive data */
735 skb = build_skb(data, priv->frag_size);
736 if (unlikely(!skb)) {
737 put_page(virt_to_head_page(new_data));
738 goto release_desc;
739 }
740 skb_reserve(skb, FE_RX_OFFSET);
741
742 dma_unmap_single(&netdev->dev, rxd->rxd1,
743 priv->rx_buf_size, DMA_FROM_DEVICE);
744 pktlen = RX_DMA_PLEN0(rxd->rxd2);
745 skb_put(skb, pktlen);
746 skb->dev = netdev;
747 if (rxd->rxd4 & checksum_bit) {
748 skb->ip_summed = CHECKSUM_UNNECESSARY;
749 } else {
750 skb_checksum_none_assert(skb);
751 }
752 if (rx_vlan)
753 fe_rx_vlan(skb);
754 skb->protocol = eth_type_trans(skb, netdev);
755
756 stats->rx_packets++;
757 stats->rx_bytes += pktlen;
758
759 napi_gro_receive(napi, skb);
760
761 priv->rx_data[idx] = new_data;
762 rxd->rxd1 = (unsigned int) dma_addr;
763
764 release_desc:
765 if (soc->rx_dma)
766 soc->rx_dma(priv, idx, priv->rx_buf_size);
767 else
768 rxd->rxd2 = RX_DMA_LSO;
769
770 wmb();
771 fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
772 done++;
773 }
774
775 return done;
776 }
777
778 static int fe_poll_tx(struct fe_priv *priv, int budget)
779 {
780 struct net_device *netdev = priv->netdev;
781 struct device *dev = &netdev->dev;
782 unsigned int bytes_compl = 0;
783 struct sk_buff *skb;
784 struct fe_tx_dma *txd;
785 int done = 0, idx;
786 u32 udf_bit = priv->soc->tx_udf_bit;
787
788 idx = priv->tx_free_idx;
789 while (done < budget) {
790 txd = &priv->tx_dma[idx];
791 skb = priv->tx_skb[idx];
792
793 if (!(txd->txd2 & TX_DMA_DONE) || !skb)
794 break;
795
796 txd_unmap_page1(dev, txd);
797
798 if (txd->txd4 & udf_bit)
799 txd_unmap_single(dev, txd);
800 else
801 txd_unmap_page0(dev, txd);
802
803 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
804 bytes_compl += skb->len;
805 dev_kfree_skb_any(skb);
806 done++;
807 }
808 priv->tx_skb[idx] = NULL;
809 idx = NEXT_TX_DESP_IDX(idx);
810 }
811 priv->tx_free_idx = idx;
812
813 if (!done)
814 return 0;
815
816 netdev_completed_queue(netdev, done, bytes_compl);
817 if (unlikely(netif_queue_stopped(netdev) &&
818 netif_carrier_ok(netdev))) {
819 netif_wake_queue(netdev);
820 }
821
822 return done;
823 }
824
825 static int fe_poll(struct napi_struct *napi, int budget)
826 {
827 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
828 struct fe_hw_stats *hwstat = priv->hw_stats;
829 int tx_done, rx_done;
830 u32 status, mask;
831 u32 tx_intr, rx_intr;
832
833 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
834 tx_intr = priv->soc->tx_dly_int;
835 rx_intr = priv->soc->rx_dly_int;
836 tx_done = rx_done = 0;
837
838 poll_again:
839 if (status & tx_intr) {
840 tx_done += fe_poll_tx(priv, budget - tx_done);
841 if (tx_done < budget) {
842 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
843 }
844 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
845 }
846
847 if (status & rx_intr) {
848 rx_done += fe_poll_rx(napi, budget - rx_done, priv);
849 if (rx_done < budget) {
850 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
851 }
852 }
853
854 if (unlikely(hwstat && (status & FE_CNT_GDM_AF))) {
855 if (spin_trylock(&hwstat->stats_lock)) {
856 fe_stats_update(priv);
857 spin_unlock(&hwstat->stats_lock);
858 }
859 fe_reg_w32(FE_CNT_GDM_AF, FE_REG_FE_INT_STATUS);
860 }
861
862 if (unlikely(netif_msg_intr(priv))) {
863 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
864 netdev_info(priv->netdev,
865 "done tx %d, rx %d, intr 0x%x/0x%x\n",
866 tx_done, rx_done, status, mask);
867 }
868
869 if ((tx_done < budget) && (rx_done < budget)) {
870 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
871 if (status & (tx_intr | rx_intr )) {
872 goto poll_again;
873 }
874 napi_complete(napi);
875 fe_int_enable(tx_intr | rx_intr);
876 }
877
878 return rx_done;
879 }
880
881 static void fe_tx_timeout(struct net_device *dev)
882 {
883 struct fe_priv *priv = netdev_priv(dev);
884
885 priv->netdev->stats.tx_errors++;
886 netif_err(priv, tx_err, dev,
887 "transmit timed out, waking up the queue\n");
888 netif_info(priv, drv, dev, ": dma_cfg:%08x, free_idx:%d, " \
889 "dma_ctx_idx=%u, dma_crx_idx=%u\n",
890 fe_reg_r32(FE_REG_PDMA_GLO_CFG), priv->tx_free_idx,
891 fe_reg_r32(FE_REG_TX_CTX_IDX0),
892 fe_reg_r32(FE_REG_RX_CALC_IDX0));
893 netif_wake_queue(dev);
894 }
895
896 static irqreturn_t fe_handle_irq(int irq, void *dev)
897 {
898 struct fe_priv *priv = netdev_priv(dev);
899 u32 status, dly_int;
900
901 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
902
903 if (unlikely(!status))
904 return IRQ_NONE;
905
906 dly_int = (priv->soc->rx_dly_int | priv->soc->tx_dly_int);
907 if (likely(status & dly_int)) {
908 fe_int_disable(dly_int);
909 napi_schedule(&priv->rx_napi);
910 } else {
911 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
912 }
913
914 return IRQ_HANDLED;
915 }
916
917 #ifdef CONFIG_NET_POLL_CONTROLLER
918 static void fe_poll_controller(struct net_device *dev)
919 {
920 struct fe_priv *priv = netdev_priv(dev);
921 u32 dly_int = priv->soc->tx_dly_int | priv->soc->rx_dly_int;
922
923 fe_int_disable(dly_int);
924 fe_handle_irq(dev->irq, dev);
925 fe_int_enable(dly_int);
926 }
927 #endif
928
929 int fe_set_clock_cycle(struct fe_priv *priv)
930 {
931 unsigned long sysclk = priv->sysclk;
932
933 if (!sysclk) {
934 return -EINVAL;
935 }
936
937 sysclk /= FE_US_CYC_CNT_DIVISOR;
938 sysclk <<= FE_US_CYC_CNT_SHIFT;
939
940 fe_w32((fe_r32(FE_FE_GLO_CFG) &
941 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
942 sysclk,
943 FE_FE_GLO_CFG);
944 return 0;
945 }
946
947 void fe_fwd_config(struct fe_priv *priv)
948 {
949 u32 fwd_cfg;
950
951 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
952
953 /* disable jumbo frame */
954 if (priv->flags & FE_FLAG_JUMBO_FRAME)
955 fwd_cfg &= ~FE_GDM1_JMB_EN;
956
957 /* set unicast/multicast/broadcast frame to cpu */
958 fwd_cfg &= ~0xffff;
959
960 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
961 }
962
963 static void fe_rxcsum_config(bool enable)
964 {
965 if (enable)
966 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
967 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
968 FE_GDMA1_FWD_CFG);
969 else
970 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
971 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
972 FE_GDMA1_FWD_CFG);
973 }
974
975 static void fe_txcsum_config(bool enable)
976 {
977 if (enable)
978 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
979 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
980 FE_CDMA_CSG_CFG);
981 else
982 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
983 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
984 FE_CDMA_CSG_CFG);
985 }
986
987 void fe_csum_config(struct fe_priv *priv)
988 {
989 struct net_device *dev = priv_netdev(priv);
990
991 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
992 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
993 }
994
995 static int fe_hw_init(struct net_device *dev)
996 {
997 struct fe_priv *priv = netdev_priv(dev);
998 int i, err;
999
1000 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1001 dev_name(priv->device), dev);
1002 if (err)
1003 return err;
1004
1005 if (priv->soc->set_mac)
1006 priv->soc->set_mac(priv, dev->dev_addr);
1007 else
1008 fe_hw_set_macaddr(priv, dev->dev_addr);
1009
1010 fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
1011
1012 fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
1013
1014 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
1015 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1016 for (i = 0; i < 16; i += 2)
1017 fe_w32(((i + 1) << 16) + i,
1018 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1019 (i * 2));
1020
1021 BUG_ON(!priv->soc->fwd_config);
1022 if (priv->soc->fwd_config(priv))
1023 netdev_err(dev, "unable to get clock\n");
1024
1025 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1026 fe_reg_w32(1, FE_REG_FE_RST_GL);
1027 fe_reg_w32(0, FE_REG_FE_RST_GL);
1028 }
1029
1030 return 0;
1031 }
1032
1033 static int fe_open(struct net_device *dev)
1034 {
1035 struct fe_priv *priv = netdev_priv(dev);
1036 unsigned long flags;
1037 u32 val;
1038 int err;
1039
1040 err = fe_init_dma(priv);
1041 if (err)
1042 goto err_out;
1043
1044 spin_lock_irqsave(&priv->page_lock, flags);
1045 napi_enable(&priv->rx_napi);
1046
1047 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1048 val |= priv->soc->pdma_glo_cfg;
1049 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1050
1051 spin_unlock_irqrestore(&priv->page_lock, flags);
1052
1053 if (priv->phy)
1054 priv->phy->start(priv);
1055
1056 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1057 netif_carrier_on(dev);
1058
1059 netif_start_queue(dev);
1060 fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
1061
1062 return 0;
1063
1064 err_out:
1065 fe_free_dma(priv);
1066 return err;
1067 }
1068
1069 static int fe_stop(struct net_device *dev)
1070 {
1071 struct fe_priv *priv = netdev_priv(dev);
1072 unsigned long flags;
1073 int i;
1074
1075 fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
1076
1077 netif_tx_disable(dev);
1078
1079 if (priv->phy)
1080 priv->phy->stop(priv);
1081
1082 spin_lock_irqsave(&priv->page_lock, flags);
1083 napi_disable(&priv->rx_napi);
1084
1085 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1086 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1087 FE_REG_PDMA_GLO_CFG);
1088 spin_unlock_irqrestore(&priv->page_lock, flags);
1089
1090 /* wait dma stop */
1091 for (i = 0; i < 10; i++) {
1092 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1093 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1094 msleep(10);
1095 continue;
1096 }
1097 break;
1098 }
1099
1100 fe_free_dma(priv);
1101
1102 return 0;
1103 }
1104
1105 static int __init fe_init(struct net_device *dev)
1106 {
1107 struct fe_priv *priv = netdev_priv(dev);
1108 struct device_node *port;
1109 int err;
1110
1111 BUG_ON(!priv->soc->reset_fe);
1112 priv->soc->reset_fe();
1113
1114 if (priv->soc->switch_init)
1115 priv->soc->switch_init(priv);
1116
1117 memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
1118 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1119
1120 err = fe_mdio_init(priv);
1121 if (err)
1122 return err;
1123
1124 if (priv->soc->port_init)
1125 for_each_child_of_node(priv->device->of_node, port)
1126 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1127 priv->soc->port_init(priv, port);
1128
1129 if (priv->phy) {
1130 err = priv->phy->connect(priv);
1131 if (err)
1132 goto err_phy_disconnect;
1133 }
1134
1135 err = fe_hw_init(dev);
1136 if (err)
1137 goto err_phy_disconnect;
1138
1139 if (priv->soc->switch_config)
1140 priv->soc->switch_config(priv);
1141
1142 return 0;
1143
1144 err_phy_disconnect:
1145 if (priv->phy)
1146 priv->phy->disconnect(priv);
1147 fe_mdio_cleanup(priv);
1148
1149 return err;
1150 }
1151
1152 static void fe_uninit(struct net_device *dev)
1153 {
1154 struct fe_priv *priv = netdev_priv(dev);
1155
1156 if (priv->phy)
1157 priv->phy->disconnect(priv);
1158 fe_mdio_cleanup(priv);
1159
1160 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1161 free_irq(dev->irq, dev);
1162 }
1163
1164 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1165 {
1166 struct fe_priv *priv = netdev_priv(dev);
1167
1168 if (!priv->phy_dev)
1169 return -ENODEV;
1170
1171 switch (cmd) {
1172 case SIOCETHTOOL:
1173 return phy_ethtool_ioctl(priv->phy_dev,
1174 (void *) ifr->ifr_data);
1175 case SIOCGMIIPHY:
1176 case SIOCGMIIREG:
1177 case SIOCSMIIREG:
1178 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1179 default:
1180 break;
1181 }
1182
1183 return -EOPNOTSUPP;
1184 }
1185
1186 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1187 {
1188 struct fe_priv *priv = netdev_priv(dev);
1189 int frag_size, old_mtu;
1190 u32 fwd_cfg;
1191
1192 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1193 return eth_change_mtu(dev, new_mtu);
1194
1195 frag_size = fe_max_frag_size(new_mtu);
1196 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1197 return -EINVAL;
1198
1199 old_mtu = dev->mtu;
1200 dev->mtu = new_mtu;
1201
1202 /* return early if the buffer sizes will not change */
1203 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1204 return 0;
1205 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1206 return 0;
1207
1208 if (new_mtu <= ETH_DATA_LEN) {
1209 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1210 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1211 } else {
1212 priv->frag_size = PAGE_SIZE;
1213 priv->rx_buf_size = fe_max_buf_size(PAGE_SIZE);
1214 }
1215
1216 if (!netif_running(dev))
1217 return 0;
1218
1219 fe_stop(dev);
1220 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1221 if (new_mtu <= ETH_DATA_LEN)
1222 fwd_cfg &= ~FE_GDM1_JMB_EN;
1223 else {
1224 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1225 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1226 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1227 }
1228 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1229
1230 return fe_open(dev);
1231 }
1232
1233 static const struct net_device_ops fe_netdev_ops = {
1234 .ndo_init = fe_init,
1235 .ndo_uninit = fe_uninit,
1236 .ndo_open = fe_open,
1237 .ndo_stop = fe_stop,
1238 .ndo_start_xmit = fe_start_xmit,
1239 .ndo_set_mac_address = fe_set_mac_address,
1240 .ndo_validate_addr = eth_validate_addr,
1241 .ndo_do_ioctl = fe_do_ioctl,
1242 .ndo_change_mtu = fe_change_mtu,
1243 .ndo_tx_timeout = fe_tx_timeout,
1244 .ndo_get_stats64 = fe_get_stats64,
1245 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1246 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1247 #ifdef CONFIG_NET_POLL_CONTROLLER
1248 .ndo_poll_controller = fe_poll_controller,
1249 #endif
1250 };
1251
1252 static int fe_probe(struct platform_device *pdev)
1253 {
1254 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1255 const struct of_device_id *match;
1256 struct fe_soc_data *soc;
1257 struct net_device *netdev;
1258 struct fe_priv *priv;
1259 struct clk *sysclk;
1260 int err;
1261
1262 device_reset(&pdev->dev);
1263
1264 match = of_match_device(of_fe_match, &pdev->dev);
1265 soc = (struct fe_soc_data *) match->data;
1266
1267 if (soc->reg_table)
1268 fe_reg_table = soc->reg_table;
1269 else
1270 soc->reg_table = fe_reg_table;
1271
1272 fe_base = devm_request_and_ioremap(&pdev->dev, res);
1273 if (!fe_base) {
1274 err = -EADDRNOTAVAIL;
1275 goto err_out;
1276 }
1277
1278 netdev = alloc_etherdev(sizeof(*priv));
1279 if (!netdev) {
1280 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1281 err = -ENOMEM;
1282 goto err_iounmap;
1283 }
1284
1285 SET_NETDEV_DEV(netdev, &pdev->dev);
1286 netdev->netdev_ops = &fe_netdev_ops;
1287 netdev->base_addr = (unsigned long) fe_base;
1288 netdev->watchdog_timeo = TX_TIMEOUT;
1289
1290 netdev->irq = platform_get_irq(pdev, 0);
1291 if (netdev->irq < 0) {
1292 dev_err(&pdev->dev, "no IRQ resource found\n");
1293 err = -ENXIO;
1294 goto err_free_dev;
1295 }
1296
1297 if (soc->init_data)
1298 soc->init_data(soc, netdev);
1299 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1300 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1301 netdev->vlan_features = netdev->hw_features &
1302 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1303 netdev->features |= netdev->hw_features;
1304
1305 /* fake rx vlan filter func. to support tx vlan offload func */
1306 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1307 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1308
1309 priv = netdev_priv(netdev);
1310 spin_lock_init(&priv->page_lock);
1311 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1312 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1313 if (!priv->hw_stats) {
1314 err = -ENOMEM;
1315 goto err_free_dev;
1316 }
1317 spin_lock_init(&priv->hw_stats->stats_lock);
1318 }
1319
1320 sysclk = devm_clk_get(&pdev->dev, NULL);
1321 if (!IS_ERR(sysclk))
1322 priv->sysclk = clk_get_rate(sysclk);
1323
1324 priv->netdev = netdev;
1325 priv->device = &pdev->dev;
1326 priv->soc = soc;
1327 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1328 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1329 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1330 if (priv->frag_size > PAGE_SIZE) {
1331 dev_err(&pdev->dev, "error frag size.\n");
1332 err = -EINVAL;
1333 goto err_free_dev;
1334 }
1335
1336 netif_napi_add(netdev, &priv->rx_napi, fe_poll, 32);
1337 fe_set_ethtool_ops(netdev);
1338
1339 err = register_netdev(netdev);
1340 if (err) {
1341 dev_err(&pdev->dev, "error bringing up device\n");
1342 goto err_free_dev;
1343 }
1344
1345 platform_set_drvdata(pdev, netdev);
1346
1347 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1348 netdev->base_addr, netdev->irq);
1349
1350 return 0;
1351
1352 err_free_dev:
1353 free_netdev(netdev);
1354 err_iounmap:
1355 devm_iounmap(&pdev->dev, fe_base);
1356 err_out:
1357 return err;
1358 }
1359
1360 static int fe_remove(struct platform_device *pdev)
1361 {
1362 struct net_device *dev = platform_get_drvdata(pdev);
1363 struct fe_priv *priv = netdev_priv(dev);
1364
1365 netif_napi_del(&priv->rx_napi);
1366 if (priv->hw_stats)
1367 kfree(priv->hw_stats);
1368
1369 unregister_netdev(dev);
1370 free_netdev(dev);
1371 platform_set_drvdata(pdev, NULL);
1372
1373 return 0;
1374 }
1375
1376 static struct platform_driver fe_driver = {
1377 .probe = fe_probe,
1378 .remove = fe_remove,
1379 .driver = {
1380 .name = "ralink_soc_eth",
1381 .owner = THIS_MODULE,
1382 .of_match_table = of_fe_match,
1383 },
1384 };
1385
1386 static int __init init_rtfe(void)
1387 {
1388 int ret;
1389
1390 ret = rtesw_init();
1391 if (ret)
1392 return ret;
1393
1394 ret = platform_driver_register(&fe_driver);
1395 if (ret)
1396 rtesw_exit();
1397
1398 return ret;
1399 }
1400
1401 static void __exit exit_rtfe(void)
1402 {
1403 platform_driver_unregister(&fe_driver);
1404 rtesw_exit();
1405 }
1406
1407 module_init(init_rtfe);
1408 module_exit(exit_rtfe);
1409
1410 MODULE_LICENSE("GPL");
1411 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1412 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1413 MODULE_VERSION(FE_DRV_VERSION);
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