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ralink: fix the 10mbit bug on mt7621
[openwrt/staging/chunkeey.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / ralink_soc_eth.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/if_vlan.h>
32 #include <linux/reset.h>
33 #include <linux/tcp.h>
34 #include <linux/io.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "ralink_soc_eth.h"
39 #include "esw_rt3052.h"
40 #include "mdio.h"
41 #include "ralink_ethtool.h"
42
43 #define TX_TIMEOUT (2 * HZ)
44 #define MAX_RX_LENGTH 1536
45 #define FE_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
46 #define FE_RX_HLEN (FE_RX_OFFSET + VLAN_ETH_HLEN + VLAN_HLEN + \
47 ETH_FCS_LEN)
48 #define DMA_DUMMY_DESC 0xffffffff
49 #define FE_DEFAULT_MSG_ENABLE \
50 (NETIF_MSG_DRV | \
51 NETIF_MSG_PROBE | \
52 NETIF_MSG_LINK | \
53 NETIF_MSG_TIMER | \
54 NETIF_MSG_IFDOWN | \
55 NETIF_MSG_IFUP | \
56 NETIF_MSG_RX_ERR | \
57 NETIF_MSG_TX_ERR)
58
59 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
60 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
61 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
62 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (NUM_DMA_DESC - 1))
63
64 static int fe_msg_level = -1;
65 module_param_named(msg_level, fe_msg_level, int, 0);
66 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
67
68 static const u32 fe_reg_table_default[FE_REG_COUNT] = {
69 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
70 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
71 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
72 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
73 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
74 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
75 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
76 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
77 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
78 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
79 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
80 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
81 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
82 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
83 };
84
85 static const u32 *fe_reg_table = fe_reg_table_default;
86
87 static void __iomem *fe_base = 0;
88
89 void fe_w32(u32 val, unsigned reg)
90 {
91 __raw_writel(val, fe_base + reg);
92 }
93
94 u32 fe_r32(unsigned reg)
95 {
96 return __raw_readl(fe_base + reg);
97 }
98
99 void fe_reg_w32(u32 val, enum fe_reg reg)
100 {
101 fe_w32(val, fe_reg_table[reg]);
102 }
103
104 u32 fe_reg_r32(enum fe_reg reg)
105 {
106 return fe_r32(fe_reg_table[reg]);
107 }
108
109 static inline void fe_int_disable(u32 mask)
110 {
111 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
112 FE_REG_FE_INT_ENABLE);
113 /* flush write */
114 fe_reg_r32(FE_REG_FE_INT_ENABLE);
115 }
116
117 static inline void fe_int_enable(u32 mask)
118 {
119 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
120 FE_REG_FE_INT_ENABLE);
121 /* flush write */
122 fe_reg_r32(FE_REG_FE_INT_ENABLE);
123 }
124
125 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
126 {
127 unsigned long flags;
128
129 spin_lock_irqsave(&priv->page_lock, flags);
130 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
131 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
132 FE_GDMA1_MAC_ADRL);
133 spin_unlock_irqrestore(&priv->page_lock, flags);
134 }
135
136 static int fe_set_mac_address(struct net_device *dev, void *p)
137 {
138 int ret = eth_mac_addr(dev, p);
139
140 if (!ret) {
141 struct fe_priv *priv = netdev_priv(dev);
142
143 if (priv->soc->set_mac)
144 priv->soc->set_mac(priv, dev->dev_addr);
145 else
146 fe_hw_set_macaddr(priv, p);
147 }
148
149 return ret;
150 }
151
152 static inline int fe_max_frag_size(int mtu)
153 {
154 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
155 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
156 }
157
158 static inline int fe_max_buf_size(int frag_size)
159 {
160 return frag_size - FE_RX_HLEN -
161 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
162 }
163
164 static void fe_clean_rx(struct fe_priv *priv)
165 {
166 int i;
167
168 if (priv->rx_data) {
169 for (i = 0; i < NUM_DMA_DESC; i++)
170 if (priv->rx_data[i]) {
171 if (priv->rx_dma && priv->rx_dma[i].rxd1)
172 dma_unmap_single(&priv->netdev->dev,
173 priv->rx_dma[i].rxd1,
174 priv->rx_buf_size,
175 DMA_FROM_DEVICE);
176 put_page(virt_to_head_page(priv->rx_data[i]));
177 }
178
179 kfree(priv->rx_data);
180 priv->rx_data = NULL;
181 }
182
183 if (priv->rx_dma) {
184 dma_free_coherent(&priv->netdev->dev,
185 NUM_DMA_DESC * sizeof(*priv->rx_dma),
186 priv->rx_dma,
187 priv->rx_phys);
188 priv->rx_dma = NULL;
189 }
190 }
191
192 static int fe_alloc_rx(struct fe_priv *priv)
193 {
194 struct net_device *netdev = priv->netdev;
195 int i;
196
197 priv->rx_data = kcalloc(NUM_DMA_DESC, sizeof(*priv->rx_data),
198 GFP_KERNEL);
199 if (!priv->rx_data)
200 goto no_rx_mem;
201
202 for (i = 0; i < NUM_DMA_DESC; i++) {
203 priv->rx_data[i] = netdev_alloc_frag(priv->frag_size);
204 if (!priv->rx_data[i])
205 goto no_rx_mem;
206 }
207
208 priv->rx_dma = dma_alloc_coherent(&netdev->dev,
209 NUM_DMA_DESC * sizeof(*priv->rx_dma),
210 &priv->rx_phys,
211 GFP_ATOMIC | __GFP_ZERO);
212 if (!priv->rx_dma)
213 goto no_rx_mem;
214
215 for (i = 0; i < NUM_DMA_DESC; i++) {
216 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
217 priv->rx_data[i] + FE_RX_OFFSET,
218 priv->rx_buf_size,
219 DMA_FROM_DEVICE);
220 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
221 goto no_rx_mem;
222 priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
223
224 if (priv->soc->rx_dma)
225 priv->soc->rx_dma(priv, i, priv->rx_buf_size);
226 else
227 priv->rx_dma[i].rxd2 = RX_DMA_LSO;
228 }
229 wmb();
230
231 fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
232 fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
233 fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
234 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
235
236 return 0;
237
238 no_rx_mem:
239 return -ENOMEM;
240 }
241
242 static void fe_clean_tx(struct fe_priv *priv)
243 {
244 int i;
245
246 if (priv->tx_skb) {
247 for (i = 0; i < NUM_DMA_DESC; i++) {
248 if (priv->tx_skb[i])
249 dev_kfree_skb_any(priv->tx_skb[i]);
250 }
251 kfree(priv->tx_skb);
252 priv->tx_skb = NULL;
253 }
254
255 if (priv->tx_dma) {
256 dma_free_coherent(&priv->netdev->dev,
257 NUM_DMA_DESC * sizeof(*priv->tx_dma),
258 priv->tx_dma,
259 priv->tx_phys);
260 priv->tx_dma = NULL;
261 }
262 }
263
264 static int fe_alloc_tx(struct fe_priv *priv)
265 {
266 int i;
267
268 priv->tx_free_idx = 0;
269
270 priv->tx_skb = kcalloc(NUM_DMA_DESC, sizeof(*priv->tx_skb),
271 GFP_KERNEL);
272 if (!priv->tx_skb)
273 goto no_tx_mem;
274
275 priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
276 NUM_DMA_DESC * sizeof(*priv->tx_dma),
277 &priv->tx_phys,
278 GFP_ATOMIC | __GFP_ZERO);
279 if (!priv->tx_dma)
280 goto no_tx_mem;
281
282 for (i = 0; i < NUM_DMA_DESC; i++) {
283 if (priv->soc->tx_dma) {
284 priv->soc->tx_dma(priv, i, NULL);
285 continue;
286 }
287 priv->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
288 }
289 wmb();
290
291 fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
292 fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
293 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
294 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
295
296 return 0;
297
298 no_tx_mem:
299 return -ENOMEM;
300 }
301
302 static int fe_init_dma(struct fe_priv *priv)
303 {
304 int err;
305
306 err = fe_alloc_tx(priv);
307 if (err)
308 return err;
309
310 err = fe_alloc_rx(priv);
311 if (err)
312 return err;
313
314 return 0;
315 }
316
317 static void fe_free_dma(struct fe_priv *priv)
318 {
319 fe_clean_tx(priv);
320 fe_clean_rx(priv);
321
322 netdev_reset_queue(priv->netdev);
323 }
324
325 static inline void txd_unmap_single(struct device *dev, struct fe_tx_dma *txd)
326 {
327 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
328 dma_unmap_single(dev, txd->txd1,
329 TX_DMA_GET_PLEN0(txd->txd2),
330 DMA_TO_DEVICE);
331 }
332
333 static inline void txd_unmap_page0(struct device *dev, struct fe_tx_dma *txd)
334 {
335 if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
336 dma_unmap_page(dev, txd->txd1,
337 TX_DMA_GET_PLEN0(txd->txd2),
338 DMA_TO_DEVICE);
339 }
340
341 static inline void txd_unmap_page1(struct device *dev, struct fe_tx_dma *txd)
342 {
343 if (txd->txd3 && TX_DMA_GET_PLEN1(txd->txd2))
344 dma_unmap_page(dev, txd->txd3,
345 TX_DMA_GET_PLEN1(txd->txd2),
346 DMA_TO_DEVICE);
347 }
348
349 void fe_stats_update(struct fe_priv *priv)
350 {
351 struct fe_hw_stats *hwstats = priv->hw_stats;
352 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
353
354 u64_stats_update_begin(&hwstats->syncp);
355
356 hwstats->tx_bytes += fe_r32(base);
357 hwstats->tx_packets += fe_r32(base + 0x04);
358 hwstats->tx_skip += fe_r32(base + 0x08);
359 hwstats->tx_collisions += fe_r32(base + 0x0c);
360 hwstats->rx_bytes += fe_r32(base + 0x20);
361 hwstats->rx_packets += fe_r32(base + 0x24);
362 hwstats->rx_overflow += fe_r32(base + 0x28);
363 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
364 hwstats->rx_short_errors += fe_r32(base + 0x30);
365 hwstats->rx_long_errors += fe_r32(base + 0x34);
366 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
367 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
368
369 u64_stats_update_end(&hwstats->syncp);
370 }
371
372 static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
373 struct rtnl_link_stats64 *storage)
374 {
375 struct fe_priv *priv = netdev_priv(dev);
376 struct fe_hw_stats *hwstats = priv->hw_stats;
377 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
378 unsigned int start;
379
380 if (!base) {
381 netdev_stats_to_stats64(storage, &dev->stats);
382 return storage;
383 }
384
385 if (netif_running(dev) && netif_device_present(dev)) {
386 if (spin_trylock(&hwstats->stats_lock)) {
387 fe_stats_update(priv);
388 spin_unlock(&hwstats->stats_lock);
389 }
390 }
391
392 do {
393 start = u64_stats_fetch_begin_bh(&hwstats->syncp);
394 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
395 storage->rx_packets = dev->stats.rx_packets;
396 storage->tx_packets = dev->stats.tx_packets;
397 storage->rx_bytes = dev->stats.rx_bytes;
398 storage->tx_bytes = dev->stats.tx_bytes;
399 } else {
400 storage->rx_packets = dev->stats.rx_packets;
401 storage->tx_packets = dev->stats.tx_packets;
402 storage->rx_bytes = dev->stats.rx_bytes;
403 storage->tx_bytes = dev->stats.tx_bytes;
404 }
405 storage->collisions = hwstats->tx_collisions;
406 storage->rx_length_errors = hwstats->rx_short_errors +
407 hwstats->rx_long_errors;
408 storage->rx_over_errors = hwstats->rx_overflow;
409 storage->rx_crc_errors = hwstats->rx_fcs_errors;
410 storage->rx_errors = hwstats->rx_checksum_errors;
411 storage->tx_aborted_errors = hwstats->tx_skip;
412 } while (u64_stats_fetch_retry_bh(&hwstats->syncp, start));
413
414 storage->tx_errors = priv->netdev->stats.tx_errors;
415 storage->rx_dropped = priv->netdev->stats.rx_dropped;
416 storage->tx_dropped = priv->netdev->stats.tx_dropped;
417
418 return storage;
419 }
420
421 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
422 int idx)
423 {
424 struct fe_priv *priv = netdev_priv(dev);
425 struct skb_frag_struct *frag;
426 struct fe_tx_dma *txd;
427 dma_addr_t mapped_addr;
428 unsigned int nr_frags;
429 u32 def_txd4, txd2;
430 int i, j, unmap_idx, tx_num;
431
432 txd = &priv->tx_dma[idx];
433 nr_frags = skb_shinfo(skb)->nr_frags;
434 tx_num = 1 + (nr_frags >> 1);
435
436 /* init tx descriptor */
437 if (priv->soc->tx_dma)
438 priv->soc->tx_dma(priv, idx, skb);
439 else
440 txd->txd4 = TX_DMA_DESP4_DEF;
441 def_txd4 = txd->txd4;
442
443 /* use dma_unmap_single to free it */
444 txd->txd4 |= priv->soc->tx_udf_bit;
445
446 /* TX Checksum offload */
447 if (skb->ip_summed == CHECKSUM_PARTIAL)
448 txd->txd4 |= TX_DMA_CHKSUM;
449
450 /* VLAN header offload */
451 if (vlan_tx_tag_present(skb)) {
452 if (IS_ENABLED(CONFIG_SOC_MT7620))
453 txd->txd4 |= TX_DMA_INS_VLAN |
454 ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
455 (vlan_tx_tag_get(skb) & 0xF);
456 else
457 txd->txd4 |= TX_DMA_INS_VLAN_MT7621 | vlan_tx_tag_get(skb);
458 }
459
460 /* TSO: fill MSS info in tcp checksum field */
461 if (skb_is_gso(skb)) {
462 if (skb_cow_head(skb, 0)) {
463 netif_warn(priv, tx_err, dev,
464 "GSO expand head fail.\n");
465 goto err_out;
466 }
467 if (skb_shinfo(skb)->gso_type &
468 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
469 txd->txd4 |= TX_DMA_TSO;
470 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
471 }
472 }
473
474 mapped_addr = dma_map_single(&dev->dev, skb->data,
475 skb_headlen(skb), DMA_TO_DEVICE);
476 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
477 goto err_out;
478 txd->txd1 = mapped_addr;
479 txd2 = TX_DMA_PLEN0(skb_headlen(skb));
480
481 /* TX SG offload */
482 j = idx;
483 for (i = 0; i < nr_frags; i++) {
484
485 frag = &skb_shinfo(skb)->frags[i];
486 mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0,
487 skb_frag_size(frag), DMA_TO_DEVICE);
488 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
489 goto err_dma;
490
491 if (i & 0x1) {
492 j = NEXT_TX_DESP_IDX(j);
493 txd = &priv->tx_dma[j];
494 txd->txd1 = mapped_addr;
495 txd2 = TX_DMA_PLEN0(frag->size);
496 txd->txd4 = def_txd4;
497 } else {
498 txd->txd3 = mapped_addr;
499 txd2 |= TX_DMA_PLEN1(frag->size);
500 if (i != (nr_frags -1))
501 txd->txd2 = txd2;
502 priv->tx_skb[j] = (struct sk_buff *) DMA_DUMMY_DESC;
503 }
504 }
505
506 /* set last segment */
507 if (nr_frags & 0x1)
508 txd->txd2 = (txd2 | TX_DMA_LS1);
509 else
510 txd->txd2 = (txd2 | TX_DMA_LS0);
511
512 /* store skb to cleanup */
513 priv->tx_skb[j] = skb;
514
515 wmb();
516 j = NEXT_TX_DESP_IDX(j);
517 fe_reg_w32(j, FE_REG_TX_CTX_IDX0);
518
519 return 0;
520
521 err_dma:
522 /* unmap dma */
523 txd = &priv->tx_dma[idx];
524 txd_unmap_single(&dev->dev, txd);
525
526 j = idx;
527 unmap_idx = i;
528 for (i = 0; i < unmap_idx; i++) {
529 if (i & 0x1) {
530 j = NEXT_TX_DESP_IDX(j);
531 txd = &priv->tx_dma[j];
532 txd_unmap_page0(&dev->dev, txd);
533 } else {
534 txd_unmap_page1(&dev->dev, txd);
535 }
536 }
537
538 err_out:
539 /* reinit descriptors and skb */
540 j = idx;
541 for (i = 0; i < tx_num; i++) {
542 priv->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;
543 priv->tx_skb[j] = NULL;
544 j = NEXT_TX_DESP_IDX(j);
545 }
546 wmb();
547
548 return -1;
549 }
550
551 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
552 unsigned int len;
553 int ret;
554
555 ret = 0;
556 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
557 if ((priv->flags & FE_FLAG_PADDING_64B) &&
558 !(priv->flags & FE_FLAG_PADDING_BUG))
559 return ret;
560
561 if (vlan_tx_tag_present(skb))
562 len = ETH_ZLEN;
563 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
564 len = VLAN_ETH_ZLEN;
565 else if(!(priv->flags & FE_FLAG_PADDING_64B))
566 len = ETH_ZLEN;
567 else
568 return ret;
569
570 if (skb->len < len) {
571 if ((ret = skb_pad(skb, len - skb->len)) < 0)
572 return ret;
573 skb->len = len;
574 skb_set_tail_pointer(skb, len);
575 }
576 }
577
578 return ret;
579 }
580
581 static inline u32 fe_empty_txd(struct fe_priv *priv, u32 tx_fill_idx)
582 {
583 return (u32)(NUM_DMA_DESC - ((tx_fill_idx - priv->tx_free_idx) &
584 (NUM_DMA_DESC - 1)));
585 }
586
587 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
588 {
589 struct fe_priv *priv = netdev_priv(dev);
590 struct net_device_stats *stats = &dev->stats;
591 u32 tx;
592 int tx_num;
593
594 if (fe_skb_padto(skb, priv)) {
595 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
596 return NETDEV_TX_OK;
597 }
598
599 spin_lock(&priv->page_lock);
600 tx_num = 1 + (skb_shinfo(skb)->nr_frags >> 1);
601 tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
602 if (unlikely(fe_empty_txd(priv, tx) <= tx_num))
603 {
604 netif_stop_queue(dev);
605 spin_unlock(&priv->page_lock);
606 netif_err(priv, tx_queued,dev,
607 "Tx Ring full when queue awake!\n");
608 return NETDEV_TX_BUSY;
609 }
610
611 if (fe_tx_map_dma(skb, dev, tx) < 0) {
612 kfree_skb(skb);
613
614 stats->tx_dropped++;
615 } else {
616 netdev_sent_queue(dev, skb->len);
617 skb_tx_timestamp(skb);
618
619 stats->tx_packets++;
620 stats->tx_bytes += skb->len;
621 }
622
623 spin_unlock(&priv->page_lock);
624
625 return NETDEV_TX_OK;
626 }
627
628 static inline void fe_rx_vlan(struct sk_buff *skb)
629 {
630 struct ethhdr *ehdr;
631 u16 vlanid;
632
633 if (!__vlan_get_tag(skb, &vlanid)) {
634 /* pop the vlan tag */
635 ehdr = (struct ethhdr *)skb->data;
636 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
637 skb_pull(skb, VLAN_HLEN);
638 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
639 }
640 }
641
642 static int fe_poll_rx(struct napi_struct *napi, int budget,
643 struct fe_priv *priv)
644 {
645 struct net_device *netdev = priv->netdev;
646 struct net_device_stats *stats = &netdev->stats;
647 struct fe_soc_data *soc = priv->soc;
648 u32 checksum_bit;
649 int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
650 struct sk_buff *skb;
651 u8 *data, *new_data;
652 struct fe_rx_dma *rxd;
653 int done = 0;
654 bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
655
656 if (netdev->features & NETIF_F_RXCSUM)
657 checksum_bit = soc->checksum_bit;
658 else
659 checksum_bit = 0;
660
661 while (done < budget) {
662 unsigned int pktlen;
663 dma_addr_t dma_addr;
664 idx = NEXT_RX_DESP_IDX(idx);
665 rxd = &priv->rx_dma[idx];
666 data = priv->rx_data[idx];
667
668 if (!(rxd->rxd2 & RX_DMA_DONE))
669 break;
670
671 /* alloc new buffer */
672 new_data = netdev_alloc_frag(priv->frag_size);
673 if (unlikely(!new_data)) {
674 stats->rx_dropped++;
675 goto release_desc;
676 }
677 dma_addr = dma_map_single(&netdev->dev,
678 new_data + FE_RX_OFFSET,
679 priv->rx_buf_size,
680 DMA_FROM_DEVICE);
681 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
682 put_page(virt_to_head_page(new_data));
683 goto release_desc;
684 }
685
686 /* receive data */
687 skb = build_skb(data, priv->frag_size);
688 if (unlikely(!skb)) {
689 put_page(virt_to_head_page(new_data));
690 goto release_desc;
691 }
692 skb_reserve(skb, FE_RX_OFFSET);
693
694 dma_unmap_single(&netdev->dev, rxd->rxd1,
695 priv->rx_buf_size, DMA_FROM_DEVICE);
696 pktlen = RX_DMA_PLEN0(rxd->rxd2);
697 skb_put(skb, pktlen);
698 skb->dev = netdev;
699 if (rxd->rxd4 & checksum_bit) {
700 skb->ip_summed = CHECKSUM_UNNECESSARY;
701 } else {
702 skb_checksum_none_assert(skb);
703 }
704 if (rx_vlan)
705 fe_rx_vlan(skb);
706 skb->protocol = eth_type_trans(skb, netdev);
707
708 stats->rx_packets++;
709 stats->rx_bytes += pktlen;
710
711 napi_gro_receive(napi, skb);
712
713 priv->rx_data[idx] = new_data;
714 rxd->rxd1 = (unsigned int) dma_addr;
715
716 release_desc:
717 if (soc->rx_dma)
718 soc->rx_dma(priv, idx, priv->rx_buf_size);
719 else
720 rxd->rxd2 = RX_DMA_LSO;
721
722 wmb();
723 fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
724 done++;
725 }
726
727 return done;
728 }
729
730 static int fe_poll_tx(struct fe_priv *priv, int budget)
731 {
732 struct net_device *netdev = priv->netdev;
733 struct device *dev = &netdev->dev;
734 unsigned int bytes_compl = 0;
735 struct sk_buff *skb;
736 struct fe_tx_dma *txd;
737 int done = 0, idx;
738 u32 udf_bit = priv->soc->tx_udf_bit;
739
740 idx = priv->tx_free_idx;
741 while (done < budget) {
742 txd = &priv->tx_dma[idx];
743 skb = priv->tx_skb[idx];
744
745 if (!(txd->txd2 & TX_DMA_DONE) || !skb)
746 break;
747
748 txd_unmap_page1(dev, txd);
749
750 if (txd->txd4 & udf_bit)
751 txd_unmap_single(dev, txd);
752 else
753 txd_unmap_page0(dev, txd);
754
755 if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
756 bytes_compl += skb->len;
757 dev_kfree_skb_any(skb);
758 done++;
759 }
760 priv->tx_skb[idx] = NULL;
761 idx = NEXT_TX_DESP_IDX(idx);
762 }
763 priv->tx_free_idx = idx;
764
765 if (!done)
766 return 0;
767
768 netdev_completed_queue(netdev, done, bytes_compl);
769 if (unlikely(netif_queue_stopped(netdev) &&
770 netif_carrier_ok(netdev))) {
771 netif_wake_queue(netdev);
772 }
773
774 return done;
775 }
776
777 static int fe_poll(struct napi_struct *napi, int budget)
778 {
779 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
780 struct fe_hw_stats *hwstat = priv->hw_stats;
781 int tx_done, rx_done;
782 u32 status, mask;
783 u32 tx_intr, rx_intr;
784
785 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
786 tx_intr = priv->soc->tx_dly_int;
787 rx_intr = priv->soc->rx_dly_int;
788 tx_done = rx_done = 0;
789
790 poll_again:
791 if (status & tx_intr) {
792 tx_done += fe_poll_tx(priv, budget - tx_done);
793 if (tx_done < budget) {
794 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
795 }
796 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
797 }
798
799 if (status & rx_intr) {
800 rx_done += fe_poll_rx(napi, budget - rx_done, priv);
801 if (rx_done < budget) {
802 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
803 }
804 }
805
806 if (unlikely(hwstat && (status & FE_CNT_GDM_AF))) {
807 if (spin_trylock(&hwstat->stats_lock)) {
808 fe_stats_update(priv);
809 spin_unlock(&hwstat->stats_lock);
810 }
811 fe_reg_w32(FE_CNT_GDM_AF, FE_REG_FE_INT_STATUS);
812 }
813
814 if (unlikely(netif_msg_intr(priv))) {
815 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
816 netdev_info(priv->netdev,
817 "done tx %d, rx %d, intr 0x%x/0x%x\n",
818 tx_done, rx_done, status, mask);
819 }
820
821 if ((tx_done < budget) && (rx_done < budget)) {
822 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
823 if (status & (tx_intr | rx_intr )) {
824 goto poll_again;
825 }
826 napi_complete(napi);
827 fe_int_enable(tx_intr | rx_intr);
828 }
829
830 return rx_done;
831 }
832
833 static void fe_tx_timeout(struct net_device *dev)
834 {
835 struct fe_priv *priv = netdev_priv(dev);
836
837 priv->netdev->stats.tx_errors++;
838 netif_err(priv, tx_err, dev,
839 "transmit timed out, waking up the queue\n");
840 netif_info(priv, drv, dev, ": dma_cfg:%08x, free_idx:%d, " \
841 "dma_ctx_idx=%u, dma_crx_idx=%u\n",
842 fe_reg_r32(FE_REG_PDMA_GLO_CFG), priv->tx_free_idx,
843 fe_reg_r32(FE_REG_TX_CTX_IDX0),
844 fe_reg_r32(FE_REG_RX_CALC_IDX0));
845 netif_wake_queue(dev);
846 }
847
848 static irqreturn_t fe_handle_irq(int irq, void *dev)
849 {
850 struct fe_priv *priv = netdev_priv(dev);
851 u32 status, dly_int;
852
853 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
854
855 if (unlikely(!status))
856 return IRQ_NONE;
857
858 dly_int = (priv->soc->rx_dly_int | priv->soc->tx_dly_int);
859 if (likely(status & dly_int)) {
860 fe_int_disable(dly_int);
861 napi_schedule(&priv->rx_napi);
862 } else {
863 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
864 }
865
866 return IRQ_HANDLED;
867 }
868
869 int fe_set_clock_cycle(struct fe_priv *priv)
870 {
871 unsigned long sysclk = priv->sysclk;
872
873 if (!sysclk) {
874 return -EINVAL;
875 }
876
877 sysclk /= FE_US_CYC_CNT_DIVISOR;
878 sysclk <<= FE_US_CYC_CNT_SHIFT;
879
880 fe_w32((fe_r32(FE_FE_GLO_CFG) &
881 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
882 sysclk,
883 FE_FE_GLO_CFG);
884 return 0;
885 }
886
887 void fe_fwd_config(struct fe_priv *priv)
888 {
889 u32 fwd_cfg;
890
891 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
892
893 /* disable jumbo frame */
894 if (priv->flags & FE_FLAG_JUMBO_FRAME)
895 fwd_cfg &= ~FE_GDM1_JMB_EN;
896
897 /* set unicast/multicast/broadcast frame to cpu */
898 fwd_cfg &= ~0xffff;
899
900 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
901 }
902
903 static void fe_rxcsum_config(bool enable)
904 {
905 if (enable)
906 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
907 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
908 FE_GDMA1_FWD_CFG);
909 else
910 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
911 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
912 FE_GDMA1_FWD_CFG);
913 }
914
915 static void fe_txcsum_config(bool enable)
916 {
917 if (enable)
918 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
919 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
920 FE_CDMA_CSG_CFG);
921 else
922 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
923 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
924 FE_CDMA_CSG_CFG);
925 }
926
927 void fe_csum_config(struct fe_priv *priv)
928 {
929 struct net_device *dev = priv_netdev(priv);
930
931 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
932 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
933 }
934
935 static int fe_hw_init(struct net_device *dev)
936 {
937 struct fe_priv *priv = netdev_priv(dev);
938 int i, err;
939
940 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
941 dev_name(priv->device), dev);
942 if (err)
943 return err;
944
945 if (priv->soc->set_mac)
946 priv->soc->set_mac(priv, dev->dev_addr);
947 else
948 fe_hw_set_macaddr(priv, dev->dev_addr);
949
950 fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
951
952 fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
953
954 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
955 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
956 for (i = 0; i < 16; i += 2)
957 fe_w32(((i + 1) << 16) + i,
958 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
959 (i * 2));
960
961 BUG_ON(!priv->soc->fwd_config);
962 if (priv->soc->fwd_config(priv))
963 netdev_err(dev, "unable to get clock\n");
964
965 if (fe_reg_table[FE_REG_FE_RST_GL]) {
966 fe_reg_w32(1, FE_REG_FE_RST_GL);
967 fe_reg_w32(0, FE_REG_FE_RST_GL);
968 }
969
970 return 0;
971 }
972
973 static int fe_open(struct net_device *dev)
974 {
975 struct fe_priv *priv = netdev_priv(dev);
976 unsigned long flags;
977 u32 val;
978 int err;
979
980 err = fe_init_dma(priv);
981 if (err)
982 goto err_out;
983
984 spin_lock_irqsave(&priv->page_lock, flags);
985 napi_enable(&priv->rx_napi);
986
987 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
988 val |= priv->soc->pdma_glo_cfg;
989 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
990
991 spin_unlock_irqrestore(&priv->page_lock, flags);
992
993 if (priv->phy)
994 priv->phy->start(priv);
995
996 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
997 netif_carrier_on(dev);
998
999 netif_start_queue(dev);
1000 fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
1001
1002 return 0;
1003
1004 err_out:
1005 fe_free_dma(priv);
1006 return err;
1007 }
1008
1009 static int fe_stop(struct net_device *dev)
1010 {
1011 struct fe_priv *priv = netdev_priv(dev);
1012 unsigned long flags;
1013 int i;
1014
1015 fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
1016
1017 netif_tx_disable(dev);
1018
1019 if (priv->phy)
1020 priv->phy->stop(priv);
1021
1022 spin_lock_irqsave(&priv->page_lock, flags);
1023 napi_disable(&priv->rx_napi);
1024
1025 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1026 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1027 FE_REG_PDMA_GLO_CFG);
1028 spin_unlock_irqrestore(&priv->page_lock, flags);
1029
1030 /* wait dma stop */
1031 for (i = 0; i < 10; i++) {
1032 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1033 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1034 msleep(10);
1035 continue;
1036 }
1037 break;
1038 }
1039
1040 fe_free_dma(priv);
1041
1042 return 0;
1043 }
1044
1045 static int __init fe_init(struct net_device *dev)
1046 {
1047 struct fe_priv *priv = netdev_priv(dev);
1048 struct device_node *port;
1049 int err;
1050
1051 BUG_ON(!priv->soc->reset_fe);
1052 priv->soc->reset_fe();
1053
1054 if (priv->soc->switch_init)
1055 priv->soc->switch_init(priv);
1056
1057 memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
1058 of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
1059
1060 err = fe_mdio_init(priv);
1061 if (err)
1062 return err;
1063
1064 if (priv->soc->port_init)
1065 for_each_child_of_node(priv->device->of_node, port)
1066 if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
1067 priv->soc->port_init(priv, port);
1068
1069 if (priv->phy) {
1070 err = priv->phy->connect(priv);
1071 if (err)
1072 goto err_phy_disconnect;
1073 }
1074
1075 err = fe_hw_init(dev);
1076 if (err)
1077 goto err_phy_disconnect;
1078
1079 if (priv->soc->switch_config)
1080 priv->soc->switch_config(priv);
1081
1082 return 0;
1083
1084 err_phy_disconnect:
1085 if (priv->phy)
1086 priv->phy->disconnect(priv);
1087 fe_mdio_cleanup(priv);
1088
1089 return err;
1090 }
1091
1092 static void fe_uninit(struct net_device *dev)
1093 {
1094 struct fe_priv *priv = netdev_priv(dev);
1095
1096 if (priv->phy)
1097 priv->phy->disconnect(priv);
1098 fe_mdio_cleanup(priv);
1099
1100 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1101 free_irq(dev->irq, dev);
1102 }
1103
1104 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1105 {
1106 struct fe_priv *priv = netdev_priv(dev);
1107
1108 if (!priv->phy_dev)
1109 return -ENODEV;
1110
1111 switch (cmd) {
1112 case SIOCETHTOOL:
1113 return phy_ethtool_ioctl(priv->phy_dev,
1114 (void *) ifr->ifr_data);
1115 case SIOCGMIIPHY:
1116 case SIOCGMIIREG:
1117 case SIOCSMIIREG:
1118 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1119 default:
1120 break;
1121 }
1122
1123 return -EOPNOTSUPP;
1124 }
1125
1126 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1127 {
1128 struct fe_priv *priv = netdev_priv(dev);
1129 int frag_size, old_mtu;
1130 u32 fwd_cfg;
1131
1132 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1133 return eth_change_mtu(dev, new_mtu);
1134
1135 frag_size = fe_max_frag_size(new_mtu);
1136 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1137 return -EINVAL;
1138
1139 old_mtu = dev->mtu;
1140 dev->mtu = new_mtu;
1141
1142 /* return early if the buffer sizes will not change */
1143 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1144 return 0;
1145 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1146 return 0;
1147
1148 if (new_mtu <= ETH_DATA_LEN) {
1149 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1150 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1151 } else {
1152 priv->frag_size = PAGE_SIZE;
1153 priv->rx_buf_size = fe_max_buf_size(PAGE_SIZE);
1154 }
1155
1156 if (!netif_running(dev))
1157 return 0;
1158
1159 fe_stop(dev);
1160 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1161 if (new_mtu <= ETH_DATA_LEN)
1162 fwd_cfg &= ~FE_GDM1_JMB_EN;
1163 else {
1164 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1165 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1166 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1167 }
1168 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1169
1170 return fe_open(dev);
1171 }
1172
1173 static const struct net_device_ops fe_netdev_ops = {
1174 .ndo_init = fe_init,
1175 .ndo_uninit = fe_uninit,
1176 .ndo_open = fe_open,
1177 .ndo_stop = fe_stop,
1178 .ndo_start_xmit = fe_start_xmit,
1179 .ndo_set_mac_address = fe_set_mac_address,
1180 .ndo_validate_addr = eth_validate_addr,
1181 .ndo_do_ioctl = fe_do_ioctl,
1182 .ndo_change_mtu = fe_change_mtu,
1183 .ndo_tx_timeout = fe_tx_timeout,
1184 .ndo_get_stats64 = fe_get_stats64,
1185 };
1186
1187 static int fe_probe(struct platform_device *pdev)
1188 {
1189 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1190 const struct of_device_id *match;
1191 struct fe_soc_data *soc;
1192 struct net_device *netdev;
1193 struct fe_priv *priv;
1194 struct clk *sysclk;
1195 int err;
1196
1197 device_reset(&pdev->dev);
1198
1199 match = of_match_device(of_fe_match, &pdev->dev);
1200 soc = (struct fe_soc_data *) match->data;
1201
1202 if (soc->reg_table)
1203 fe_reg_table = soc->reg_table;
1204 else
1205 soc->reg_table = fe_reg_table;
1206
1207 fe_base = devm_request_and_ioremap(&pdev->dev, res);
1208 if (!fe_base) {
1209 err = -EADDRNOTAVAIL;
1210 goto err_out;
1211 }
1212
1213 netdev = alloc_etherdev(sizeof(*priv));
1214 if (!netdev) {
1215 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1216 err = -ENOMEM;
1217 goto err_iounmap;
1218 }
1219
1220 SET_NETDEV_DEV(netdev, &pdev->dev);
1221 netdev->netdev_ops = &fe_netdev_ops;
1222 netdev->base_addr = (unsigned long) fe_base;
1223 netdev->watchdog_timeo = TX_TIMEOUT;
1224
1225 netdev->irq = platform_get_irq(pdev, 0);
1226 if (netdev->irq < 0) {
1227 dev_err(&pdev->dev, "no IRQ resource found\n");
1228 err = -ENXIO;
1229 goto err_free_dev;
1230 }
1231
1232 if (soc->init_data)
1233 soc->init_data(soc, netdev);
1234 /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
1235 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
1236 netdev->vlan_features = netdev->hw_features &
1237 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1238 netdev->features |= netdev->hw_features;
1239
1240 priv = netdev_priv(netdev);
1241 spin_lock_init(&priv->page_lock);
1242 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1243 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1244 if (!priv->hw_stats) {
1245 err = -ENOMEM;
1246 goto err_free_dev;
1247 }
1248 spin_lock_init(&priv->hw_stats->stats_lock);
1249 }
1250
1251 sysclk = devm_clk_get(&pdev->dev, NULL);
1252 if (!IS_ERR(sysclk))
1253 priv->sysclk = clk_get_rate(sysclk);
1254
1255 priv->netdev = netdev;
1256 priv->device = &pdev->dev;
1257 priv->soc = soc;
1258 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1259 priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
1260 priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
1261 if (priv->frag_size > PAGE_SIZE) {
1262 dev_err(&pdev->dev, "error frag size.\n");
1263 err = -EINVAL;
1264 goto err_free_dev;
1265 }
1266
1267 netif_napi_add(netdev, &priv->rx_napi, fe_poll, 32);
1268 fe_set_ethtool_ops(netdev);
1269
1270 err = register_netdev(netdev);
1271 if (err) {
1272 dev_err(&pdev->dev, "error bringing up device\n");
1273 goto err_free_dev;
1274 }
1275
1276 platform_set_drvdata(pdev, netdev);
1277
1278 netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
1279 netdev->base_addr, netdev->irq);
1280
1281 return 0;
1282
1283 err_free_dev:
1284 free_netdev(netdev);
1285 err_iounmap:
1286 devm_iounmap(&pdev->dev, fe_base);
1287 err_out:
1288 return err;
1289 }
1290
1291 static int fe_remove(struct platform_device *pdev)
1292 {
1293 struct net_device *dev = platform_get_drvdata(pdev);
1294 struct fe_priv *priv = netdev_priv(dev);
1295
1296 netif_napi_del(&priv->rx_napi);
1297 if (priv->hw_stats)
1298 kfree(priv->hw_stats);
1299
1300 unregister_netdev(dev);
1301 free_netdev(dev);
1302 platform_set_drvdata(pdev, NULL);
1303
1304 return 0;
1305 }
1306
1307 static struct platform_driver fe_driver = {
1308 .probe = fe_probe,
1309 .remove = fe_remove,
1310 .driver = {
1311 .name = "ralink_soc_eth",
1312 .owner = THIS_MODULE,
1313 .of_match_table = of_fe_match,
1314 },
1315 };
1316
1317 static int __init init_rtfe(void)
1318 {
1319 int ret;
1320
1321 ret = rtesw_init();
1322 if (ret)
1323 return ret;
1324
1325 ret = platform_driver_register(&fe_driver);
1326 if (ret)
1327 rtesw_exit();
1328
1329 return ret;
1330 }
1331
1332 static void __exit exit_rtfe(void)
1333 {
1334 platform_driver_unregister(&fe_driver);
1335 rtesw_exit();
1336 }
1337
1338 module_init(init_rtfe);
1339 module_exit(exit_rtfe);
1340
1341 MODULE_LICENSE("GPL");
1342 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1343 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1344 MODULE_VERSION(FE_DRV_VERSION);
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