target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; version 2 of the License
   5  *
   6  *   This program is distributed in the hope that it will be useful,
   7  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  *   GNU General Public License for more details.
  10  *
  11  *   You should have received a copy of the GNU General Public License
  12  *   along with this program; if not, write to the Free Software
  13  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  14  *
  15  *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/if_vlan.h>
  21
  22 #include <asm/mach-ralink/ralink_regs.h>
  23
  24 #include <mt7620.h>
  25 #include "ralink_soc_eth.h"
  26 #include "gsw_mt7620a.h"
  27
  28 #define MT7620A_CDMA_CSG_CFG    0x400
  29 #define MT7620_DMA_VID          (MT7620A_CDMA_CSG_CFG | 0x30)
  30 #define MT7621_DMA_VID          0xa8
  31 #define MT7620A_DMA_2B_OFFSET   BIT(31)
  32 #define MT7620A_RESET_FE        BIT(21)
  33 #define MT7621_RESET_FE         BIT(6)
  34 #define MT7620A_RESET_ESW       BIT(23)
  35 #define MT7620_L4_VALID         BIT(23)
  36 #define MT7621_L4_VALID         BIT(24)
  37
  38 #define MT7620_TX_DMA_UDF       BIT(15)
  39 #define MT7621_TX_DMA_UDF       BIT(19)
  40 #define TX_DMA_FP_BMAP          ((0xff) << 19)
  41
  42 #define CDMA_ICS_EN             BIT(2)
  43 #define CDMA_UCS_EN             BIT(1)
  44 #define CDMA_TCS_EN             BIT(0)
  45
  46 #define GDMA_ICS_EN             BIT(22)
  47 #define GDMA_TCS_EN             BIT(21)
  48 #define GDMA_UCS_EN             BIT(20)
  49
  50 /* frame engine counters */
  51 #define MT7620_REG_MIB_OFFSET   0x1000
  52 #define MT7620_PPE_AC_BCNT0     (MT7620_REG_MIB_OFFSET + 0x00)
  53 #define MT7620_GDM1_TX_GBCNT    (MT7620_REG_MIB_OFFSET + 0x300)
  54 #define MT7620_GDM2_TX_GBCNT    (MT7620_GDM1_TX_GBCNT + 0x40)
  55
  56 #define MT7621_REG_MIB_OFFSET   0x2000
  57 #define MT7621_PPE_AC_BCNT0     (MT7621_REG_MIB_OFFSET + 0x00)
  58 #define MT7621_GDM1_TX_GBCNT    (MT7621_REG_MIB_OFFSET + 0x400)
  59 #define MT7621_GDM2_TX_GBCNT    (MT7621_GDM1_TX_GBCNT + 0x40)
  60
  61 #define GSW_REG_GDMA1_MAC_ADRL  0x508
  62 #define GSW_REG_GDMA1_MAC_ADRH  0x50C
  63
  64 #define MT7621_FE_RST_GL        (FE_FE_OFFSET + 0x04)
  65
  66 static const u32 mt7620_reg_table[FE_REG_COUNT] = {
  67         [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
  68         [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
  69         [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
  70         [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
  71         [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
  72         [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
  73         [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
  74         [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
  75         [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
  76         [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
  77         [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
  78         [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
  79         [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
  80         [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
  81         [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
  82         [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
  83 };
  84
  85 static const u32 mt7621_reg_table[FE_REG_COUNT] = {
  86         [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
  87         [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
  88         [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
  89         [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
  90         [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
  91         [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
  92         [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
  93         [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
  94         [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
  95         [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
  96         [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
  97         [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
  98         [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
  99         [FE_REG_FE_DMA_VID_BASE] = MT7621_DMA_VID,
 100         [FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
 101         [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
 102 };
 103
 104 static void mt7620_fe_reset(void)
 105 {
 106         fe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW);
 107 }
 108
 109 static void mt7621_fe_reset(void)
 110 {
 111         fe_reset(MT7621_RESET_FE);
 112 }
 113
 114 static void mt7620_rxcsum_config(bool enable)
 115 {
 116         if (enable)
 117                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
 118                                         GDMA_TCS_EN | GDMA_UCS_EN),
 119                                 MT7620A_GDMA1_FWD_CFG);
 120         else
 121                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
 122                                         GDMA_TCS_EN | GDMA_UCS_EN),
 123                                 MT7620A_GDMA1_FWD_CFG);
 124 }
 125
 126 static void mt7620_txcsum_config(bool enable)
 127 {
 128         if (enable)
 129                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
 130                                         CDMA_UCS_EN | CDMA_TCS_EN),
 131                                 MT7620A_CDMA_CSG_CFG);
 132         else
 133                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
 134                                         CDMA_UCS_EN | CDMA_TCS_EN),
 135                                 MT7620A_CDMA_CSG_CFG);
 136 }
 137
 138 static int mt7620_fwd_config(struct fe_priv *priv)
 139 {
 140         struct net_device *dev = priv_netdev(priv);
 141
 142         fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
 143
 144         mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
 145         mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
 146
 147         return 0;
 148 }
 149
 150 static int mt7621_fwd_config(struct fe_priv *priv)
 151 {
 152         struct net_device *dev = priv_netdev(priv);
 153
 154         fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff, MT7620A_GDMA1_FWD_CFG);
 155
 156         mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
 157         mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
 158
 159         return 0;
 160 }
 161
 162 static void mt7620_tx_dma(struct fe_tx_dma *txd)
 163 {
 164         txd->txd4 = 0;
 165 }
 166
 167 static void mt7621_tx_dma(struct fe_tx_dma *txd)
 168 {
 169         txd->txd4 = BIT(25);
 170 }
 171
 172 static void mt7620_rx_dma(struct fe_rx_dma *rxd, u16 len)
 173 {
 174         rxd->rxd2 = RX_DMA_PLEN0(len);
 175 }
 176
 177 static void mt7620_init_data(struct fe_soc_data *data,
 178                 struct net_device *netdev)
 179 {
 180         struct fe_priv *priv = netdev_priv(netdev);
 181
 182         priv->flags = FE_FLAG_PADDING_64B;
 183         netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
 184                 NETIF_F_HW_VLAN_CTAG_TX;
 185
 186         if (mt7620_get_eco() >= 5 || IS_ENABLED(CONFIG_SOC_MT7621))
 187                 netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
 188                         NETIF_F_IPV6_CSUM;
 189 }
 190
 191 static void mt7621_init_data(struct fe_soc_data *data,
 192                 struct net_device *netdev)
 193 {
 194         struct fe_priv *priv = netdev_priv(netdev);
 195
 196         priv->flags = FE_FLAG_PADDING_64B;
 197         netdev->hw_features = NETIF_F_HW_VLAN_CTAG_TX;
 198 }
 199
 200 static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
 201 {
 202         unsigned long flags;
 203
 204         spin_lock_irqsave(&priv->page_lock, flags);
 205         fe_w32((mac[0] << 8) | mac[1], GSW_REG_GDMA1_MAC_ADRH);
 206         fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
 207                 GSW_REG_GDMA1_MAC_ADRL);
 208         spin_unlock_irqrestore(&priv->page_lock, flags);
 209 }
 210
 211 static struct fe_soc_data mt7620_data = {
 212         .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
 213         .init_data = mt7620_init_data,
 214         .reset_fe = mt7620_fe_reset,
 215         .set_mac = mt7620_set_mac,
 216         .fwd_config = mt7620_fwd_config,
 217         .tx_dma = mt7620_tx_dma,
 218         .rx_dma = mt7620_rx_dma,
 219         .switch_init = mt7620_gsw_probe,
 220         .switch_config = mt7620_gsw_config,
 221         .port_init = mt7620_port_init,
 222         .reg_table = mt7620_reg_table,
 223         .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
 224         .rx_int = RT5350_RX_DONE_INT,
 225         .tx_int = RT5350_TX_DONE_INT,
 226         .checksum_bit = MT7620_L4_VALID,
 227         .tx_udf_bit = MT7620_TX_DMA_UDF,
 228         .has_carrier = mt7620a_has_carrier,
 229         .mdio_read = mt7620_mdio_read,
 230         .mdio_write = mt7620_mdio_write,
 231         .mdio_adjust_link = mt7620_mdio_link_adjust,
 232 };
 233
 234 static struct fe_soc_data mt7621_data = {
 235         .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
 236         .init_data = mt7621_init_data,
 237         .reset_fe = mt7621_fe_reset,
 238         .set_mac = mt7621_set_mac,
 239         .fwd_config = mt7621_fwd_config,
 240         .tx_dma = mt7621_tx_dma,
 241         .rx_dma = mt7620_rx_dma,
 242         .switch_init = mt7620_gsw_probe,
 243         .switch_config = mt7621_gsw_config,
 244         .reg_table = mt7621_reg_table,
 245         .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
 246         .rx_int = RT5350_RX_DONE_INT,
 247         .tx_int = RT5350_TX_DONE_INT,
 248         .checksum_bit = MT7621_L4_VALID,
 249         .tx_udf_bit = MT7621_TX_DMA_UDF,
 250         .has_carrier = mt7620a_has_carrier,
 251         .mdio_read = mt7620_mdio_read,
 252         .mdio_write = mt7620_mdio_write,
 253         .mdio_adjust_link = mt7620_mdio_link_adjust,
 254 };
 255
 256 const struct of_device_id of_fe_match[] = {
 257         { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
 258         { .compatible = "ralink,mt7621-eth", .data = &mt7621_data },
 259         {},
 260 };
 261
 262 MODULE_DEVICE_TABLE(of, of_fe_match);