target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; version 2 of the License
   5  *
   6  *   This program is distributed in the hope that it will be useful,
   7  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  *   GNU General Public License for more details.
  10  *
  11  *   You should have received a copy of the GNU General Public License
  12  *   along with this program; if not, write to the Free Software
  13  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  14  *
  15  *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/if_vlan.h>
  21
  22 #include <asm/mach-ralink/ralink_regs.h>
  23
  24 #include <mt7620.h>
  25 #include "ralink_soc_eth.h"
  26 #include "gsw_mt7620a.h"
  27
  28 #define MT7620A_CDMA_CSG_CFG    0x400
  29 #define MT7620_DMA_VID          (MT7620A_CDMA_CSG_CFG | 0x30)
  30 #define MT7621_DMA_VID          0xa8
  31 #define MT7620A_DMA_2B_OFFSET   BIT(31)
  32 #define MT7620A_RESET_FE        BIT(21)
  33 #define MT7621_RESET_FE         BIT(6)
  34 #define MT7620A_RESET_ESW       BIT(23)
  35 #define MT7620_L4_VALID         BIT(23)
  36 #define MT7621_L4_VALID         BIT(24)
  37
  38 #define MT7620_TX_DMA_UDF       BIT(15)
  39 #define MT7621_TX_DMA_UDF       BIT(19)
  40 #define TX_DMA_FP_BMAP          ((0xff) << 19)
  41
  42 #define SYSC_REG_RESET_CTRL     0x34
  43
  44 #define CDMA_ICS_EN             BIT(2)
  45 #define CDMA_UCS_EN             BIT(1)
  46 #define CDMA_TCS_EN             BIT(0)
  47
  48 #define GDMA_ICS_EN             BIT(22)
  49 #define GDMA_TCS_EN             BIT(21)
  50 #define GDMA_UCS_EN             BIT(20)
  51
  52 /* frame engine counters */
  53 #define MT7620_REG_MIB_OFFSET   0x1000
  54 #define MT7620_PPE_AC_BCNT0     (MT7620_REG_MIB_OFFSET + 0x00)
  55 #define MT7620_GDM1_TX_GBCNT    (MT7620_REG_MIB_OFFSET + 0x300)
  56 #define MT7620_GDM2_TX_GBCNT    (MT7620_GDM1_TX_GBCNT + 0x40)
  57
  58 #define MT7621_REG_MIB_OFFSET   0x2000
  59 #define MT7621_PPE_AC_BCNT0     (MT7621_REG_MIB_OFFSET + 0x00)
  60 #define MT7621_GDM1_TX_GBCNT    (MT7621_REG_MIB_OFFSET + 0x400)
  61 #define MT7621_GDM2_TX_GBCNT    (MT7621_GDM1_TX_GBCNT + 0x40)
  62
  63 #define GSW_REG_GDMA1_MAC_ADRL  0x508
  64 #define GSW_REG_GDMA1_MAC_ADRH  0x50C
  65
  66 #define MT7621_FE_RST_GL        (FE_FE_OFFSET + 0x04)
  67
  68 static const u32 mt7620_reg_table[FE_REG_COUNT] = {
  69         [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
  70         [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
  71         [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
  72         [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
  73         [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
  74         [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
  75         [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
  76         [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
  77         [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
  78         [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
  79         [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
  80         [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
  81         [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
  82         [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
  83         [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
  84         [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
  85 };
  86
  87 static const u32 mt7621_reg_table[FE_REG_COUNT] = {
  88         [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
  89         [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
  90         [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
  91         [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
  92         [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
  93         [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
  94         [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
  95         [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
  96         [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
  97         [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
  98         [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
  99         [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
 100         [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
 101         [FE_REG_FE_DMA_VID_BASE] = MT7621_DMA_VID,
 102         [FE_REG_FE_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
 103         [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
 104 };
 105
 106 static void mt7620_fe_reset(void)
 107 {
 108         u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
 109
 110         rt_sysc_w32(val | MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
 111         rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
 112 }
 113
 114 static void mt7621_fe_reset(void)
 115 {
 116         u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
 117
 118         rt_sysc_w32(val | MT7621_RESET_FE, SYSC_REG_RESET_CTRL);
 119         rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
 120 }
 121
 122 static void mt7620_rxcsum_config(bool enable)
 123 {
 124         if (enable)
 125                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
 126                                         GDMA_TCS_EN | GDMA_UCS_EN),
 127                                 MT7620A_GDMA1_FWD_CFG);
 128         else
 129                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
 130                                         GDMA_TCS_EN | GDMA_UCS_EN),
 131                                 MT7620A_GDMA1_FWD_CFG);
 132 }
 133
 134 static void mt7620_txcsum_config(bool enable)
 135 {
 136         if (enable)
 137                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
 138                                         CDMA_UCS_EN | CDMA_TCS_EN),
 139                                 MT7620A_CDMA_CSG_CFG);
 140         else
 141                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
 142                                         CDMA_UCS_EN | CDMA_TCS_EN),
 143                                 MT7620A_CDMA_CSG_CFG);
 144 }
 145
 146 static int mt7620_fwd_config(struct fe_priv *priv)
 147 {
 148         struct net_device *dev = priv_netdev(priv);
 149
 150         fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
 151
 152         mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
 153         mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
 154
 155         return 0;
 156 }
 157
 158 static int mt7621_fwd_config(struct fe_priv *priv)
 159 {
 160         struct net_device *dev = priv_netdev(priv);
 161
 162         fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~0xffff, MT7620A_GDMA1_FWD_CFG);
 163
 164         mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
 165         mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
 166
 167         return 0;
 168 }
 169
 170 static void mt7620_tx_dma(struct fe_tx_dma *txd)
 171 {
 172         txd->txd4 = 0;
 173 }
 174
 175 static void mt7621_tx_dma(struct fe_tx_dma *txd)
 176 {
 177         txd->txd4 = BIT(25);
 178 }
 179
 180 static void mt7620_rx_dma(struct fe_rx_dma *rxd, u16 len)
 181 {
 182         rxd->rxd2 = RX_DMA_PLEN0(len);
 183 }
 184
 185 static void mt7620_init_data(struct fe_soc_data *data,
 186                 struct net_device *netdev)
 187 {
 188         struct fe_priv *priv = netdev_priv(netdev);
 189
 190         priv->flags = FE_FLAG_PADDING_64B;
 191         netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
 192                 NETIF_F_HW_VLAN_CTAG_TX;
 193
 194         if (mt7620_get_eco() >= 5 || IS_ENABLED(CONFIG_SOC_MT7621))
 195                 netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
 196                         NETIF_F_IPV6_CSUM;
 197 }
 198
 199 static void mt7621_init_data(struct fe_soc_data *data,
 200                 struct net_device *netdev)
 201 {
 202         struct fe_priv *priv = netdev_priv(netdev);
 203
 204         priv->flags = FE_FLAG_PADDING_64B;
 205         netdev->hw_features = NETIF_F_HW_VLAN_CTAG_TX;
 206 }
 207
 208 static void mt7621_set_mac(struct fe_priv *priv, unsigned char *mac)
 209 {
 210         unsigned long flags;
 211
 212         spin_lock_irqsave(&priv->page_lock, flags);
 213         fe_w32((mac[0] << 8) | mac[1], GSW_REG_GDMA1_MAC_ADRH);
 214         fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
 215                 GSW_REG_GDMA1_MAC_ADRL);
 216         spin_unlock_irqrestore(&priv->page_lock, flags);
 217 }
 218
 219 static struct fe_soc_data mt7620_data = {
 220         .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
 221         .init_data = mt7620_init_data,
 222         .reset_fe = mt7620_fe_reset,
 223         .set_mac = mt7620_set_mac,
 224         .fwd_config = mt7620_fwd_config,
 225         .tx_dma = mt7620_tx_dma,
 226         .rx_dma = mt7620_rx_dma,
 227         .switch_init = mt7620_gsw_probe,
 228         .switch_config = mt7620_gsw_config,
 229         .port_init = mt7620_port_init,
 230         .reg_table = mt7620_reg_table,
 231         .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
 232         .rx_int = RT5350_RX_DONE_INT,
 233         .tx_int = RT5350_TX_DONE_INT,
 234         .checksum_bit = MT7620_L4_VALID,
 235         .tx_udf_bit = MT7620_TX_DMA_UDF,
 236         .has_carrier = mt7620a_has_carrier,
 237         .mdio_read = mt7620_mdio_read,
 238         .mdio_write = mt7620_mdio_write,
 239         .mdio_adjust_link = mt7620_mdio_link_adjust,
 240 };
 241
 242 static struct fe_soc_data mt7621_data = {
 243         .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
 244         .init_data = mt7621_init_data,
 245         .reset_fe = mt7621_fe_reset,
 246         .set_mac = mt7621_set_mac,
 247         .fwd_config = mt7621_fwd_config,
 248         .tx_dma = mt7621_tx_dma,
 249         .rx_dma = mt7620_rx_dma,
 250         .switch_init = mt7620_gsw_probe,
 251         .switch_config = mt7621_gsw_config,
 252         .reg_table = mt7621_reg_table,
 253         .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
 254         .rx_int = RT5350_RX_DONE_INT,
 255         .tx_int = RT5350_TX_DONE_INT,
 256         .checksum_bit = MT7621_L4_VALID,
 257         .tx_udf_bit = MT7621_TX_DMA_UDF,
 258         .has_carrier = mt7620a_has_carrier,
 259         .mdio_read = mt7620_mdio_read,
 260         .mdio_write = mt7620_mdio_write,
 261         .mdio_adjust_link = mt7620_mdio_link_adjust,
 262 };
 263
 264 const struct of_device_id of_fe_match[] = {
 265         { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
 266         { .compatible = "ralink,mt7621-eth", .data = &mt7621_data },
 267         {},
 268 };
 269
 270 MODULE_DEVICE_TABLE(of, of_fe_match);