1 /* Copyright Statement:
3 * This software/firmware and related documentation ("MediaTek Software") are
4 * protected under relevant copyright laws. The information contained herein
5 * is confidential and proprietary to MediaTek Inc. and/or its licensors.
6 * Without the prior written permission of MediaTek inc. and/or its licensors,
7 * any reproduction, modification, use or disclosure of MediaTek Software,
8 * and information contained herein, in whole or in part, shall be strictly prohibited.
10 * MediaTek Inc. (C) 2010. All rights reserved.
12 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
13 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
14 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
15 * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
18 * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
19 * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
20 * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
21 * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
22 * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
23 * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
24 * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
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27 * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
28 * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
29 * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
31 * The following software/firmware and/or related documentation ("MediaTek Software")
32 * have been modified by MediaTek Inc. All revisions are subject to any receiver's
33 * applicable license agreements with MediaTek Inc.
36 #include <linux/module.h>
37 #include <linux/delay.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/spinlock.h>
40 #include <linux/platform_device.h>
41 #include <linux/interrupt.h>
43 #include <linux/mmc/host.h>
44 #include <linux/mmc/mmc.h>
45 #include <linux/mmc/sd.h>
46 #include <linux/mmc/sdio.h>
48 #include <asm/mach-ralink/ralink_regs.h>
52 #include "mt6575_sd.h"
54 //#define IRQ_SDC 14 //MT7620 /*FIXME*/
55 #ifdef CONFIG_SOC_MT7621
56 #define RALINK_SYSCTL_BASE 0xbe000000
57 #define RALINK_MSDC_BASE 0xbe130000
59 #define RALINK_SYSCTL_BASE 0xb0000000
60 #define RALINK_MSDC_BASE 0xb0130000
62 #define IRQ_SDC 22 /*FIXME*/
64 #define DRV_NAME "mtk-sd"
66 #if defined(CONFIG_SOC_MT7620)
67 #define HOST_MAX_MCLK (48000000) /* +/- by chhung */
68 #elif defined(CONFIG_SOC_MT7621)
69 #define HOST_MAX_MCLK (50000000) /* +/- by chhung */
71 #define HOST_MIN_MCLK (260000)
73 #define HOST_MAX_BLKSZ (2048)
75 #define MSDC_OCR_AVAIL (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
77 #define GPIO_PULL_DOWN (0)
78 #define GPIO_PULL_UP (1)
80 #if 0 /* --- by chhung */
81 #define MSDC_CLKSRC_REG (0xf100000C)
82 #define PDN_REG (0xF1000010)
83 #endif /* end of --- */
85 #define DEFAULT_DEBOUNCE (8) /* 8 cycles */
86 #define DEFAULT_DTOC (40) /* data timeout counter. 65536x40 sclk. */
88 #define CMD_TIMEOUT (HZ / 10) /* 100ms */
89 #define DAT_TIMEOUT (HZ / 2 * 5) /* 500ms x5 */
91 #define MAX_DMA_CNT (64 * 1024 - 512) /* a single transaction for WIFI may be 50K*/
93 #define MAX_GPD_NUM (1 + 1) /* one null gpd */
94 #define MAX_BD_NUM (1024)
95 #define MAX_BD_PER_GPD (MAX_BD_NUM)
97 #define MAX_HW_SGMTS (MAX_BD_NUM)
98 #define MAX_PHY_SGMTS (MAX_BD_NUM)
99 #define MAX_SGMT_SZ (MAX_DMA_CNT)
100 #define MAX_REQ_SZ (MAX_SGMT_SZ * 8)
102 static int cd_active_low
= 1;
104 //=================================
105 #define PERI_MSDC0_PDN (15)
106 //#define PERI_MSDC1_PDN (16)
107 //#define PERI_MSDC2_PDN (17)
108 //#define PERI_MSDC3_PDN (18)
110 #if 0 /* --- by chhung */
111 /* gate means clock power down */
112 static int g_clk_gate
= 0;
113 #define msdc_gate_clock(id) \
115 g_clk_gate &= ~(1 << ((id) + PERI_MSDC0_PDN)); \
117 /* not like power down register. 1 means clock on. */
118 #define msdc_ungate_clock(id) \
120 g_clk_gate |= 1 << ((id) + PERI_MSDC0_PDN); \
123 // do we need sync object or not
124 void msdc_clk_status(int *status
)
126 *status
= g_clk_gate
;
128 #endif /* end of --- */
131 struct msdc_hw msdc0_hw
= {
133 .flags
= MSDC_CD_PIN_EN
| MSDC_REMOVABLE
,
134 // .flags = MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE,
139 static int msdc_rsp
[] = {
151 #define msdc_txfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
152 #define msdc_rxfifocnt() ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
153 #define msdc_fifo_write32(v) sdr_write32(MSDC_TXDATA, (v))
154 #define msdc_fifo_write8(v) sdr_write8(MSDC_TXDATA, (v))
155 #define msdc_fifo_read32() sdr_read32(MSDC_RXDATA)
156 #define msdc_fifo_read8() sdr_read8(MSDC_RXDATA)
158 #define msdc_dma_on() sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
160 #define msdc_retry(expr, retry, cnt) \
167 retry--; mdelay(1); cnt = backup; \
170 WARN_ON(retry == 0); \
173 static void msdc_reset_hw(struct msdc_host
*host
)
175 void __iomem
*base
= host
->base
;
177 sdr_set_bits(MSDC_CFG
, MSDC_CFG_RST
);
178 while (sdr_read32(MSDC_CFG
) & MSDC_CFG_RST
)
182 #define msdc_clr_int() \
184 volatile u32 val = sdr_read32(MSDC_INT); \
185 sdr_write32(MSDC_INT, val); \
188 #define msdc_clr_fifo() \
190 int retry = 3, cnt = 1000; \
191 sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
192 msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
195 #define msdc_irq_save(val) \
197 val = sdr_read32(MSDC_INTEN); \
198 sdr_clr_bits(MSDC_INTEN, val); \
201 #define msdc_irq_restore(val) \
203 sdr_set_bits(MSDC_INTEN, val); \
206 /* clock source for host: global */
207 #if defined(CONFIG_SOC_MT7620)
208 static u32 hclks
[] = {48000000}; /* +/- by chhung */
209 #elif defined(CONFIG_SOC_MT7621)
210 static u32 hclks
[] = {50000000}; /* +/- by chhung */
213 //============================================
214 // the power for msdc host controller: global
215 // always keep the VMC on.
216 //============================================
217 #define msdc_vcore_on(host) \
219 INIT_MSG("[+]VMC ref. count<%d>", ++host->pwr_ref); \
220 (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
222 #define msdc_vcore_off(host) \
224 INIT_MSG("[-]VMC ref. count<%d>", --host->pwr_ref); \
225 (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
228 //====================================
229 // the vdd output for card: global
230 // always keep the VMCH on.
231 //====================================
232 #define msdc_vdd_on(host) \
234 (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
236 #define msdc_vdd_off(host) \
238 (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
241 #define sdc_is_busy() (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
242 #define sdc_is_cmd_busy() (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
244 #define sdc_send_cmd(cmd, arg) \
246 sdr_write32(SDC_ARG, (arg)); \
247 sdr_write32(SDC_CMD, (cmd)); \
250 // can modify to read h/w register.
251 //#define is_card_present(h) ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);
252 #define is_card_present(h) (((struct msdc_host *)(h))->card_inserted)
256 #define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
258 #define PHYSADDR(a) ((a) & 0x1fffffff)
261 static unsigned int msdc_do_command(struct msdc_host
*host
,
262 struct mmc_command
*cmd
,
264 unsigned long timeout
);
266 static int msdc_tune_cmdrsp(struct msdc_host
*host
, struct mmc_command
*cmd
);
268 #ifdef MT6575_SD_DEBUG
269 static void msdc_dump_card_status(struct msdc_host
*host
, u32 status
)
271 /* N_MSG is currently a no-op */
273 static char *state
[] = {
292 if (status
& R1_OUT_OF_RANGE
)
293 N_MSG(RSP
, "[CARD_STATUS] Out of Range");
294 if (status
& R1_ADDRESS_ERROR
)
295 N_MSG(RSP
, "[CARD_STATUS] Address Error");
296 if (status
& R1_BLOCK_LEN_ERROR
)
297 N_MSG(RSP
, "[CARD_STATUS] Block Len Error");
298 if (status
& R1_ERASE_SEQ_ERROR
)
299 N_MSG(RSP
, "[CARD_STATUS] Erase Seq Error");
300 if (status
& R1_ERASE_PARAM
)
301 N_MSG(RSP
, "[CARD_STATUS] Erase Param");
302 if (status
& R1_WP_VIOLATION
)
303 N_MSG(RSP
, "[CARD_STATUS] WP Violation");
304 if (status
& R1_CARD_IS_LOCKED
)
305 N_MSG(RSP
, "[CARD_STATUS] Card is Locked");
306 if (status
& R1_LOCK_UNLOCK_FAILED
)
307 N_MSG(RSP
, "[CARD_STATUS] Lock/Unlock Failed");
308 if (status
& R1_COM_CRC_ERROR
)
309 N_MSG(RSP
, "[CARD_STATUS] Command CRC Error");
310 if (status
& R1_ILLEGAL_COMMAND
)
311 N_MSG(RSP
, "[CARD_STATUS] Illegal Command");
312 if (status
& R1_CARD_ECC_FAILED
)
313 N_MSG(RSP
, "[CARD_STATUS] Card ECC Failed");
314 if (status
& R1_CC_ERROR
)
315 N_MSG(RSP
, "[CARD_STATUS] CC Error");
316 if (status
& R1_ERROR
)
317 N_MSG(RSP
, "[CARD_STATUS] Error");
318 if (status
& R1_UNDERRUN
)
319 N_MSG(RSP
, "[CARD_STATUS] Underrun");
320 if (status
& R1_OVERRUN
)
321 N_MSG(RSP
, "[CARD_STATUS] Overrun");
322 if (status
& R1_CID_CSD_OVERWRITE
)
323 N_MSG(RSP
, "[CARD_STATUS] CID/CSD Overwrite");
324 if (status
& R1_WP_ERASE_SKIP
)
325 N_MSG(RSP
, "[CARD_STATUS] WP Eraser Skip");
326 if (status
& R1_CARD_ECC_DISABLED
)
327 N_MSG(RSP
, "[CARD_STATUS] Card ECC Disabled");
328 if (status
& R1_ERASE_RESET
)
329 N_MSG(RSP
, "[CARD_STATUS] Erase Reset");
330 if (status
& R1_READY_FOR_DATA
)
331 N_MSG(RSP
, "[CARD_STATUS] Ready for Data");
332 if (status
& R1_SWITCH_ERROR
)
333 N_MSG(RSP
, "[CARD_STATUS] Switch error");
334 if (status
& R1_APP_CMD
)
335 N_MSG(RSP
, "[CARD_STATUS] App Command");
337 N_MSG(RSP
, "[CARD_STATUS] '%s' State", state
[R1_CURRENT_STATE(status
)]);
340 static void msdc_dump_ocr_reg(struct msdc_host
*host
, u32 resp
)
343 N_MSG(RSP
, "[OCR] Low Voltage Range");
344 if (resp
& (1 << 15))
345 N_MSG(RSP
, "[OCR] 2.7-2.8 volt");
346 if (resp
& (1 << 16))
347 N_MSG(RSP
, "[OCR] 2.8-2.9 volt");
348 if (resp
& (1 << 17))
349 N_MSG(RSP
, "[OCR] 2.9-3.0 volt");
350 if (resp
& (1 << 18))
351 N_MSG(RSP
, "[OCR] 3.0-3.1 volt");
352 if (resp
& (1 << 19))
353 N_MSG(RSP
, "[OCR] 3.1-3.2 volt");
354 if (resp
& (1 << 20))
355 N_MSG(RSP
, "[OCR] 3.2-3.3 volt");
356 if (resp
& (1 << 21))
357 N_MSG(RSP
, "[OCR] 3.3-3.4 volt");
358 if (resp
& (1 << 22))
359 N_MSG(RSP
, "[OCR] 3.4-3.5 volt");
360 if (resp
& (1 << 23))
361 N_MSG(RSP
, "[OCR] 3.5-3.6 volt");
362 if (resp
& (1 << 24))
363 N_MSG(RSP
, "[OCR] Switching to 1.8V Accepted (S18A)");
364 if (resp
& (1 << 30))
365 N_MSG(RSP
, "[OCR] Card Capacity Status (CCS)");
366 if (resp
& (1 << 31))
367 N_MSG(RSP
, "[OCR] Card Power Up Status (Idle)");
369 N_MSG(RSP
, "[OCR] Card Power Up Status (Busy)");
372 static void msdc_dump_rca_resp(struct msdc_host
*host
, u32 resp
)
374 u32 status
= (((resp
>> 15) & 0x1) << 23) |
375 (((resp
>> 14) & 0x1) << 22) |
376 (((resp
>> 13) & 0x1) << 19) |
379 N_MSG(RSP
, "[RCA] 0x%.4x", resp
>> 16);
380 msdc_dump_card_status(host
, status
);
383 static void msdc_dump_io_resp(struct msdc_host
*host
, u32 resp
)
385 u32 flags
= (resp
>> 8) & 0xFF;
387 char *state
[] = {"DIS", "CMD", "TRN", "RFU"};
389 if (flags
& (1 << 7))
390 N_MSG(RSP
, "[IO] COM_CRC_ERR");
391 if (flags
& (1 << 6))
392 N_MSG(RSP
, "[IO] Illgal command");
393 if (flags
& (1 << 3))
394 N_MSG(RSP
, "[IO] Error");
395 if (flags
& (1 << 2))
396 N_MSG(RSP
, "[IO] RFU");
397 if (flags
& (1 << 1))
398 N_MSG(RSP
, "[IO] Function number error");
399 if (flags
& (1 << 0))
400 N_MSG(RSP
, "[IO] Out of range");
402 N_MSG(RSP
, "[IO] State: %s, Data:0x%x", state
[(resp
>> 12) & 0x3], resp
& 0xFF);
406 static void msdc_set_timeout(struct msdc_host
*host
, u32 ns
, u32 clks
)
408 void __iomem
*base
= host
->base
;
411 host
->timeout_ns
= ns
;
412 host
->timeout_clks
= clks
;
414 clk_ns
= 1000000000UL / host
->sclk
;
415 timeout
= ns
/ clk_ns
+ clks
;
416 timeout
= timeout
>> 16; /* in 65536 sclk cycle unit */
417 timeout
= timeout
> 1 ? timeout
- 1 : 0;
418 timeout
= timeout
> 255 ? 255 : timeout
;
420 sdr_set_field(SDC_CFG
, SDC_CFG_DTOC
, timeout
);
422 N_MSG(OPS
, "Set read data timeout: %dns %dclks -> %d x 65536 cycles",
423 ns
, clks
, timeout
+ 1);
426 static void msdc_tasklet_card(struct work_struct
*work
)
428 struct msdc_host
*host
= (struct msdc_host
*)container_of(work
,
429 struct msdc_host
, card_delaywork
.work
);
430 void __iomem
*base
= host
->base
;
435 spin_lock(&host
->lock
);
437 status
= sdr_read32(MSDC_PS
);
439 inserted
= (status
& MSDC_PS_CDSTS
) ? 0 : 1;
441 inserted
= (status
& MSDC_PS_CDSTS
) ? 1 : 0;
444 change
= host
->card_inserted
^ inserted
;
445 host
->card_inserted
= inserted
;
447 if (change
&& !host
->suspend
) {
449 host
->mmc
->f_max
= HOST_MAX_MCLK
; // work around
450 mmc_detect_change(host
->mmc
, msecs_to_jiffies(20));
452 #else /* Make sure: handle the last interrupt */
453 host
->card_inserted
= inserted
;
455 if (!host
->suspend
) {
456 host
->mmc
->f_max
= HOST_MAX_MCLK
;
457 mmc_detect_change(host
->mmc
, msecs_to_jiffies(20));
460 IRQ_MSG("card found<%s>", inserted
? "inserted" : "removed");
463 spin_unlock(&host
->lock
);
466 #if 0 /* --- by chhung */
468 static u8 clk_src_bit
[4] = {
472 static void msdc_select_clksrc(struct msdc_host
*host
, unsigned char clksrc
)
475 void __iomem
*base
= host
->base
;
478 INIT_MSG("set clock source to <%d>", clksrc
);
480 val
= sdr_read32(MSDC_CLKSRC_REG
);
481 if (sdr_read32(MSDC_ECO_VER
) >= 4) {
482 val
&= ~(0x3 << clk_src_bit
[host
->id
]);
483 val
|= clksrc
<< clk_src_bit
[host
->id
];
485 val
&= ~0x3; val
|= clksrc
;
487 sdr_write32(MSDC_CLKSRC_REG
, val
);
489 host
->hclk
= hclks
[clksrc
];
490 host
->hw
->clk_src
= clksrc
;
492 #endif /* end of --- */
494 static void msdc_set_mclk(struct msdc_host
*host
, int ddr
, unsigned int hz
)
496 //struct msdc_hw *hw = host->hw;
497 void __iomem
*base
= host
->base
;
502 u32 hclk
= host
->hclk
;
503 //u8 clksrc = hw->clk_src;
505 if (!hz
) { // set mmc system clock to 0 ?
506 //ERR_MSG("set mclk to 0!!!");
511 msdc_irq_save(flags
);
514 mode
= 0x2; /* ddr mode and use divisor */
515 if (hz
>= (hclk
>> 2)) {
516 div
= 1; /* mean div = 1/4 */
517 sclk
= hclk
>> 2; /* sclk = clk / 4 */
519 div
= (hclk
+ ((hz
<< 2) - 1)) / (hz
<< 2);
520 sclk
= (hclk
>> 2) / div
;
522 } else if (hz
>= hclk
) { /* bug fix */
523 mode
= 0x1; /* no divisor and divisor is ignored */
527 mode
= 0x0; /* use divisor */
528 if (hz
>= (hclk
>> 1)) {
529 div
= 0; /* mean div = 1/2 */
530 sclk
= hclk
>> 1; /* sclk = clk / 2 */
532 div
= (hclk
+ ((hz
<< 2) - 1)) / (hz
<< 2);
533 sclk
= (hclk
>> 2) / div
;
537 /* set clock mode and divisor */
538 sdr_set_field(MSDC_CFG
, MSDC_CFG_CKMOD
, mode
);
539 sdr_set_field(MSDC_CFG
, MSDC_CFG_CKDIV
, div
);
541 /* wait clock stable */
542 while (!(sdr_read32(MSDC_CFG
) & MSDC_CFG_CKSTB
))
547 msdc_set_timeout(host
, host
->timeout_ns
, host
->timeout_clks
); // need?
549 INIT_MSG("================");
550 INIT_MSG("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>", hz
/ 1000, hclk
/ 1000, sclk
/ 1000);
551 INIT_MSG("================");
553 msdc_irq_restore(flags
);
556 /* Fix me. when need to abort */
557 static void msdc_abort_data(struct msdc_host
*host
)
559 void __iomem
*base
= host
->base
;
560 struct mmc_command
*stop
= host
->mrq
->stop
;
562 ERR_MSG("Need to Abort.");
568 // need to check FIFO count 0 ?
570 if (stop
) { /* try to stop, but may not success */
571 ERR_MSG("stop when abort CMD<%d>", stop
->opcode
);
572 (void)msdc_do_command(host
, stop
, 0, CMD_TIMEOUT
);
575 //if (host->mclk >= 25000000) {
576 // msdc_set_mclk(host, 0, host->mclk >> 1);
580 #if 0 /* --- by chhung */
581 static void msdc_pin_config(struct msdc_host
*host
, int mode
)
583 struct msdc_hw
*hw
= host
->hw
;
584 void __iomem
*base
= host
->base
;
585 int pull
= (mode
== MSDC_PIN_PULL_UP
) ? GPIO_PULL_UP
: GPIO_PULL_DOWN
;
588 if (hw
->flags
& MSDC_WP_PIN_EN
) {
589 if (hw
->config_gpio_pin
) /* NULL */
590 hw
->config_gpio_pin(MSDC_WP_PIN
, pull
);
594 case MSDC_PIN_PULL_UP
:
595 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 1); /* Check & FIXME */
596 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
597 sdr_set_field(MSDC_PAD_CTL1
, MSDC_PAD_CTL1_CMDPU
, 1);
598 sdr_set_field(MSDC_PAD_CTL1
, MSDC_PAD_CTL1_CMDPD
, 0);
599 sdr_set_field(MSDC_PAD_CTL2
, MSDC_PAD_CTL2_DATPU
, 1);
600 sdr_set_field(MSDC_PAD_CTL2
, MSDC_PAD_CTL2_DATPD
, 0);
602 case MSDC_PIN_PULL_DOWN
:
603 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
604 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 1); /* Check & FIXME */
605 sdr_set_field(MSDC_PAD_CTL1
, MSDC_PAD_CTL1_CMDPU
, 0);
606 sdr_set_field(MSDC_PAD_CTL1
, MSDC_PAD_CTL1_CMDPD
, 1);
607 sdr_set_field(MSDC_PAD_CTL2
, MSDC_PAD_CTL2_DATPU
, 0);
608 sdr_set_field(MSDC_PAD_CTL2
, MSDC_PAD_CTL2_DATPD
, 1);
610 case MSDC_PIN_PULL_NONE
:
612 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPU, 0); /* Check & FIXME */
613 //sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKPD, 0); /* Check & FIXME */
614 sdr_set_field(MSDC_PAD_CTL1
, MSDC_PAD_CTL1_CMDPU
, 0);
615 sdr_set_field(MSDC_PAD_CTL1
, MSDC_PAD_CTL1_CMDPD
, 0);
616 sdr_set_field(MSDC_PAD_CTL2
, MSDC_PAD_CTL2_DATPU
, 0);
617 sdr_set_field(MSDC_PAD_CTL2
, MSDC_PAD_CTL2_DATPD
, 0);
621 N_MSG(CFG
, "Pins mode(%d), down(%d), up(%d)",
622 mode
, MSDC_PIN_PULL_DOWN
, MSDC_PIN_PULL_UP
);
625 void msdc_pin_reset(struct msdc_host
*host
, int mode
)
627 struct msdc_hw
*hw
= (struct msdc_hw
*)host
->hw
;
628 void __iomem
*base
= host
->base
;
629 int pull
= (mode
== MSDC_PIN_PULL_UP
) ? GPIO_PULL_UP
: GPIO_PULL_DOWN
;
631 /* Config reset pin */
632 if (hw
->flags
& MSDC_RST_PIN_EN
) {
633 if (hw
->config_gpio_pin
) /* NULL */
634 hw
->config_gpio_pin(MSDC_RST_PIN
, pull
);
636 if (mode
== MSDC_PIN_PULL_UP
)
637 sdr_clr_bits(EMMC_IOCON
, EMMC_IOCON_BOOTRST
);
639 sdr_set_bits(EMMC_IOCON
, EMMC_IOCON_BOOTRST
);
643 static void msdc_core_power(struct msdc_host
*host
, int on
)
645 N_MSG(CFG
, "Turn %s %s power (copower: %d -> %d)",
646 on
? "on" : "off", "core", host
->core_power
, on
);
648 if (on
&& host
->core_power
== 0) {
650 host
->core_power
= 1;
652 } else if (!on
&& host
->core_power
== 1) {
653 msdc_vcore_off(host
);
654 host
->core_power
= 0;
659 static void msdc_host_power(struct msdc_host
*host
, int on
)
661 N_MSG(CFG
, "Turn %s %s power ", on
? "on" : "off", "host");
664 //msdc_core_power(host, 1); // need do card detection.
665 msdc_pin_reset(host
, MSDC_PIN_PULL_UP
);
667 msdc_pin_reset(host
, MSDC_PIN_PULL_DOWN
);
668 //msdc_core_power(host, 0);
672 static void msdc_card_power(struct msdc_host
*host
, int on
)
674 N_MSG(CFG
, "Turn %s %s power ", on
? "on" : "off", "card");
677 msdc_pin_config(host
, MSDC_PIN_PULL_UP
);
678 //msdc_vdd_on(host); // need todo card detection.
681 //msdc_vdd_off(host);
682 msdc_pin_config(host
, MSDC_PIN_PULL_DOWN
);
687 static void msdc_set_power_mode(struct msdc_host
*host
, u8 mode
)
689 N_MSG(CFG
, "Set power mode(%d)", mode
);
691 if (host
->power_mode
== MMC_POWER_OFF
&& mode
!= MMC_POWER_OFF
) {
692 msdc_host_power(host
, 1);
693 msdc_card_power(host
, 1);
694 } else if (host
->power_mode
!= MMC_POWER_OFF
&& mode
== MMC_POWER_OFF
) {
695 msdc_card_power(host
, 0);
696 msdc_host_power(host
, 0);
698 host
->power_mode
= mode
;
700 #endif /* end of --- */
704 register as callback function of WIFI(combo_sdio_register_pm) .
705 can called by msdc_drv_suspend/resume too.
707 static void msdc_pm(pm_message_t state
, void *data
)
709 struct msdc_host
*host
= (struct msdc_host
*)data
;
710 int evt
= state
.event
;
712 if (evt
== PM_EVENT_USER_RESUME
|| evt
== PM_EVENT_USER_SUSPEND
) {
713 INIT_MSG("USR_%s: suspend<%d> power<%d>",
714 evt
== PM_EVENT_USER_RESUME
? "EVENT_USER_RESUME" : "EVENT_USER_SUSPEND",
715 host
->suspend
, host
->power_mode
);
718 if (evt
== PM_EVENT_SUSPEND
|| evt
== PM_EVENT_USER_SUSPEND
) {
719 if (host
->suspend
) /* already suspend */ /* default 0*/
722 /* for memory card. already power off by mmc */
723 if (evt
== PM_EVENT_SUSPEND
&& host
->power_mode
== MMC_POWER_OFF
)
727 host
->pm_state
= state
; /* default PMSG_RESUME */
729 } else if (evt
== PM_EVENT_RESUME
|| evt
== PM_EVENT_USER_RESUME
) {
730 if (!host
->suspend
) {
731 //ERR_MSG("warning: already resume");
735 /* No PM resume when USR suspend */
736 if (evt
== PM_EVENT_RESUME
&& host
->pm_state
.event
== PM_EVENT_USER_SUSPEND
) {
737 ERR_MSG("PM Resume when in USR Suspend"); /* won't happen. */
742 host
->pm_state
= state
;
748 /*--------------------------------------------------------------------------*/
749 /* mmc_host_ops members */
750 /*--------------------------------------------------------------------------*/
751 static unsigned int msdc_command_start(struct msdc_host
*host
,
752 struct mmc_command
*cmd
,
753 int tune
, /* not used */
754 unsigned long timeout
)
756 void __iomem
*base
= host
->base
;
757 u32 opcode
= cmd
->opcode
;
759 u32 wints
= MSDC_INT_CMDRDY
| MSDC_INT_RSPCRCERR
| MSDC_INT_CMDTMO
|
760 MSDC_INT_ACMDRDY
| MSDC_INT_ACMDCRCERR
| MSDC_INT_ACMDTMO
|
761 MSDC_INT_ACMD19_DONE
;
766 /* Protocol layer does not provide response type, but our hardware needs
767 * to know exact type, not just size!
769 if (opcode
== MMC_SEND_OP_COND
|| opcode
== SD_APP_OP_COND
) {
771 } else if (opcode
== MMC_SET_RELATIVE_ADDR
) {
772 resp
= (mmc_cmd_type(cmd
) == MMC_CMD_BCR
) ? RESP_R6
: RESP_R1
;
773 } else if (opcode
== MMC_FAST_IO
) {
775 } else if (opcode
== MMC_GO_IRQ_STATE
) {
777 } else if (opcode
== MMC_SELECT_CARD
) {
778 resp
= (cmd
->arg
!= 0) ? RESP_R1B
: RESP_NONE
;
779 } else if (opcode
== SD_IO_RW_DIRECT
|| opcode
== SD_IO_RW_EXTENDED
) {
780 resp
= RESP_R1
; /* SDIO workaround. */
781 } else if (opcode
== SD_SEND_IF_COND
&& (mmc_cmd_type(cmd
) == MMC_CMD_BCR
)) {
784 switch (mmc_resp_type(cmd
)) {
806 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
807 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
809 rawcmd
= opcode
| msdc_rsp
[resp
] << 7 | host
->blksz
<< 16;
811 if (opcode
== MMC_READ_MULTIPLE_BLOCK
) {
813 } else if (opcode
== MMC_READ_SINGLE_BLOCK
) {
815 } else if (opcode
== MMC_WRITE_MULTIPLE_BLOCK
) {
816 rawcmd
|= ((2 << 11) | (1 << 13));
817 } else if (opcode
== MMC_WRITE_BLOCK
) {
818 rawcmd
|= ((1 << 11) | (1 << 13));
819 } else if (opcode
== SD_IO_RW_EXTENDED
) {
820 if (cmd
->data
->flags
& MMC_DATA_WRITE
)
822 if (cmd
->data
->blocks
> 1)
826 } else if (opcode
== SD_IO_RW_DIRECT
&& cmd
->flags
== (unsigned int)-1) {
828 } else if ((opcode
== SD_APP_SEND_SCR
) ||
829 (opcode
== SD_APP_SEND_NUM_WR_BLKS
) ||
830 (opcode
== SD_SWITCH
&& (mmc_cmd_type(cmd
) == MMC_CMD_ADTC
)) ||
831 (opcode
== SD_APP_SD_STATUS
&& (mmc_cmd_type(cmd
) == MMC_CMD_ADTC
)) ||
832 (opcode
== MMC_SEND_EXT_CSD
&& (mmc_cmd_type(cmd
) == MMC_CMD_ADTC
))) {
834 } else if (opcode
== MMC_STOP_TRANSMISSION
) {
836 rawcmd
&= ~(0x0FFF << 16);
839 N_MSG(CMD
, "CMD<%d><0x%.8x> Arg<0x%.8x>", opcode
, rawcmd
, cmd
->arg
);
841 tmo
= jiffies
+ timeout
;
843 if (opcode
== MMC_SEND_STATUS
) {
845 if (!sdc_is_cmd_busy())
848 if (time_after(jiffies
, tmo
)) {
849 ERR_MSG("XXX cmd_busy timeout: before CMD<%d>", opcode
);
850 cmd
->error
= -ETIMEDOUT
;
859 if (time_after(jiffies
, tmo
)) {
860 ERR_MSG("XXX sdc_busy timeout: before CMD<%d>", opcode
);
861 cmd
->error
= -ETIMEDOUT
;
868 //BUG_ON(in_interrupt());
870 host
->cmd_rsp
= resp
;
872 init_completion(&host
->cmd_done
);
874 sdr_set_bits(MSDC_INTEN
, wints
);
875 sdc_send_cmd(rawcmd
, cmd
->arg
);
881 static unsigned int msdc_command_resp(struct msdc_host
*host
,
882 struct mmc_command
*cmd
,
884 unsigned long timeout
)
885 __must_hold(&host
->lock
)
887 void __iomem
*base
= host
->base
;
888 u32 opcode
= cmd
->opcode
;
891 u32 wints
= MSDC_INT_CMDRDY
| MSDC_INT_RSPCRCERR
| MSDC_INT_CMDTMO
|
892 MSDC_INT_ACMDRDY
| MSDC_INT_ACMDCRCERR
| MSDC_INT_ACMDTMO
|
893 MSDC_INT_ACMD19_DONE
;
895 resp
= host
->cmd_rsp
;
897 BUG_ON(in_interrupt());
898 //init_completion(&host->cmd_done);
899 //sdr_set_bits(MSDC_INTEN, wints);
901 spin_unlock(&host
->lock
);
902 if (!wait_for_completion_timeout(&host
->cmd_done
, 10 * timeout
)) {
903 ERR_MSG("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>", opcode
, cmd
->arg
);
904 cmd
->error
= -ETIMEDOUT
;
907 spin_lock(&host
->lock
);
909 sdr_clr_bits(MSDC_INTEN
, wints
);
913 #ifdef MT6575_SD_DEBUG
916 N_MSG(RSP
, "CMD_RSP(%d): %d RSP(%d)", opcode
, cmd
->error
, resp
);
919 N_MSG(RSP
, "CMD_RSP(%d): %d RSP(%d)= %.8x %.8x %.8x %.8x",
920 opcode
, cmd
->error
, resp
, cmd
->resp
[0], cmd
->resp
[1],
921 cmd
->resp
[2], cmd
->resp
[3]);
923 default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
924 N_MSG(RSP
, "CMD_RSP(%d): %d RSP(%d)= 0x%.8x",
925 opcode
, cmd
->error
, resp
, cmd
->resp
[0]);
926 if (cmd
->error
== 0) {
930 msdc_dump_card_status(host
, cmd
->resp
[0]);
933 msdc_dump_ocr_reg(host
, cmd
->resp
[0]);
936 msdc_dump_io_resp(host
, cmd
->resp
[0]);
939 msdc_dump_rca_resp(host
, cmd
->resp
[0]);
947 /* do we need to save card's RCA when SD_SEND_RELATIVE_ADDR */
952 /* memory card CRC */
953 if (host
->hw
->flags
& MSDC_REMOVABLE
&& cmd
->error
== -EIO
) {
954 if (sdr_read32(SDC_CMD
) & 0x1800) { /* check if has data phase */
955 msdc_abort_data(host
);
962 cmd
->error
= msdc_tune_cmdrsp(host
, cmd
);
966 /* if (resp == RESP_R1B) {
967 while ((sdr_read32(MSDC_PS) & 0x10000) != 0x10000);
969 /* CMD12 Error Handle */
974 static unsigned int msdc_do_command(struct msdc_host
*host
,
975 struct mmc_command
*cmd
,
977 unsigned long timeout
)
979 if (msdc_command_start(host
, cmd
, tune
, timeout
))
982 if (msdc_command_resp(host
, cmd
, tune
, timeout
))
987 N_MSG(CMD
, " return<%d> resp<0x%.8x>", cmd
->error
, cmd
->resp
[0]);
991 #if 0 /* --- by chhung */
992 // DMA resume / start / stop
993 static void msdc_dma_resume(struct msdc_host
*host
)
995 void __iomem
*base
= host
->base
;
997 sdr_set_field(MSDC_DMA_CTRL
, MSDC_DMA_CTRL_RESUME
, 1);
999 N_MSG(DMA
, "DMA resume");
1001 #endif /* end of --- */
1003 static void msdc_dma_start(struct msdc_host
*host
)
1005 void __iomem
*base
= host
->base
;
1006 u32 wints
= MSDC_INTEN_XFER_COMPL
| MSDC_INTEN_DATTMO
| MSDC_INTEN_DATCRCERR
;
1008 sdr_set_bits(MSDC_INTEN
, wints
);
1009 //dsb(); /* --- by chhung */
1010 sdr_set_field(MSDC_DMA_CTRL
, MSDC_DMA_CTRL_START
, 1);
1012 N_MSG(DMA
, "DMA start");
1015 static void msdc_dma_stop(struct msdc_host
*host
)
1017 void __iomem
*base
= host
->base
;
1019 u32 wints
= MSDC_INTEN_XFER_COMPL
| MSDC_INTEN_DATTMO
| MSDC_INTEN_DATCRCERR
;
1021 N_MSG(DMA
, "DMA status: 0x%.8x", sdr_read32(MSDC_DMA_CFG
));
1022 //while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
1024 sdr_set_field(MSDC_DMA_CTRL
, MSDC_DMA_CTRL_STOP
, 1);
1025 while (sdr_read32(MSDC_DMA_CFG
) & MSDC_DMA_CFG_STS
)
1028 //dsb(); /* --- by chhung */
1029 sdr_clr_bits(MSDC_INTEN
, wints
); /* Not just xfer_comp */
1031 N_MSG(DMA
, "DMA stop");
1035 static u8
msdc_dma_calcs(u8
*buf
, u32 len
)
1039 for (i
= 0; i
< len
; i
++)
1041 return 0xFF - (u8
)sum
;
1044 /* gpd bd setup + dma registers */
1045 static void msdc_dma_config(struct msdc_host
*host
, struct msdc_dma
*dma
)
1047 void __iomem
*base
= host
->base
;
1048 //u32 i, j, num, bdlen, arg, xfersz;
1050 struct scatterlist
*sg
;
1054 switch (dma
->mode
) {
1055 case MSDC_MODE_DMA_BASIC
:
1056 BUG_ON(host
->xfer_size
> 65535);
1057 BUG_ON(dma
->sglen
!= 1);
1058 sdr_write32(MSDC_DMA_SA
, PHYSADDR(sg_dma_address(sg
)));
1059 sdr_set_field(MSDC_DMA_CTRL
, MSDC_DMA_CTRL_LASTBUF
, 1);
1060 //#if defined (CONFIG_RALINK_MT7620)
1061 if (ralink_soc
== MT762X_SOC_MT7620A
)
1062 sdr_set_field(MSDC_DMA_CTRL
, MSDC_DMA_CTRL_XFERSZ
, sg_dma_len(sg
));
1063 //#elif defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
1065 sdr_write32((void __iomem
*)(RALINK_MSDC_BASE
+ 0xa8), sg_dma_len(sg
));
1067 sdr_set_field(MSDC_DMA_CTRL
, MSDC_DMA_CTRL_BRUSTSZ
,
1069 sdr_set_field(MSDC_DMA_CTRL
, MSDC_DMA_CTRL_MODE
, 0);
1071 case MSDC_MODE_DMA_DESC
:
1073 /* calculate the required number of gpd */
1074 num
= (dma
->sglen
+ MAX_BD_PER_GPD
- 1) / MAX_BD_PER_GPD
;
1082 gpd
->hwo
= 1; /* hw will clear it */
1084 gpd
->chksum
= 0; /* need to clear first. */
1085 gpd
->chksum
= msdc_dma_calcs((u8
*)gpd
, 16);
1088 for_each_sg(dma
->sg
, sg
, dma
->sglen
, j
) {
1091 bd
[j
].ptr
= (void *)sg_dma_address(sg
);
1092 bd
[j
].buflen
= sg_dma_len(sg
);
1094 if (j
== dma
->sglen
- 1)
1095 bd
[j
].eol
= 1; /* the last bd */
1099 bd
[j
].chksum
= 0; /* checksume need to clear first */
1100 bd
[j
].chksum
= msdc_dma_calcs((u8
*)(&bd
[j
]), 16);
1103 sdr_set_field(MSDC_DMA_CFG
, MSDC_DMA_CFG_DECSEN
, 1);
1104 sdr_set_field(MSDC_DMA_CTRL
, MSDC_DMA_CTRL_BRUSTSZ
,
1106 sdr_set_field(MSDC_DMA_CTRL
, MSDC_DMA_CTRL_MODE
, 1);
1108 sdr_write32(MSDC_DMA_SA
, PHYSADDR((u32
)dma
->gpd_addr
));
1115 N_MSG(DMA
, "DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL
));
1116 N_MSG(DMA
, "DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG
));
1117 N_MSG(DMA
, "DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA
));
1121 static void msdc_dma_setup(struct msdc_host
*host
, struct msdc_dma
*dma
,
1122 struct scatterlist
*sg
, unsigned int sglen
)
1124 BUG_ON(sglen
> MAX_BD_NUM
); /* not support currently */
1129 dma
->mode
= MSDC_MODE_DMA_DESC
;
1131 N_MSG(DMA
, "DMA mode<%d> sglen<%d> xfersz<%d>", dma
->mode
, dma
->sglen
,
1134 msdc_dma_config(host
, dma
);
1137 static int msdc_do_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1138 __must_hold(&host
->lock
)
1140 struct msdc_host
*host
= mmc_priv(mmc
);
1141 struct mmc_command
*cmd
;
1142 struct mmc_data
*data
;
1143 void __iomem
*base
= host
->base
;
1145 int read
= 1, send_type
= 0;
1150 BUG_ON(mmc
== NULL
);
1151 BUG_ON(mrq
== NULL
);
1156 data
= mrq
->cmd
->data
;
1158 #if 0 /* --- by chhung */
1160 N_MSG(OPS
, "enable clock!");
1161 msdc_ungate_clock(host
->id
);
1163 #endif /* end of --- */
1166 send_type
= SND_CMD
;
1167 if (msdc_do_command(host
, cmd
, 1, CMD_TIMEOUT
) != 0)
1170 BUG_ON(data
->blksz
> HOST_MAX_BLKSZ
);
1171 send_type
= SND_DAT
;
1174 read
= data
->flags
& MMC_DATA_READ
? 1 : 0;
1176 host
->xfer_size
= data
->blocks
* data
->blksz
;
1177 host
->blksz
= data
->blksz
;
1180 if ((host
->timeout_ns
!= data
->timeout_ns
) ||
1181 (host
->timeout_clks
!= data
->timeout_clks
)) {
1182 msdc_set_timeout(host
, data
->timeout_ns
, data
->timeout_clks
);
1186 sdr_write32(SDC_BLK_NUM
, data
->blocks
);
1187 //msdc_clr_fifo(); /* no need */
1189 msdc_dma_on(); /* enable DMA mode first!! */
1190 init_completion(&host
->xfer_done
);
1192 /* start the command first*/
1193 if (msdc_command_start(host
, cmd
, 1, CMD_TIMEOUT
) != 0)
1196 data
->sg_count
= dma_map_sg(mmc_dev(mmc
), data
->sg
,
1198 mmc_get_dma_dir(data
));
1199 msdc_dma_setup(host
, &host
->dma
, data
->sg
,
1202 /* then wait command done */
1203 if (msdc_command_resp(host
, cmd
, 1, CMD_TIMEOUT
) != 0)
1206 /* for read, the data coming too fast, then CRC error
1207 start DMA no business with CRC. */
1208 //init_completion(&host->xfer_done);
1209 msdc_dma_start(host
);
1211 spin_unlock(&host
->lock
);
1212 if (!wait_for_completion_timeout(&host
->xfer_done
, DAT_TIMEOUT
)) {
1213 ERR_MSG("XXX CMD<%d> wait xfer_done<%d> timeout!!", cmd
->opcode
, data
->blocks
* data
->blksz
);
1214 ERR_MSG(" DMA_SA = 0x%x", sdr_read32(MSDC_DMA_SA
));
1215 ERR_MSG(" DMA_CA = 0x%x", sdr_read32(MSDC_DMA_CA
));
1216 ERR_MSG(" DMA_CTRL = 0x%x", sdr_read32(MSDC_DMA_CTRL
));
1217 ERR_MSG(" DMA_CFG = 0x%x", sdr_read32(MSDC_DMA_CFG
));
1218 data
->error
= -ETIMEDOUT
;
1220 msdc_reset_hw(host
);
1224 spin_lock(&host
->lock
);
1225 msdc_dma_stop(host
);
1227 /* Last: stop transfer */
1229 if (msdc_do_command(host
, data
->stop
, 0, CMD_TIMEOUT
) != 0)
1237 dma_unmap_sg(mmc_dev(mmc
), data
->sg
, data
->sg_len
,
1238 mmc_get_dma_dir(data
));
1241 #if 0 // don't stop twice!
1242 if (host
->hw
->flags
& MSDC_REMOVABLE
&& data
->error
) {
1243 msdc_abort_data(host
);
1244 /* reset in IRQ, stop command has issued. -> No need */
1248 N_MSG(OPS
, "CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>", cmd
->opcode
, (dma
? "dma" : "pio"),
1249 (read
? "read " : "write"), data
->blksz
, data
->blocks
, data
->error
);
1252 #if 0 /* --- by chhung */
1255 if (send_type
== SND_CMD
) {
1256 if (cmd
->opcode
== MMC_SEND_STATUS
) {
1257 if ((cmd
->resp
[0] & CARD_READY_FOR_DATA
) || (CARD_CURRENT_STATE(cmd
->resp
[0]) != 7)) {
1258 N_MSG(OPS
, "disable clock, CMD13 IDLE");
1259 msdc_gate_clock(host
->id
);
1262 N_MSG(OPS
, "disable clock, CMD<%d>", cmd
->opcode
);
1263 msdc_gate_clock(host
->id
);
1267 N_MSG(OPS
, "disable clock!!! Read CMD<%d>", cmd
->opcode
);
1268 msdc_gate_clock(host
->id
);
1273 msdc_gate_clock(host
->id
);
1275 #endif /* end of --- */
1277 if (mrq
->cmd
->error
)
1278 host
->error
= 0x001;
1279 if (mrq
->data
&& mrq
->data
->error
)
1280 host
->error
|= 0x010;
1281 if (mrq
->stop
&& mrq
->stop
->error
)
1282 host
->error
|= 0x100;
1284 //if (host->error) ERR_MSG("host->error<%d>", host->error);
1289 static int msdc_app_cmd(struct mmc_host
*mmc
, struct msdc_host
*host
)
1291 struct mmc_command cmd
;
1292 struct mmc_request mrq
;
1295 memset(&cmd
, 0, sizeof(struct mmc_command
));
1296 cmd
.opcode
= MMC_APP_CMD
;
1297 #if 0 /* bug: we meet mmc->card is null when ACMD6 */
1298 cmd
.arg
= mmc
->card
->rca
<< 16;
1300 cmd
.arg
= host
->app_cmd_arg
;
1302 cmd
.flags
= MMC_RSP_SPI_R1
| MMC_RSP_R1
| MMC_CMD_AC
;
1304 memset(&mrq
, 0, sizeof(struct mmc_request
));
1305 mrq
.cmd
= &cmd
; cmd
.mrq
= &mrq
;
1308 err
= msdc_do_command(host
, &cmd
, 0, CMD_TIMEOUT
);
1312 static int msdc_tune_cmdrsp(struct msdc_host
*host
, struct mmc_command
*cmd
)
1315 void __iomem
*base
= host
->base
;
1316 u32 rsmpl
, cur_rsmpl
, orig_rsmpl
;
1317 u32 rrdly
, cur_rrdly
= 0xffffffff, orig_rrdly
;
1320 /* ==== don't support 3.0 now ====
1322 2: PAD_CMD_RESP_RXDLY[26:22]
1323 ==========================*/
1325 // save the previous tune result
1326 sdr_get_field(MSDC_IOCON
, MSDC_IOCON_RSPL
, &orig_rsmpl
);
1327 sdr_get_field(MSDC_PAD_TUNE
, MSDC_PAD_TUNE_CMDRRDLY
, &orig_rrdly
);
1331 for (rsmpl
= 0; rsmpl
< 2; rsmpl
++) {
1332 /* Lv1: R_SMPL[1] */
1333 cur_rsmpl
= (orig_rsmpl
+ rsmpl
) % 2;
1338 sdr_set_field(MSDC_IOCON
, MSDC_IOCON_RSPL
, cur_rsmpl
);
1340 if (host
->app_cmd
) {
1341 result
= msdc_app_cmd(host
->mmc
, host
);
1343 ERR_MSG("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>",
1344 host
->mrq
->cmd
->opcode
, cur_rrdly
, cur_rsmpl
);
1348 result
= msdc_do_command(host
, cmd
, 0, CMD_TIMEOUT
); // not tune.
1349 ERR_MSG("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>", cmd
->opcode
,
1350 (result
== 0) ? "PASS" : "FAIL", cur_rrdly
, cur_rsmpl
);
1354 if (result
!= -EIO
) {
1355 ERR_MSG("TUNE_CMD<%d> Error<%d> not -EIO", cmd
->opcode
, result
);
1360 if (sdr_read32(SDC_CMD
) & 0x1800) { /* check if has data phase */
1361 msdc_abort_data(host
);
1365 /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */
1366 cur_rrdly
= (orig_rrdly
+ rrdly
+ 1) % 32;
1367 sdr_set_field(MSDC_PAD_TUNE
, MSDC_PAD_TUNE_CMDRRDLY
, cur_rrdly
);
1368 } while (++rrdly
< 32);
1373 /* Support SD2.0 Only */
1374 static int msdc_tune_bread(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1376 struct msdc_host
*host
= mmc_priv(mmc
);
1377 void __iomem
*base
= host
->base
;
1380 u32 rxdly
, cur_rxdly0
, cur_rxdly1
;
1381 u32 dsmpl
, cur_dsmpl
, orig_dsmpl
;
1382 u32 cur_dat0
, cur_dat1
, cur_dat2
, cur_dat3
;
1383 u32 cur_dat4
, cur_dat5
, cur_dat6
, cur_dat7
;
1384 u32 orig_dat0
, orig_dat1
, orig_dat2
, orig_dat3
;
1385 u32 orig_dat4
, orig_dat5
, orig_dat6
, orig_dat7
;
1389 sdr_get_field(MSDC_IOCON
, MSDC_IOCON_DSPL
, &orig_dsmpl
);
1391 /* Tune Method 2. */
1392 sdr_set_field(MSDC_IOCON
, MSDC_IOCON_DDLSEL
, 1);
1396 for (dsmpl
= 0; dsmpl
< 2; dsmpl
++) {
1397 cur_dsmpl
= (orig_dsmpl
+ dsmpl
) % 2;
1402 sdr_set_field(MSDC_IOCON
, MSDC_IOCON_DSPL
, cur_dsmpl
);
1404 if (host
->app_cmd
) {
1405 result
= msdc_app_cmd(host
->mmc
, host
);
1407 ERR_MSG("TUNE_BREAD app_cmd<%d> failed", host
->mrq
->cmd
->opcode
);
1411 result
= msdc_do_request(mmc
, mrq
);
1413 sdr_get_field(SDC_DCRC_STS
,
1414 SDC_DCRC_STS_POS
| SDC_DCRC_STS_NEG
,
1417 dcrc
&= ~SDC_DCRC_STS_NEG
;
1418 ERR_MSG("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>",
1419 (result
== 0 && dcrc
== 0) ? "PASS" : "FAIL", dcrc
,
1420 sdr_read32(MSDC_DAT_RDDLY0
), sdr_read32(MSDC_DAT_RDDLY1
), cur_dsmpl
);
1422 /* Fix me: result is 0, but dcrc is still exist */
1423 if (result
== 0 && dcrc
== 0) {
1426 /* there is a case: command timeout, and data phase not processed */
1427 if (mrq
->data
->error
!= 0 &&
1428 mrq
->data
->error
!= -EIO
) {
1429 ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
1430 result
, mrq
->cmd
->error
, mrq
->data
->error
);
1436 cur_rxdly0
= sdr_read32(MSDC_DAT_RDDLY0
);
1437 cur_rxdly1
= sdr_read32(MSDC_DAT_RDDLY1
);
1439 /* E1 ECO. YD: Reverse */
1440 if (sdr_read32(MSDC_ECO_VER
) >= 4) {
1441 orig_dat0
= (cur_rxdly0
>> 24) & 0x1F;
1442 orig_dat1
= (cur_rxdly0
>> 16) & 0x1F;
1443 orig_dat2
= (cur_rxdly0
>> 8) & 0x1F;
1444 orig_dat3
= (cur_rxdly0
>> 0) & 0x1F;
1445 orig_dat4
= (cur_rxdly1
>> 24) & 0x1F;
1446 orig_dat5
= (cur_rxdly1
>> 16) & 0x1F;
1447 orig_dat6
= (cur_rxdly1
>> 8) & 0x1F;
1448 orig_dat7
= (cur_rxdly1
>> 0) & 0x1F;
1450 orig_dat0
= (cur_rxdly0
>> 0) & 0x1F;
1451 orig_dat1
= (cur_rxdly0
>> 8) & 0x1F;
1452 orig_dat2
= (cur_rxdly0
>> 16) & 0x1F;
1453 orig_dat3
= (cur_rxdly0
>> 24) & 0x1F;
1454 orig_dat4
= (cur_rxdly1
>> 0) & 0x1F;
1455 orig_dat5
= (cur_rxdly1
>> 8) & 0x1F;
1456 orig_dat6
= (cur_rxdly1
>> 16) & 0x1F;
1457 orig_dat7
= (cur_rxdly1
>> 24) & 0x1F;
1461 cur_dat0
= (dcrc
& (1 << 0) || dcrc
& (1 << 8)) ? ((orig_dat0
+ 1) % 32) : orig_dat0
;
1462 cur_dat1
= (dcrc
& (1 << 1) || dcrc
& (1 << 9)) ? ((orig_dat1
+ 1) % 32) : orig_dat1
;
1463 cur_dat2
= (dcrc
& (1 << 2) || dcrc
& (1 << 10)) ? ((orig_dat2
+ 1) % 32) : orig_dat2
;
1464 cur_dat3
= (dcrc
& (1 << 3) || dcrc
& (1 << 11)) ? ((orig_dat3
+ 1) % 32) : orig_dat3
;
1466 cur_dat0
= (dcrc
& (1 << 0)) ? ((orig_dat0
+ 1) % 32) : orig_dat0
;
1467 cur_dat1
= (dcrc
& (1 << 1)) ? ((orig_dat1
+ 1) % 32) : orig_dat1
;
1468 cur_dat2
= (dcrc
& (1 << 2)) ? ((orig_dat2
+ 1) % 32) : orig_dat2
;
1469 cur_dat3
= (dcrc
& (1 << 3)) ? ((orig_dat3
+ 1) % 32) : orig_dat3
;
1471 cur_dat4
= (dcrc
& (1 << 4)) ? ((orig_dat4
+ 1) % 32) : orig_dat4
;
1472 cur_dat5
= (dcrc
& (1 << 5)) ? ((orig_dat5
+ 1) % 32) : orig_dat5
;
1473 cur_dat6
= (dcrc
& (1 << 6)) ? ((orig_dat6
+ 1) % 32) : orig_dat6
;
1474 cur_dat7
= (dcrc
& (1 << 7)) ? ((orig_dat7
+ 1) % 32) : orig_dat7
;
1476 cur_rxdly0
= (cur_dat0
<< 24) | (cur_dat1
<< 16) | (cur_dat2
<< 8) | (cur_dat3
<< 0);
1477 cur_rxdly1
= (cur_dat4
<< 24) | (cur_dat5
<< 16) | (cur_dat6
<< 8) | (cur_dat7
<< 0);
1479 sdr_write32(MSDC_DAT_RDDLY0
, cur_rxdly0
);
1480 sdr_write32(MSDC_DAT_RDDLY1
, cur_rxdly1
);
1482 } while (++rxdly
< 32);
1488 static int msdc_tune_bwrite(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1490 struct msdc_host
*host
= mmc_priv(mmc
);
1491 void __iomem
*base
= host
->base
;
1493 u32 wrrdly
, cur_wrrdly
= 0xffffffff, orig_wrrdly
;
1494 u32 dsmpl
, cur_dsmpl
, orig_dsmpl
;
1495 u32 rxdly
, cur_rxdly0
;
1496 u32 orig_dat0
, orig_dat1
, orig_dat2
, orig_dat3
;
1497 u32 cur_dat0
, cur_dat1
, cur_dat2
, cur_dat3
;
1501 // MSDC_IOCON_DDR50CKD need to check. [Fix me]
1503 sdr_get_field(MSDC_PAD_TUNE
, MSDC_PAD_TUNE_DATWRDLY
, &orig_wrrdly
);
1504 sdr_get_field(MSDC_IOCON
, MSDC_IOCON_DSPL
, &orig_dsmpl
);
1506 /* Tune Method 2. just DAT0 */
1507 sdr_set_field(MSDC_IOCON
, MSDC_IOCON_DDLSEL
, 1);
1508 cur_rxdly0
= sdr_read32(MSDC_DAT_RDDLY0
);
1510 /* E1 ECO. YD: Reverse */
1511 if (sdr_read32(MSDC_ECO_VER
) >= 4) {
1512 orig_dat0
= (cur_rxdly0
>> 24) & 0x1F;
1513 orig_dat1
= (cur_rxdly0
>> 16) & 0x1F;
1514 orig_dat2
= (cur_rxdly0
>> 8) & 0x1F;
1515 orig_dat3
= (cur_rxdly0
>> 0) & 0x1F;
1517 orig_dat0
= (cur_rxdly0
>> 0) & 0x1F;
1518 orig_dat1
= (cur_rxdly0
>> 8) & 0x1F;
1519 orig_dat2
= (cur_rxdly0
>> 16) & 0x1F;
1520 orig_dat3
= (cur_rxdly0
>> 24) & 0x1F;
1527 for (dsmpl
= 0; dsmpl
< 2; dsmpl
++) {
1528 cur_dsmpl
= (orig_dsmpl
+ dsmpl
) % 2;
1533 sdr_set_field(MSDC_IOCON
, MSDC_IOCON_DSPL
, cur_dsmpl
);
1535 if (host
->app_cmd
) {
1536 result
= msdc_app_cmd(host
->mmc
, host
);
1538 ERR_MSG("TUNE_BWRITE app_cmd<%d> failed", host
->mrq
->cmd
->opcode
);
1542 result
= msdc_do_request(mmc
, mrq
);
1544 ERR_MSG("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>",
1545 result
== 0 ? "PASS" : "FAIL",
1546 cur_dsmpl
, cur_wrrdly
, cur_rxdly0
);
1551 /* there is a case: command timeout, and data phase not processed */
1552 if (mrq
->data
->error
!= -EIO
) {
1553 ERR_MSG("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>",
1554 result
, mrq
->cmd
->error
, mrq
->data
->error
);
1559 cur_wrrdly
= (orig_wrrdly
+ wrrdly
+ 1) % 32;
1560 sdr_set_field(MSDC_PAD_TUNE
, MSDC_PAD_TUNE_DATWRDLY
, cur_wrrdly
);
1561 } while (++wrrdly
< 32);
1563 cur_dat0
= (orig_dat0
+ rxdly
) % 32; /* only adjust bit-1 for crc */
1564 cur_dat1
= orig_dat1
;
1565 cur_dat2
= orig_dat2
;
1566 cur_dat3
= orig_dat3
;
1568 cur_rxdly0
= (cur_dat0
<< 24) | (cur_dat1
<< 16) | (cur_dat2
<< 8) | (cur_dat3
<< 0);
1569 sdr_write32(MSDC_DAT_RDDLY0
, cur_rxdly0
);
1570 } while (++rxdly
< 32);
1576 static int msdc_get_card_status(struct mmc_host
*mmc
, struct msdc_host
*host
, u32
*status
)
1578 struct mmc_command cmd
;
1579 struct mmc_request mrq
;
1582 memset(&cmd
, 0, sizeof(struct mmc_command
));
1583 cmd
.opcode
= MMC_SEND_STATUS
;
1585 cmd
.arg
= mmc
->card
->rca
<< 16;
1587 ERR_MSG("cmd13 mmc card is null");
1588 cmd
.arg
= host
->app_cmd_arg
;
1590 cmd
.flags
= MMC_RSP_SPI_R2
| MMC_RSP_R1
| MMC_CMD_AC
;
1592 memset(&mrq
, 0, sizeof(struct mmc_request
));
1593 mrq
.cmd
= &cmd
; cmd
.mrq
= &mrq
;
1596 err
= msdc_do_command(host
, &cmd
, 1, CMD_TIMEOUT
);
1599 *status
= cmd
.resp
[0];
1604 static int msdc_check_busy(struct mmc_host
*mmc
, struct msdc_host
*host
)
1610 err
= msdc_get_card_status(mmc
, host
, &status
);
1614 ERR_MSG("cmd<13> resp<0x%x>", status
);
1615 } while (R1_CURRENT_STATE(status
) == 7);
1620 /* failed when msdc_do_request */
1621 static int msdc_tune_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1623 struct msdc_host
*host
= mmc_priv(mmc
);
1624 struct mmc_command
*cmd
;
1625 struct mmc_data
*data
;
1626 //u32 base = host->base;
1630 data
= mrq
->cmd
->data
;
1632 read
= data
->flags
& MMC_DATA_READ
? 1 : 0;
1635 if (data
->error
== -EIO
)
1636 ret
= msdc_tune_bread(mmc
, mrq
);
1638 ret
= msdc_check_busy(mmc
, host
);
1640 ERR_MSG("XXX cmd13 wait program done failed");
1644 /* Fix me: don't care card status? */
1645 ret
= msdc_tune_bwrite(mmc
, mrq
);
1652 static void msdc_ops_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1654 struct msdc_host
*host
= mmc_priv(mmc
);
1656 //=== for sdio profile ===
1657 #if 0 /* --- by chhung */
1658 u32 old_H32
, old_L32
, new_H32
, new_L32
;
1659 u32 ticks
= 0, opcode
= 0, sizes
= 0, bRx
= 0;
1660 #endif /* end of --- */
1664 /* start to process */
1665 spin_lock(&host
->lock
);
1666 #if 0 /* --- by chhung */
1667 if (sdio_pro_enable
) { //=== for sdio profile ===
1668 if (mrq
->cmd
->opcode
== 52 || mrq
->cmd
->opcode
== 53)
1669 GPT_GetCounter64(&old_L32
, &old_H32
);
1671 #endif /* end of --- */
1675 if (msdc_do_request(mmc
, mrq
)) {
1676 if (host
->hw
->flags
& MSDC_REMOVABLE
&& ralink_soc
== MT762X_SOC_MT7621AT
&& mrq
->data
&& mrq
->data
->error
)
1677 msdc_tune_request(mmc
, mrq
);
1680 /* ==== when request done, check if app_cmd ==== */
1681 if (mrq
->cmd
->opcode
== MMC_APP_CMD
) {
1683 host
->app_cmd_arg
= mrq
->cmd
->arg
; /* save the RCA */
1686 //host->app_cmd_arg = 0;
1691 #if 0 /* --- by chhung */
1692 //=== for sdio profile ===
1693 if (sdio_pro_enable
) {
1694 if (mrq
->cmd
->opcode
== 52 || mrq
->cmd
->opcode
== 53) {
1695 GPT_GetCounter64(&new_L32
, &new_H32
);
1696 ticks
= msdc_time_calc(old_L32
, old_H32
, new_L32
, new_H32
);
1698 opcode
= mrq
->cmd
->opcode
;
1699 if (mrq
->cmd
->data
) {
1700 sizes
= mrq
->cmd
->data
->blocks
* mrq
->cmd
->data
->blksz
;
1701 bRx
= mrq
->cmd
->data
->flags
& MMC_DATA_READ
? 1 : 0;
1703 bRx
= mrq
->cmd
->arg
& 0x80000000 ? 1 : 0;
1706 if (!mrq
->cmd
->error
)
1707 msdc_performance(opcode
, sizes
, bRx
, ticks
);
1710 #endif /* end of --- */
1711 spin_unlock(&host
->lock
);
1713 mmc_request_done(mmc
, mrq
);
1718 /* called by ops.set_ios */
1719 static void msdc_set_buswidth(struct msdc_host
*host
, u32 width
)
1721 void __iomem
*base
= host
->base
;
1722 u32 val
= sdr_read32(SDC_CFG
);
1724 val
&= ~SDC_CFG_BUSWIDTH
;
1728 case MMC_BUS_WIDTH_1
:
1730 val
|= (MSDC_BUS_1BITS
<< 16);
1732 case MMC_BUS_WIDTH_4
:
1733 val
|= (MSDC_BUS_4BITS
<< 16);
1735 case MMC_BUS_WIDTH_8
:
1736 val
|= (MSDC_BUS_8BITS
<< 16);
1740 sdr_write32(SDC_CFG
, val
);
1742 N_MSG(CFG
, "Bus Width = %d", width
);
1746 static void msdc_ops_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1748 struct msdc_host
*host
= mmc_priv(mmc
);
1749 void __iomem
*base
= host
->base
;
1752 #ifdef MT6575_SD_DEBUG
1753 static char *vdd
[] = {
1754 "1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
1755 "2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
1756 "2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
1757 "3.40v", "3.50v", "3.60v"
1759 static char *power_mode
[] = {
1762 static char *bus_mode
[] = {
1763 "UNKNOWN", "OPENDRAIN", "PUSHPULL"
1765 static char *timing
[] = {
1766 "LEGACY", "MMC_HS", "SD_HS"
1769 printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)",
1770 ios
->clock
/ 1000, bus_mode
[ios
->bus_mode
],
1771 (ios
->bus_width
== MMC_BUS_WIDTH_4
) ? 4 : 1,
1772 power_mode
[ios
->power_mode
], vdd
[ios
->vdd
], timing
[ios
->timing
]);
1775 msdc_set_buswidth(host
, ios
->bus_width
);
1777 /* Power control ??? */
1778 switch (ios
->power_mode
) {
1781 // msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
1784 host
->power_mode
= MMC_POWER_ON
;
1791 if (host
->mclk
!= ios
->clock
) {
1792 if (ios
->clock
> 25000000) {
1793 //if (!(host->hw->flags & MSDC_REMOVABLE)) {
1794 INIT_MSG("SD data latch edge<%d>", MSDC_SMPL_FALLING
);
1795 sdr_set_field(MSDC_IOCON
, MSDC_IOCON_RSPL
,
1797 sdr_set_field(MSDC_IOCON
, MSDC_IOCON_DSPL
,
1799 /* sdxc: set sample crc by clock falling edge. Added by zhangzf */
1800 if (ralink_soc
== MT762X_SOC_MT7628AN
)
1801 sdr_set_field(MSDC_IOCON
, MSDC_IOCON_WDSPL
, MSDC_SMPL_FALLING
);
1802 //} /* for tuning debug */
1803 } else { /* default value */
1804 sdr_write32(MSDC_IOCON
, 0x00000000);
1805 // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
1806 sdr_write32(MSDC_DAT_RDDLY0
, 0x10101010); // for MT7620 E2 and afterward
1807 sdr_write32(MSDC_DAT_RDDLY1
, 0x00000000);
1808 // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
1809 sdr_write32(MSDC_PAD_TUNE
, 0x84101010); // for MT7620 E2 and afterward
1811 msdc_set_mclk(host
, ddr
, ios
->clock
);
1816 static int msdc_ops_get_ro(struct mmc_host
*mmc
)
1818 struct msdc_host
*host
= mmc_priv(mmc
);
1819 void __iomem
*base
= host
->base
;
1820 unsigned long flags
;
1823 if (host
->hw
->flags
& MSDC_WP_PIN_EN
) { /* set for card */
1824 spin_lock_irqsave(&host
->lock
, flags
);
1825 ro
= (sdr_read32(MSDC_PS
) >> 31);
1826 spin_unlock_irqrestore(&host
->lock
, flags
);
1832 static int msdc_ops_get_cd(struct mmc_host
*mmc
)
1834 struct msdc_host
*host
= mmc_priv(mmc
);
1835 void __iomem
*base
= host
->base
;
1836 unsigned long flags
;
1839 /* for sdio, MSDC_REMOVABLE not set, always return 1 */
1840 if (!(host
->hw
->flags
& MSDC_REMOVABLE
)) {
1841 /* For sdio, read H/W always get<1>, but may timeout some times */
1843 host
->card_inserted
= 1;
1846 host
->card_inserted
= (host
->pm_state
.event
== PM_EVENT_USER_RESUME
) ? 1 : 0;
1847 INIT_MSG("sdio ops_get_cd<%d>", host
->card_inserted
);
1848 return host
->card_inserted
;
1852 /* MSDC_CD_PIN_EN set for card */
1853 if (host
->hw
->flags
& MSDC_CD_PIN_EN
) {
1854 spin_lock_irqsave(&host
->lock
, flags
);
1856 present
= host
->card_inserted
; /* why not read from H/W: Fix me*/
1860 present
= (sdr_read32(MSDC_PS
) & MSDC_PS_CDSTS
) ? 0 : 1;
1862 present
= (sdr_read32(MSDC_PS
) & MSDC_PS_CDSTS
) ? 1 : 0;
1863 host
->card_inserted
= present
;
1865 spin_unlock_irqrestore(&host
->lock
, flags
);
1867 present
= 0; /* TODO? Check DAT3 pins for card detection */
1870 INIT_MSG("ops_get_cd return<%d>", present
);
1874 static struct mmc_host_ops mt_msdc_ops
= {
1875 .request
= msdc_ops_request
,
1876 .set_ios
= msdc_ops_set_ios
,
1877 .get_ro
= msdc_ops_get_ro
,
1878 .get_cd
= msdc_ops_get_cd
,
1881 /*--------------------------------------------------------------------------*/
1882 /* interrupt handler */
1883 /*--------------------------------------------------------------------------*/
1884 static irqreturn_t
msdc_irq(int irq
, void *dev_id
)
1886 struct msdc_host
*host
= (struct msdc_host
*)dev_id
;
1887 struct mmc_data
*data
= host
->data
;
1888 struct mmc_command
*cmd
= host
->cmd
;
1889 void __iomem
*base
= host
->base
;
1891 u32 cmdsts
= MSDC_INT_RSPCRCERR
| MSDC_INT_CMDTMO
| MSDC_INT_CMDRDY
|
1892 MSDC_INT_ACMDCRCERR
| MSDC_INT_ACMDTMO
| MSDC_INT_ACMDRDY
|
1893 MSDC_INT_ACMD19_DONE
;
1894 u32 datsts
= MSDC_INT_DATCRCERR
| MSDC_INT_DATTMO
;
1896 u32 intsts
= sdr_read32(MSDC_INT
);
1897 u32 inten
= sdr_read32(MSDC_INTEN
); inten
&= intsts
;
1899 sdr_write32(MSDC_INT
, intsts
); /* clear interrupts */
1900 /* MSG will cause fatal error */
1902 /* card change interrupt */
1903 if (intsts
& MSDC_INT_CDSC
) {
1904 if (host
->mmc
->caps
& MMC_CAP_NEEDS_POLL
)
1906 IRQ_MSG("MSDC_INT_CDSC irq<0x%.8x>", intsts
);
1907 schedule_delayed_work(&host
->card_delaywork
, HZ
);
1908 /* tuning when plug card ? */
1911 /* sdio interrupt */
1912 if (intsts
& MSDC_INT_SDIOIRQ
) {
1913 IRQ_MSG("XXX MSDC_INT_SDIOIRQ"); /* seems not sdio irq */
1914 //mmc_signal_sdio_irq(host->mmc);
1917 /* transfer complete interrupt */
1919 if (inten
& MSDC_INT_XFER_COMPL
) {
1920 data
->bytes_xfered
= host
->xfer_size
;
1921 complete(&host
->xfer_done
);
1924 if (intsts
& datsts
) {
1925 /* do basic reset, or stop command will sdc_busy */
1926 msdc_reset_hw(host
);
1930 if (intsts
& MSDC_INT_DATTMO
) {
1931 IRQ_MSG("XXX CMD<%d> MSDC_INT_DATTMO", host
->mrq
->cmd
->opcode
);
1932 data
->error
= -ETIMEDOUT
;
1933 } else if (intsts
& MSDC_INT_DATCRCERR
) {
1934 IRQ_MSG("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>", host
->mrq
->cmd
->opcode
, sdr_read32(SDC_DCRC_STS
));
1938 //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {
1939 complete(&host
->xfer_done
); /* Read CRC come fast, XFER_COMPL not enabled */
1943 /* command interrupts */
1944 if ((cmd
!= NULL
) && (intsts
& cmdsts
)) {
1945 if ((intsts
& MSDC_INT_CMDRDY
) || (intsts
& MSDC_INT_ACMDRDY
) ||
1946 (intsts
& MSDC_INT_ACMD19_DONE
)) {
1947 u32
*rsp
= &cmd
->resp
[0];
1949 switch (host
->cmd_rsp
) {
1953 *rsp
++ = sdr_read32(SDC_RESP3
); *rsp
++ = sdr_read32(SDC_RESP2
);
1954 *rsp
++ = sdr_read32(SDC_RESP1
); *rsp
++ = sdr_read32(SDC_RESP0
);
1956 default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
1957 if ((intsts
& MSDC_INT_ACMDRDY
) || (intsts
& MSDC_INT_ACMD19_DONE
))
1958 *rsp
= sdr_read32(SDC_ACMD_RESP
);
1960 *rsp
= sdr_read32(SDC_RESP0
);
1963 } else if ((intsts
& MSDC_INT_RSPCRCERR
) || (intsts
& MSDC_INT_ACMDCRCERR
)) {
1964 if (intsts
& MSDC_INT_ACMDCRCERR
)
1965 IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDCRCERR", cmd
->opcode
);
1967 IRQ_MSG("XXX CMD<%d> MSDC_INT_RSPCRCERR", cmd
->opcode
);
1969 } else if ((intsts
& MSDC_INT_CMDTMO
) || (intsts
& MSDC_INT_ACMDTMO
)) {
1970 if (intsts
& MSDC_INT_ACMDTMO
)
1971 IRQ_MSG("XXX CMD<%d> MSDC_INT_ACMDTMO", cmd
->opcode
);
1973 IRQ_MSG("XXX CMD<%d> MSDC_INT_CMDTMO", cmd
->opcode
);
1974 cmd
->error
= -ETIMEDOUT
;
1975 msdc_reset_hw(host
);
1979 complete(&host
->cmd_done
);
1982 /* mmc irq interrupts */
1983 if (intsts
& MSDC_INT_MMCIRQ
)
1984 printk(KERN_INFO
"msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host
->id
, sdr_read32(SDC_CSTS
));
1986 #ifdef MT6575_SD_DEBUG
1988 /* msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;*/
1989 N_MSG(INT
, "IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)",
1996 int_reg
->atocmd19done
);
1997 N_MSG(INT
, "IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)",
2004 N_MSG(INT
, "IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)",
2010 int_reg
->dmaqempty
);
2017 /*--------------------------------------------------------------------------*/
2018 /* platform_driver members */
2019 /*--------------------------------------------------------------------------*/
2020 /* called by msdc_drv_probe/remove */
2021 static void msdc_enable_cd_irq(struct msdc_host
*host
, int enable
)
2023 struct msdc_hw
*hw
= host
->hw
;
2024 void __iomem
*base
= host
->base
;
2026 /* for sdio, not set */
2027 if ((hw
->flags
& MSDC_CD_PIN_EN
) == 0) {
2028 /* Pull down card detection pin since it is not avaiable */
2030 if (hw->config_gpio_pin)
2031 hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
2033 sdr_clr_bits(MSDC_PS
, MSDC_PS_CDEN
);
2034 sdr_clr_bits(MSDC_INTEN
, MSDC_INTEN_CDSC
);
2035 sdr_clr_bits(SDC_CFG
, SDC_CFG_INSWKUP
);
2039 N_MSG(CFG
, "CD IRQ Eanable(%d)", enable
);
2042 /* card detection circuit relies on the core power so that the core power
2043 * shouldn't be turned off. Here adds a reference count to keep
2044 * the core power alive.
2046 //msdc_vcore_on(host); //did in msdc_init_hw()
2048 if (hw
->config_gpio_pin
) /* NULL */
2049 hw
->config_gpio_pin(MSDC_CD_PIN
, GPIO_PULL_UP
);
2051 sdr_set_field(MSDC_PS
, MSDC_PS_CDDEBOUNCE
, DEFAULT_DEBOUNCE
);
2052 sdr_set_bits(MSDC_PS
, MSDC_PS_CDEN
);
2053 sdr_set_bits(MSDC_INTEN
, MSDC_INTEN_CDSC
);
2054 sdr_set_bits(SDC_CFG
, SDC_CFG_INSWKUP
); /* not in document! Fix me */
2056 if (hw
->config_gpio_pin
) /* NULL */
2057 hw
->config_gpio_pin(MSDC_CD_PIN
, GPIO_PULL_DOWN
);
2059 sdr_clr_bits(SDC_CFG
, SDC_CFG_INSWKUP
);
2060 sdr_clr_bits(MSDC_PS
, MSDC_PS_CDEN
);
2061 sdr_clr_bits(MSDC_INTEN
, MSDC_INTEN_CDSC
);
2063 /* Here decreases a reference count to core power since card
2064 * detection circuit is shutdown.
2066 //msdc_vcore_off(host);
2070 /* called by msdc_drv_probe */
2071 static void msdc_init_hw(struct msdc_host
*host
)
2073 void __iomem
*base
= host
->base
;
2076 #if 0 /* --- by chhung */
2077 msdc_vcore_on(host
);
2078 msdc_pin_reset(host
, MSDC_PIN_PULL_UP
);
2079 msdc_select_clksrc(host
, hw
->clk_src
);
2080 enable_clock(PERI_MSDC0_PDN
+ host
->id
, "SD");
2082 #endif /* end of --- */
2083 /* Configure to MMC/SD mode */
2084 sdr_set_field(MSDC_CFG
, MSDC_CFG_MODE
, MSDC_SDMMC
);
2087 msdc_reset_hw(host
);
2090 /* Disable card detection */
2091 sdr_clr_bits(MSDC_PS
, MSDC_PS_CDEN
);
2093 /* Disable and clear all interrupts */
2094 sdr_clr_bits(MSDC_INTEN
, sdr_read32(MSDC_INTEN
));
2095 sdr_write32(MSDC_INT
, sdr_read32(MSDC_INT
));
2098 /* reset tuning parameter */
2099 sdr_write32(MSDC_PAD_CTL0
, 0x00090000);
2100 sdr_write32(MSDC_PAD_CTL1
, 0x000A0000);
2101 sdr_write32(MSDC_PAD_CTL2
, 0x000A0000);
2102 // sdr_write32(MSDC_PAD_TUNE, 0x00000000);
2103 sdr_write32(MSDC_PAD_TUNE
, 0x84101010); // for MT7620 E2 and afterward
2104 // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
2105 sdr_write32(MSDC_DAT_RDDLY0
, 0x10101010); // for MT7620 E2 and afterward
2106 sdr_write32(MSDC_DAT_RDDLY1
, 0x00000000);
2107 sdr_write32(MSDC_IOCON
, 0x00000000);
2108 #if 0 // use MT7620 default value: 0x403c004f
2109 sdr_write32(MSDC_PATCH_BIT0
, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
2112 if (sdr_read32(MSDC_ECO_VER
) >= 4) {
2113 if (host
->id
== 1) {
2114 sdr_set_field(MSDC_PATCH_BIT1
, MSDC_PATCH_BIT1_WRDAT_CRCS
, 1);
2115 sdr_set_field(MSDC_PATCH_BIT1
, MSDC_PATCH_BIT1_CMD_RSP
, 1);
2117 /* internal clock: latch read data */
2118 sdr_set_bits(MSDC_PATCH_BIT0
, MSDC_PATCH_BIT_CKGEN_CK
);
2123 /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in
2124 pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
2125 set when kernel driver wants to use SDIO bus interrupt */
2126 /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
2127 sdr_set_bits(SDC_CFG
, SDC_CFG_SDIO
);
2129 /* disable detect SDIO device interupt function */
2130 sdr_clr_bits(SDC_CFG
, SDC_CFG_SDIOIDE
);
2132 /* eneable SMT for glitch filter */
2133 sdr_set_bits(MSDC_PAD_CTL0
, MSDC_PAD_CTL0_CLKSMT
);
2134 sdr_set_bits(MSDC_PAD_CTL1
, MSDC_PAD_CTL1_CMDSMT
);
2135 sdr_set_bits(MSDC_PAD_CTL2
, MSDC_PAD_CTL2_DATSMT
);
2138 /* set clk, cmd, dat pad driving */
2139 sdr_set_field(MSDC_PAD_CTL0
, MSDC_PAD_CTL0_CLKDRVN
, 4);
2140 sdr_set_field(MSDC_PAD_CTL0
, MSDC_PAD_CTL0_CLKDRVP
, 4);
2141 sdr_set_field(MSDC_PAD_CTL1
, MSDC_PAD_CTL1_CMDDRVN
, 4);
2142 sdr_set_field(MSDC_PAD_CTL1
, MSDC_PAD_CTL1_CMDDRVP
, 4);
2143 sdr_set_field(MSDC_PAD_CTL2
, MSDC_PAD_CTL2_DATDRVN
, 4);
2144 sdr_set_field(MSDC_PAD_CTL2
, MSDC_PAD_CTL2_DATDRVP
, 4);
2146 sdr_set_field(MSDC_PAD_CTL0
, MSDC_PAD_CTL0_CLKDRVN
, 0);
2147 sdr_set_field(MSDC_PAD_CTL0
, MSDC_PAD_CTL0_CLKDRVP
, 0);
2148 sdr_set_field(MSDC_PAD_CTL1
, MSDC_PAD_CTL1_CMDDRVN
, 0);
2149 sdr_set_field(MSDC_PAD_CTL1
, MSDC_PAD_CTL1_CMDDRVP
, 0);
2150 sdr_set_field(MSDC_PAD_CTL2
, MSDC_PAD_CTL2_DATDRVN
, 0);
2151 sdr_set_field(MSDC_PAD_CTL2
, MSDC_PAD_CTL2_DATDRVP
, 0);
2154 /* set sampling edge */
2156 /* write crc timeout detection */
2157 sdr_set_field(MSDC_PATCH_BIT0
, 1 << 30, 1);
2159 /* Configure to default data timeout */
2160 sdr_set_field(SDC_CFG
, SDC_CFG_DTOC
, DEFAULT_DTOC
);
2162 msdc_set_buswidth(host
, MMC_BUS_WIDTH_1
);
2164 N_MSG(FUC
, "init hardware done!");
2167 /* called by msdc_drv_remove */
2168 static void msdc_deinit_hw(struct msdc_host
*host
)
2170 void __iomem
*base
= host
->base
;
2172 /* Disable and clear all interrupts */
2173 sdr_clr_bits(MSDC_INTEN
, sdr_read32(MSDC_INTEN
));
2174 sdr_write32(MSDC_INT
, sdr_read32(MSDC_INT
));
2176 /* Disable card detection */
2177 msdc_enable_cd_irq(host
, 0);
2178 // msdc_set_power_mode(host, MMC_POWER_OFF); /* make sure power down */ /* --- by chhung */
2181 /* init gpd and bd list in msdc_drv_probe */
2182 static void msdc_init_gpd_bd(struct msdc_host
*host
, struct msdc_dma
*dma
)
2184 struct gpd
*gpd
= dma
->gpd
;
2185 struct bd
*bd
= dma
->bd
;
2188 /* we just support one gpd, but gpd->next must be set for desc
2189 * DMA. That's why we alloc 2 gpd structurs.
2192 memset(gpd
, 0, sizeof(struct gpd
) * 2);
2194 gpd
->bdp
= 1; /* hwo, cs, bd pointer */
2195 gpd
->ptr
= (void *)dma
->bd_addr
; /* physical address */
2196 gpd
->next
= (void *)((u32
)dma
->gpd_addr
+ sizeof(struct gpd
));
2198 memset(bd
, 0, sizeof(struct bd
) * MAX_BD_NUM
);
2199 for (i
= 0; i
< (MAX_BD_NUM
- 1); i
++)
2200 bd
[i
].next
= (void *)(dma
->bd_addr
+ sizeof(*bd
) * (i
+ 1));
2203 static int msdc_drv_probe(struct platform_device
*pdev
)
2205 struct resource
*res
;
2207 struct mmc_host
*mmc
;
2208 struct msdc_host
*host
;
2213 // Set the pins for sdxc to sdxc mode
2214 //FIXME: this should be done by pinctl and not by the sd driver
2215 if (ralink_soc
== MT762X_SOC_MT7620A
||
2216 ralink_soc
== MT762X_SOC_MT7621AT
) {
2217 reg
= sdr_read32((void __iomem
*)(RALINK_SYSCTL_BASE
+
2218 0x60)) & ~(0x3 << 18);
2219 if (ralink_soc
== MT762X_SOC_MT7620A
)
2222 else if (ralink_soc
== MT762X_SOC_MT7628AN
) {
2223 /* Fixed MT7628 SDXC init by zhangzf */
2224 reg
&= ~((0x3 << 0)|(0x3 << 6)|(0x3 << 10)|(0x1 << 15)|(0x3 << 20)|(0x3 << 24));
2225 reg
|= ((0x1 << 0)|(0x1 << 6)|(0x1 << 10)|(0x1 << 15)|(0x1 << 20)|(0x1 << 24));
2226 #if defined (CONFIG_MTK_MMC_EMMC_8BIT)
2227 reg
|= 0x3 << 26 | 0x3 << 28 | 0x3 << 30;
2229 reg1
= sdr_read32((void __iomem
*)(RALINK_SYSCTL_BASE
+ 0x1340));
2230 reg1
|= (0x1 << 11); //Normal mode(AP mode), SDXC CLK=PAD_GPIO0=GPIO11, driving = 8mA
2231 sdr_write32((void __iomem
*)(RALINK_SYSCTL_BASE
+ 0x1340), reg1
);
2233 reg
= sdr_read32((void __iomem
*)(RALINK_SYSCTL_BASE
+ 0x3c));
2235 sdr_write32((void __iomem
*)(RALINK_SYSCTL_BASE
+ 0x3c), reg
);
2236 reg
= sdr_read32((void __iomem
*)(RALINK_SYSCTL_BASE
+
2237 0x60)) & ~(0x3 << 10);
2238 #if defined(CONFIG_MTK_MMC_EMMC_8BIT)
2239 reg
|= 0x3 << 26 | 0x3 << 28 | 0x3 << 30;
2243 sdr_write32((void __iomem
*)(RALINK_SYSCTL_BASE
+ 0x60), reg
);
2247 if (of_property_read_bool(pdev
->dev
.of_node
, "mtk,wp-en"))
2248 msdc0_hw
.flags
|= MSDC_WP_PIN_EN
;
2250 /* Allocate MMC host for this device */
2251 mmc
= mmc_alloc_host(sizeof(struct msdc_host
), &pdev
->dev
);
2255 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2256 base
= devm_ioremap_resource(&pdev
->dev
, res
);
2258 ret
= PTR_ERR(base
);
2262 /* Set host parameters to mmc */
2263 mmc
->ops
= &mt_msdc_ops
;
2264 mmc
->f_min
= HOST_MIN_MCLK
;
2265 mmc
->f_max
= HOST_MAX_MCLK
;
2266 mmc
->ocr_avail
= MSDC_OCR_AVAIL
;
2268 mmc
->caps
= MMC_CAP_MMC_HIGHSPEED
| MMC_CAP_SD_HIGHSPEED
;
2270 //TODO: read this as bus-width from dt (via mmc_of_parse)
2271 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
2273 cd_active_low
= !of_property_read_bool(pdev
->dev
.of_node
, "mediatek,cd-high");
2275 if (of_property_read_bool(pdev
->dev
.of_node
, "mediatek,cd-poll"))
2276 mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
2278 /* MMC core transfer sizes tunable parameters */
2279 mmc
->max_segs
= MAX_HW_SGMTS
;
2281 mmc
->max_seg_size
= MAX_SGMT_SZ
;
2282 mmc
->max_blk_size
= HOST_MAX_BLKSZ
;
2283 mmc
->max_req_size
= MAX_REQ_SZ
;
2284 mmc
->max_blk_count
= mmc
->max_req_size
;
2286 host
= mmc_priv(mmc
);
2289 host
->id
= pdev
->id
;
2290 if (host
->id
< 0 || host
->id
>= 4)
2294 host
->irq
= platform_get_irq(pdev
, 0);
2295 if (host
->irq
< 0) {
2301 host
->mclk
= 0; /* mclk: the request clock of mmc sub-system */
2302 host
->hclk
= hclks
[hw
->clk_src
]; /* hclk: clock of clock source to msdc controller */
2303 host
->sclk
= 0; /* sclk: the really clock after divition */
2304 host
->pm_state
= PMSG_RESUME
;
2306 host
->core_clkon
= 0;
2307 host
->card_clkon
= 0;
2308 host
->core_power
= 0;
2309 host
->power_mode
= MMC_POWER_OFF
;
2310 // host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
2311 host
->timeout_ns
= 0;
2312 host
->timeout_clks
= DEFAULT_DTOC
* 65536;
2315 //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
2317 mmc_dev(mmc
)->dma_mask
= NULL
;
2319 /* using dma_alloc_coherent*/ /* todo: using 1, for all 4 slots */
2320 host
->dma
.gpd
= dma_alloc_coherent(&pdev
->dev
,
2321 MAX_GPD_NUM
* sizeof(struct gpd
),
2322 &host
->dma
.gpd_addr
, GFP_KERNEL
);
2323 host
->dma
.bd
= dma_alloc_coherent(&pdev
->dev
,
2324 MAX_BD_NUM
* sizeof(struct bd
),
2325 &host
->dma
.bd_addr
, GFP_KERNEL
);
2326 if (!host
->dma
.gpd
|| !host
->dma
.bd
) {
2330 msdc_init_gpd_bd(host
, &host
->dma
);
2332 INIT_DELAYED_WORK(&host
->card_delaywork
, msdc_tasklet_card
);
2333 spin_lock_init(&host
->lock
);
2336 /* TODO check weather flags 0 is correct, the mtk-sd driver uses
2337 * IRQF_TRIGGER_LOW | IRQF_ONESHOT for flags
2339 * for flags 0 the trigger polarity is determined by the
2340 * device tree, but not the oneshot flag, but maybe it is also
2341 * not needed because the soc could be oneshot safe.
2343 ret
= devm_request_irq(&pdev
->dev
, host
->irq
, msdc_irq
, 0, pdev
->name
,
2348 platform_set_drvdata(pdev
, mmc
);
2350 ret
= mmc_add_host(mmc
);
2354 /* Config card detection pin and enable interrupts */
2355 if (hw
->flags
& MSDC_CD_PIN_EN
) { /* set for card */
2356 msdc_enable_cd_irq(host
, 1);
2358 msdc_enable_cd_irq(host
, 0);
2364 platform_set_drvdata(pdev
, NULL
);
2365 msdc_deinit_hw(host
);
2366 cancel_delayed_work_sync(&host
->card_delaywork
);
2370 dma_free_coherent(&pdev
->dev
, MAX_GPD_NUM
* sizeof(struct gpd
),
2371 host
->dma
.gpd
, host
->dma
.gpd_addr
);
2373 dma_free_coherent(&pdev
->dev
, MAX_BD_NUM
* sizeof(struct bd
),
2374 host
->dma
.bd
, host
->dma
.bd_addr
);
2381 /* 4 device share one driver, using "drvdata" to show difference */
2382 static int msdc_drv_remove(struct platform_device
*pdev
)
2384 struct mmc_host
*mmc
;
2385 struct msdc_host
*host
;
2387 mmc
= platform_get_drvdata(pdev
);
2390 host
= mmc_priv(mmc
);
2393 ERR_MSG("removed !!!");
2395 platform_set_drvdata(pdev
, NULL
);
2396 mmc_remove_host(host
->mmc
);
2397 msdc_deinit_hw(host
);
2399 cancel_delayed_work_sync(&host
->card_delaywork
);
2401 dma_free_coherent(&pdev
->dev
, MAX_GPD_NUM
* sizeof(struct gpd
),
2402 host
->dma
.gpd
, host
->dma
.gpd_addr
);
2403 dma_free_coherent(&pdev
->dev
, MAX_BD_NUM
* sizeof(struct bd
),
2404 host
->dma
.bd
, host
->dma
.bd_addr
);
2406 mmc_free_host(host
->mmc
);
2411 /* Fix me: Power Flow */
2414 static void msdc_drv_pm(struct platform_device
*pdev
, pm_message_t state
)
2416 struct mmc_host
*mmc
= platform_get_drvdata(pdev
);
2418 struct msdc_host
*host
= mmc_priv(mmc
);
2419 msdc_pm(state
, (void *)host
);
2423 static int msdc_drv_suspend(struct platform_device
*pdev
, pm_message_t state
)
2425 if (state
.event
== PM_EVENT_SUSPEND
)
2426 msdc_drv_pm(pdev
, state
);
2430 static int msdc_drv_resume(struct platform_device
*pdev
)
2432 struct pm_message state
;
2434 state
.event
= PM_EVENT_RESUME
;
2435 msdc_drv_pm(pdev
, state
);
2440 static const struct of_device_id mt7620_sdhci_match
[] = {
2441 { .compatible
= "ralink,mt7620-sdhci" },
2444 MODULE_DEVICE_TABLE(of
, mt7620_sdhci_match
);
2446 static struct platform_driver mt_msdc_driver
= {
2447 .probe
= msdc_drv_probe
,
2448 .remove
= msdc_drv_remove
,
2450 .suspend
= msdc_drv_suspend
,
2451 .resume
= msdc_drv_resume
,
2455 .of_match_table
= mt7620_sdhci_match
,
2459 /*--------------------------------------------------------------------------*/
2460 /* module init/exit */
2461 /*--------------------------------------------------------------------------*/
2462 static int __init
mt_msdc_init(void)
2466 ret
= platform_driver_register(&mt_msdc_driver
);
2468 printk(KERN_ERR DRV_NAME
": Can't register driver");
2472 #if defined(MT6575_SD_DEBUG)
2473 msdc_debug_proc_init();
2478 static void __exit
mt_msdc_exit(void)
2480 platform_driver_unregister(&mt_msdc_driver
);
2483 module_init(mt_msdc_init
);
2484 module_exit(mt_msdc_exit
);
2485 MODULE_LICENSE("GPL");
2486 MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
2487 MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");