1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_device.h>
20 #include <linux/of_irq.h>
22 #include <ralink_regs.h>
24 #include "mtk_eth_soc.h"
25 #include "gsw_mt7620.h"
27 void mtk_switch_w32(struct mt7620_gsw
*gsw
, u32 val
, unsigned reg
)
29 iowrite32(val
, gsw
->base
+ reg
);
32 u32
mtk_switch_r32(struct mt7620_gsw
*gsw
, unsigned reg
)
34 return ioread32(gsw
->base
+ reg
);
37 static irqreturn_t
gsw_interrupt_mt7620(int irq
, void *_priv
)
39 struct fe_priv
*priv
= (struct fe_priv
*)_priv
;
40 struct mt7620_gsw
*gsw
= (struct mt7620_gsw
*)priv
->soc
->swpriv
;
42 int i
, max
= (gsw
->port4
== PORT4_EPHY
) ? (4) : (3);
44 status
= mtk_switch_r32(gsw
, GSW_REG_ISR
);
45 if (status
& PORT_IRQ_ST_CHG
)
46 for (i
= 0; i
<= max
; i
++) {
47 u32 status
= mtk_switch_r32(gsw
, GSW_REG_PORT_STATUS(i
));
48 int link
= status
& 0x1;
50 if (link
!= priv
->link
[i
])
51 mt7620_print_link_state(priv
, i
, link
,
57 mt7620_handle_carrier(priv
);
58 mtk_switch_w32(gsw
, status
, GSW_REG_ISR
);
63 static int mt7620_mdio_mode(struct device_node
*eth_node
)
65 struct device_node
*phy_node
, *mdiobus_node
;
69 mdiobus_node
= of_get_child_by_name(eth_node
, "mdio-bus");
72 for_each_child_of_node(mdiobus_node
, phy_node
) {
73 id
= of_get_property(phy_node
, "reg", NULL
);
74 if (id
&& (be32_to_cpu(*id
) == 0x1f))
78 of_node_put(mdiobus_node
);
84 static void mt7620_hw_init(struct mt7620_gsw
*gsw
, int mdio_mode
)
86 u32 is_BGA
= (rt_sysc_r32(0x0c) >> 16) & 1;
88 rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1
) | BIT(8), SYSC_REG_CFG1
);
89 mtk_switch_w32(gsw
, mtk_switch_r32(gsw
, GSW_REG_CKGCR
) & ~(0x3 << 4), GSW_REG_CKGCR
);
91 /* Enable MIB stats */
92 mtk_switch_w32(gsw
, mtk_switch_r32(gsw
, GSW_REG_MIB_CNT_EN
) | (1 << 1), GSW_REG_MIB_CNT_EN
);
97 /* turn off ephy and set phy base addr to 12 */
98 mtk_switch_w32(gsw
, mtk_switch_r32(gsw
, GSW_REG_GPC1
) |
99 (0x1f << 24) | (0xc << 16),
102 /* set MT7530 central align */
103 val
= mt7530_mdio_r32(gsw
, 0x7830);
106 mt7530_mdio_w32(gsw
, 0x7830, val
);
108 val
= mt7530_mdio_r32(gsw
, 0x7a40);
110 mt7530_mdio_w32(gsw
, 0x7a40, val
);
112 mt7530_mdio_w32(gsw
, 0x7a78, 0x855);
115 _mt7620_mii_write(gsw
, 1, 31, 0x4000);
117 _mt7620_mii_write(gsw
, 1, 17, 0x7444);
119 _mt7620_mii_write(gsw
, 1, 19, 0x0114);
121 _mt7620_mii_write(gsw
, 1, 19, 0x0117);
123 _mt7620_mii_write(gsw
, 1, 22, 0x10cf);
124 _mt7620_mii_write(gsw
, 1, 25, 0x6212);
125 _mt7620_mii_write(gsw
, 1, 26, 0x0777);
126 _mt7620_mii_write(gsw
, 1, 29, 0x4000);
127 _mt7620_mii_write(gsw
, 1, 28, 0xc077);
128 _mt7620_mii_write(gsw
, 1, 24, 0x0000);
131 _mt7620_mii_write(gsw
, 1, 31, 0x3000);
132 _mt7620_mii_write(gsw
, 1, 17, 0x4838);
135 _mt7620_mii_write(gsw
, 1, 31, 0x2000);
137 _mt7620_mii_write(gsw
, 1, 21, 0x0515);
138 _mt7620_mii_write(gsw
, 1, 22, 0x0053);
139 _mt7620_mii_write(gsw
, 1, 23, 0x00bf);
140 _mt7620_mii_write(gsw
, 1, 24, 0x0aaf);
141 _mt7620_mii_write(gsw
, 1, 25, 0x0fad);
142 _mt7620_mii_write(gsw
, 1, 26, 0x0fc1);
144 _mt7620_mii_write(gsw
, 1, 21, 0x0517);
145 _mt7620_mii_write(gsw
, 1, 22, 0x0fd2);
146 _mt7620_mii_write(gsw
, 1, 23, 0x00bf);
147 _mt7620_mii_write(gsw
, 1, 24, 0x0aab);
148 _mt7620_mii_write(gsw
, 1, 25, 0x00ae);
149 _mt7620_mii_write(gsw
, 1, 26, 0x0fff);
152 _mt7620_mii_write(gsw
, 1, 31, 0x1000);
153 _mt7620_mii_write(gsw
, 1, 17, 0xe7f8);
157 _mt7620_mii_write(gsw
, 1, 31, 0x8000);
158 _mt7620_mii_write(gsw
, 0, 30, 0xa000);
159 _mt7620_mii_write(gsw
, 1, 30, 0xa000);
160 _mt7620_mii_write(gsw
, 2, 30, 0xa000);
161 _mt7620_mii_write(gsw
, 3, 30, 0xa000);
163 _mt7620_mii_write(gsw
, 0, 4, 0x05e1);
164 _mt7620_mii_write(gsw
, 1, 4, 0x05e1);
165 _mt7620_mii_write(gsw
, 2, 4, 0x05e1);
166 _mt7620_mii_write(gsw
, 3, 4, 0x05e1);
169 _mt7620_mii_write(gsw
, 1, 31, 0xa000);
170 _mt7620_mii_write(gsw
, 0, 16, 0x1111);
171 _mt7620_mii_write(gsw
, 1, 16, 0x1010);
172 _mt7620_mii_write(gsw
, 2, 16, 0x1515);
173 _mt7620_mii_write(gsw
, 3, 16, 0x0f0f);
175 /* CPU Port6 Force Link 1G, FC ON */
176 mtk_switch_w32(gsw
, 0x5e33b, GSW_REG_PORT_PMCR(6));
178 /* Set Port 6 as CPU Port */
179 mtk_switch_w32(gsw
, 0x7f7f7fe0, 0x0010);
182 if (gsw
->port4
== PORT4_EPHY
) {
183 u32 val
= rt_sysc_r32(SYSC_REG_CFG1
);
186 rt_sysc_w32(val
, SYSC_REG_CFG1
);
187 _mt7620_mii_write(gsw
, 4, 30, 0xa000);
188 _mt7620_mii_write(gsw
, 4, 4, 0x05e1);
189 _mt7620_mii_write(gsw
, 4, 16, 0x1313);
190 _mt7620_mii_write(gsw
, 4, 0, 0x3100);
191 pr_info("gsw: setting port4 to ephy mode\n");
192 } else if (!mdio_mode
) {
193 u32 val
= rt_sysc_r32(SYSC_REG_CFG1
);
196 rt_sysc_w32(val
, SYSC_REG_CFG1
);
197 pr_info("gsw: setting port4 to gmac mode\n");
201 static const struct of_device_id mediatek_gsw_match
[] = {
202 { .compatible
= "mediatek,mt7620-gsw" },
205 MODULE_DEVICE_TABLE(of
, mediatek_gsw_match
);
207 int mtk_gsw_init(struct fe_priv
*priv
)
209 struct device_node
*np
= priv
->switch_np
;
210 struct platform_device
*pdev
= of_find_device_by_node(np
);
211 struct mt7620_gsw
*gsw
;
216 if (!of_device_is_compatible(np
, mediatek_gsw_match
->compatible
))
219 gsw
= platform_get_drvdata(pdev
);
220 priv
->soc
->swpriv
= gsw
;
222 mt7620_hw_init(gsw
, mt7620_mdio_mode(priv
->dev
->of_node
));
225 request_irq(gsw
->irq
, gsw_interrupt_mt7620
, 0,
227 mtk_switch_w32(gsw
, ~PORT_IRQ_ST_CHG
, GSW_REG_IMR
);
233 static int mt7620_gsw_probe(struct platform_device
*pdev
)
235 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
236 const char *port4
= NULL
;
237 struct mt7620_gsw
*gsw
;
238 struct device_node
*np
= pdev
->dev
.of_node
;
240 gsw
= devm_kzalloc(&pdev
->dev
, sizeof(struct mt7620_gsw
), GFP_KERNEL
);
244 gsw
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
245 if (IS_ERR(gsw
->base
))
246 return PTR_ERR(gsw
->base
);
248 gsw
->dev
= &pdev
->dev
;
250 of_property_read_string(np
, "mediatek,port4", &port4
);
251 if (port4
&& !strcmp(port4
, "ephy"))
252 gsw
->port4
= PORT4_EPHY
;
253 else if (port4
&& !strcmp(port4
, "gmac"))
254 gsw
->port4
= PORT4_EXT
;
256 gsw
->port4
= PORT4_EPHY
;
258 gsw
->irq
= platform_get_irq(pdev
, 0);
260 platform_set_drvdata(pdev
, gsw
);
265 static int mt7620_gsw_remove(struct platform_device
*pdev
)
267 platform_set_drvdata(pdev
, NULL
);
272 static struct platform_driver gsw_driver
= {
273 .probe
= mt7620_gsw_probe
,
274 .remove
= mt7620_gsw_remove
,
276 .name
= "mt7620-gsw",
277 .owner
= THIS_MODULE
,
278 .of_match_table
= mediatek_gsw_match
,
282 module_platform_driver(gsw_driver
);
284 MODULE_LICENSE("GPL");
285 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
286 MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC");
287 MODULE_VERSION(MTK_FE_DRV_VERSION
);