1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
32 #include <linux/bug.h>
33 #include <linux/netfilter.h>
34 #include <net/netfilter/nf_flow_table.h>
35 #include <linux/of_gpio.h>
36 #include <linux/gpio.h>
37 #include <linux/gpio/consumer.h>
39 #include <asm/mach-ralink/ralink_regs.h>
41 #include "mtk_eth_soc.h"
45 #define MAX_RX_LENGTH 1536
46 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
47 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
48 #define DMA_DUMMY_DESC 0xffffffff
49 #define FE_DEFAULT_MSG_ENABLE \
59 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
60 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
61 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
62 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
64 #define SYSC_REG_RSTCTRL 0x34
66 static int fe_msg_level
= -1;
67 module_param_named(msg_level
, fe_msg_level
, int, 0);
68 MODULE_PARM_DESC(msg_level
, "Message level (-1=defaults,0=none,...,16=all)");
70 static const u16 fe_reg_table_default
[FE_REG_COUNT
] = {
71 [FE_REG_PDMA_GLO_CFG
] = FE_PDMA_GLO_CFG
,
72 [FE_REG_PDMA_RST_CFG
] = FE_PDMA_RST_CFG
,
73 [FE_REG_DLY_INT_CFG
] = FE_DLY_INT_CFG
,
74 [FE_REG_TX_BASE_PTR0
] = FE_TX_BASE_PTR0
,
75 [FE_REG_TX_MAX_CNT0
] = FE_TX_MAX_CNT0
,
76 [FE_REG_TX_CTX_IDX0
] = FE_TX_CTX_IDX0
,
77 [FE_REG_TX_DTX_IDX0
] = FE_TX_DTX_IDX0
,
78 [FE_REG_RX_BASE_PTR0
] = FE_RX_BASE_PTR0
,
79 [FE_REG_RX_MAX_CNT0
] = FE_RX_MAX_CNT0
,
80 [FE_REG_RX_CALC_IDX0
] = FE_RX_CALC_IDX0
,
81 [FE_REG_RX_DRX_IDX0
] = FE_RX_DRX_IDX0
,
82 [FE_REG_FE_INT_ENABLE
] = FE_FE_INT_ENABLE
,
83 [FE_REG_FE_INT_STATUS
] = FE_FE_INT_STATUS
,
84 [FE_REG_FE_DMA_VID_BASE
] = FE_DMA_VID0
,
85 [FE_REG_FE_COUNTER_BASE
] = FE_GDMA1_TX_GBCNT
,
86 [FE_REG_FE_RST_GL
] = FE_FE_RST_GL
,
89 static const u16
*fe_reg_table
= fe_reg_table_default
;
93 void (*action
)(struct fe_priv
*);
96 static void __iomem
*fe_base
;
98 void fe_w32(u32 val
, unsigned reg
)
100 __raw_writel(val
, fe_base
+ reg
);
103 u32
fe_r32(unsigned reg
)
105 return __raw_readl(fe_base
+ reg
);
108 void fe_reg_w32(u32 val
, enum fe_reg reg
)
110 fe_w32(val
, fe_reg_table
[reg
]);
113 u32
fe_reg_r32(enum fe_reg reg
)
115 return fe_r32(fe_reg_table
[reg
]);
118 void fe_m32(struct fe_priv
*eth
, u32 clear
, u32 set
, unsigned reg
)
122 spin_lock(ð
->page_lock
);
123 val
= __raw_readl(fe_base
+ reg
);
126 __raw_writel(val
, fe_base
+ reg
);
127 spin_unlock(ð
->page_lock
);
130 void fe_reset(u32 reset_bits
)
134 t
= rt_sysc_r32(SYSC_REG_RSTCTRL
);
136 rt_sysc_w32(t
, SYSC_REG_RSTCTRL
);
137 usleep_range(10, 20);
140 rt_sysc_w32(t
, SYSC_REG_RSTCTRL
);
141 usleep_range(10, 20);
144 static inline void fe_int_disable(u32 mask
)
146 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE
) & ~mask
,
147 FE_REG_FE_INT_ENABLE
);
149 fe_reg_r32(FE_REG_FE_INT_ENABLE
);
152 static inline void fe_int_enable(u32 mask
)
154 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE
) | mask
,
155 FE_REG_FE_INT_ENABLE
);
157 fe_reg_r32(FE_REG_FE_INT_ENABLE
);
160 static inline void fe_hw_set_macaddr(struct fe_priv
*priv
, unsigned char *mac
)
164 spin_lock_irqsave(&priv
->page_lock
, flags
);
165 fe_w32((mac
[0] << 8) | mac
[1], FE_GDMA1_MAC_ADRH
);
166 fe_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
168 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
171 static int fe_set_mac_address(struct net_device
*dev
, void *p
)
173 int ret
= eth_mac_addr(dev
, p
);
176 struct fe_priv
*priv
= netdev_priv(dev
);
178 if (priv
->soc
->set_mac
)
179 priv
->soc
->set_mac(priv
, dev
->dev_addr
);
181 fe_hw_set_macaddr(priv
, p
);
187 static inline int fe_max_frag_size(int mtu
)
189 /* make sure buf_size will be at least MAX_RX_LENGTH */
190 if (mtu
+ FE_RX_ETH_HLEN
< MAX_RX_LENGTH
)
191 mtu
= MAX_RX_LENGTH
- FE_RX_ETH_HLEN
;
193 return SKB_DATA_ALIGN(FE_RX_HLEN
+ mtu
) +
194 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
197 static inline int fe_max_buf_size(int frag_size
)
199 int buf_size
= frag_size
- NET_SKB_PAD
- NET_IP_ALIGN
-
200 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
202 BUG_ON(buf_size
< MAX_RX_LENGTH
);
206 static inline void fe_get_rxd(struct fe_rx_dma
*rxd
, struct fe_rx_dma
*dma_rxd
)
208 rxd
->rxd1
= dma_rxd
->rxd1
;
209 rxd
->rxd2
= dma_rxd
->rxd2
;
210 rxd
->rxd3
= dma_rxd
->rxd3
;
211 rxd
->rxd4
= dma_rxd
->rxd4
;
214 static inline void fe_set_txd(struct fe_tx_dma
*txd
, struct fe_tx_dma
*dma_txd
)
216 dma_txd
->txd1
= txd
->txd1
;
217 dma_txd
->txd3
= txd
->txd3
;
218 dma_txd
->txd4
= txd
->txd4
;
219 /* clean dma done flag last */
220 dma_txd
->txd2
= txd
->txd2
;
223 static void fe_clean_rx(struct fe_priv
*priv
)
225 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
230 for (i
= 0; i
< ring
->rx_ring_size
; i
++)
231 if (ring
->rx_data
[i
]) {
232 if (ring
->rx_dma
&& ring
->rx_dma
[i
].rxd1
)
233 dma_unmap_single(&priv
->netdev
->dev
,
234 ring
->rx_dma
[i
].rxd1
,
237 skb_free_frag(ring
->rx_data
[i
]);
240 kfree(ring
->rx_data
);
241 ring
->rx_data
= NULL
;
245 dma_free_coherent(&priv
->netdev
->dev
,
246 ring
->rx_ring_size
* sizeof(*ring
->rx_dma
),
252 if (!ring
->frag_cache
.va
)
255 page
= virt_to_page(ring
->frag_cache
.va
);
256 __page_frag_cache_drain(page
, ring
->frag_cache
.pagecnt_bias
);
257 memset(&ring
->frag_cache
, 0, sizeof(ring
->frag_cache
));
260 static int fe_alloc_rx(struct fe_priv
*priv
)
262 struct net_device
*netdev
= priv
->netdev
;
263 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
266 ring
->rx_data
= kcalloc(ring
->rx_ring_size
, sizeof(*ring
->rx_data
),
271 for (i
= 0; i
< ring
->rx_ring_size
; i
++) {
272 ring
->rx_data
[i
] = page_frag_alloc(&ring
->frag_cache
,
275 if (!ring
->rx_data
[i
])
279 ring
->rx_dma
= dma_alloc_coherent(&netdev
->dev
,
280 ring
->rx_ring_size
* sizeof(*ring
->rx_dma
),
282 GFP_ATOMIC
| __GFP_ZERO
);
286 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
290 for (i
= 0; i
< ring
->rx_ring_size
; i
++) {
291 dma_addr_t dma_addr
= dma_map_single(&netdev
->dev
,
292 ring
->rx_data
[i
] + NET_SKB_PAD
+ pad
,
295 if (unlikely(dma_mapping_error(&netdev
->dev
, dma_addr
)))
297 ring
->rx_dma
[i
].rxd1
= (unsigned int)dma_addr
;
299 if (priv
->flags
& FE_FLAG_RX_SG_DMA
)
300 ring
->rx_dma
[i
].rxd2
= RX_DMA_PLEN0(ring
->rx_buf_size
);
302 ring
->rx_dma
[i
].rxd2
= RX_DMA_LSO
;
304 ring
->rx_calc_idx
= ring
->rx_ring_size
- 1;
305 /* make sure that all changes to the dma ring are flushed before we
310 fe_reg_w32(ring
->rx_phys
, FE_REG_RX_BASE_PTR0
);
311 fe_reg_w32(ring
->rx_ring_size
, FE_REG_RX_MAX_CNT0
);
312 fe_reg_w32(ring
->rx_calc_idx
, FE_REG_RX_CALC_IDX0
);
313 fe_reg_w32(FE_PST_DRX_IDX0
, FE_REG_PDMA_RST_CFG
);
321 static void fe_txd_unmap(struct device
*dev
, struct fe_tx_buf
*tx_buf
)
323 if (dma_unmap_len(tx_buf
, dma_len0
))
325 dma_unmap_addr(tx_buf
, dma_addr0
),
326 dma_unmap_len(tx_buf
, dma_len0
),
329 if (dma_unmap_len(tx_buf
, dma_len1
))
331 dma_unmap_addr(tx_buf
, dma_addr1
),
332 dma_unmap_len(tx_buf
, dma_len1
),
335 dma_unmap_len_set(tx_buf
, dma_addr0
, 0);
336 dma_unmap_len_set(tx_buf
, dma_addr1
, 0);
337 if (tx_buf
->skb
&& (tx_buf
->skb
!= (struct sk_buff
*)DMA_DUMMY_DESC
))
338 dev_kfree_skb_any(tx_buf
->skb
);
342 static void fe_clean_tx(struct fe_priv
*priv
)
345 struct device
*dev
= &priv
->netdev
->dev
;
346 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
349 for (i
= 0; i
< ring
->tx_ring_size
; i
++)
350 fe_txd_unmap(dev
, &ring
->tx_buf
[i
]);
356 dma_free_coherent(dev
,
357 ring
->tx_ring_size
* sizeof(*ring
->tx_dma
),
363 netdev_reset_queue(priv
->netdev
);
366 static int fe_alloc_tx(struct fe_priv
*priv
)
369 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
371 ring
->tx_free_idx
= 0;
372 ring
->tx_next_idx
= 0;
373 ring
->tx_thresh
= max((unsigned long)ring
->tx_ring_size
>> 2,
376 ring
->tx_buf
= kcalloc(ring
->tx_ring_size
, sizeof(*ring
->tx_buf
),
381 ring
->tx_dma
= dma_alloc_coherent(&priv
->netdev
->dev
,
382 ring
->tx_ring_size
* sizeof(*ring
->tx_dma
),
384 GFP_ATOMIC
| __GFP_ZERO
);
388 for (i
= 0; i
< ring
->tx_ring_size
; i
++) {
389 if (priv
->soc
->tx_dma
)
390 priv
->soc
->tx_dma(&ring
->tx_dma
[i
]);
391 ring
->tx_dma
[i
].txd2
= TX_DMA_DESP2_DEF
;
393 /* make sure that all changes to the dma ring are flushed before we
398 fe_reg_w32(ring
->tx_phys
, FE_REG_TX_BASE_PTR0
);
399 fe_reg_w32(ring
->tx_ring_size
, FE_REG_TX_MAX_CNT0
);
400 fe_reg_w32(0, FE_REG_TX_CTX_IDX0
);
401 fe_reg_w32(FE_PST_DTX_IDX0
, FE_REG_PDMA_RST_CFG
);
409 static int fe_init_dma(struct fe_priv
*priv
)
413 err
= fe_alloc_tx(priv
);
417 err
= fe_alloc_rx(priv
);
424 static void fe_free_dma(struct fe_priv
*priv
)
430 void fe_stats_update(struct fe_priv
*priv
)
432 struct fe_hw_stats
*hwstats
= priv
->hw_stats
;
433 unsigned int base
= fe_reg_table
[FE_REG_FE_COUNTER_BASE
];
436 u64_stats_update_begin(&hwstats
->syncp
);
438 if (IS_ENABLED(CONFIG_SOC_MT7621
)) {
439 hwstats
->rx_bytes
+= fe_r32(base
);
440 stats
= fe_r32(base
+ 0x04);
442 hwstats
->rx_bytes
+= (stats
<< 32);
443 hwstats
->rx_packets
+= fe_r32(base
+ 0x08);
444 hwstats
->rx_overflow
+= fe_r32(base
+ 0x10);
445 hwstats
->rx_fcs_errors
+= fe_r32(base
+ 0x14);
446 hwstats
->rx_short_errors
+= fe_r32(base
+ 0x18);
447 hwstats
->rx_long_errors
+= fe_r32(base
+ 0x1c);
448 hwstats
->rx_checksum_errors
+= fe_r32(base
+ 0x20);
449 hwstats
->rx_flow_control_packets
+= fe_r32(base
+ 0x24);
450 hwstats
->tx_skip
+= fe_r32(base
+ 0x28);
451 hwstats
->tx_collisions
+= fe_r32(base
+ 0x2c);
452 hwstats
->tx_bytes
+= fe_r32(base
+ 0x30);
453 stats
= fe_r32(base
+ 0x34);
455 hwstats
->tx_bytes
+= (stats
<< 32);
456 hwstats
->tx_packets
+= fe_r32(base
+ 0x38);
458 hwstats
->tx_bytes
+= fe_r32(base
);
459 hwstats
->tx_packets
+= fe_r32(base
+ 0x04);
460 hwstats
->tx_skip
+= fe_r32(base
+ 0x08);
461 hwstats
->tx_collisions
+= fe_r32(base
+ 0x0c);
462 hwstats
->rx_bytes
+= fe_r32(base
+ 0x20);
463 hwstats
->rx_packets
+= fe_r32(base
+ 0x24);
464 hwstats
->rx_overflow
+= fe_r32(base
+ 0x28);
465 hwstats
->rx_fcs_errors
+= fe_r32(base
+ 0x2c);
466 hwstats
->rx_short_errors
+= fe_r32(base
+ 0x30);
467 hwstats
->rx_long_errors
+= fe_r32(base
+ 0x34);
468 hwstats
->rx_checksum_errors
+= fe_r32(base
+ 0x38);
469 hwstats
->rx_flow_control_packets
+= fe_r32(base
+ 0x3c);
472 u64_stats_update_end(&hwstats
->syncp
);
475 static void fe_get_stats64(struct net_device
*dev
,
476 struct rtnl_link_stats64
*storage
)
478 struct fe_priv
*priv
= netdev_priv(dev
);
479 struct fe_hw_stats
*hwstats
= priv
->hw_stats
;
480 unsigned int base
= fe_reg_table
[FE_REG_FE_COUNTER_BASE
];
484 netdev_stats_to_stats64(storage
, &dev
->stats
);
488 if (netif_running(dev
) && netif_device_present(dev
)) {
489 if (spin_trylock_bh(&hwstats
->stats_lock
)) {
490 fe_stats_update(priv
);
491 spin_unlock_bh(&hwstats
->stats_lock
);
496 start
= u64_stats_fetch_begin_irq(&hwstats
->syncp
);
497 storage
->rx_packets
= hwstats
->rx_packets
;
498 storage
->tx_packets
= hwstats
->tx_packets
;
499 storage
->rx_bytes
= hwstats
->rx_bytes
;
500 storage
->tx_bytes
= hwstats
->tx_bytes
;
501 storage
->collisions
= hwstats
->tx_collisions
;
502 storage
->rx_length_errors
= hwstats
->rx_short_errors
+
503 hwstats
->rx_long_errors
;
504 storage
->rx_over_errors
= hwstats
->rx_overflow
;
505 storage
->rx_crc_errors
= hwstats
->rx_fcs_errors
;
506 storage
->rx_errors
= hwstats
->rx_checksum_errors
;
507 storage
->tx_aborted_errors
= hwstats
->tx_skip
;
508 } while (u64_stats_fetch_retry_irq(&hwstats
->syncp
, start
));
510 storage
->tx_errors
= priv
->netdev
->stats
.tx_errors
;
511 storage
->rx_dropped
= priv
->netdev
->stats
.rx_dropped
;
512 storage
->tx_dropped
= priv
->netdev
->stats
.tx_dropped
;
515 static int fe_vlan_rx_add_vid(struct net_device
*dev
,
516 __be16 proto
, u16 vid
)
518 struct fe_priv
*priv
= netdev_priv(dev
);
519 u32 idx
= (vid
& 0xf);
522 if (!((fe_reg_table
[FE_REG_FE_DMA_VID_BASE
]) &&
523 (dev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)))
526 if (test_bit(idx
, &priv
->vlan_map
)) {
527 netdev_warn(dev
, "disable tx vlan offload\n");
528 dev
->wanted_features
&= ~NETIF_F_HW_VLAN_CTAG_TX
;
529 netdev_update_features(dev
);
531 vlan_cfg
= fe_r32(fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
535 vlan_cfg
|= (vid
<< 16);
537 vlan_cfg
&= 0xffff0000;
540 fe_w32(vlan_cfg
, fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
542 set_bit(idx
, &priv
->vlan_map
);
548 static int fe_vlan_rx_kill_vid(struct net_device
*dev
,
549 __be16 proto
, u16 vid
)
551 struct fe_priv
*priv
= netdev_priv(dev
);
552 u32 idx
= (vid
& 0xf);
554 if (!((fe_reg_table
[FE_REG_FE_DMA_VID_BASE
]) &&
555 (dev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)))
558 clear_bit(idx
, &priv
->vlan_map
);
563 static inline u32
fe_empty_txd(struct fe_tx_ring
*ring
)
566 return (u32
)(ring
->tx_ring_size
-
567 ((ring
->tx_next_idx
- ring
->tx_free_idx
) &
568 (ring
->tx_ring_size
- 1)));
571 struct fe_map_state
{
573 struct fe_tx_dma txd
;
579 static void fe_tx_dma_write_desc(struct fe_tx_ring
*ring
, struct fe_map_state
*st
)
581 fe_set_txd(&st
->txd
, &ring
->tx_dma
[st
->ring_idx
]);
582 memset(&st
->txd
, 0, sizeof(st
->txd
));
583 st
->txd
.txd4
= st
->def_txd4
;
584 st
->ring_idx
= NEXT_TX_DESP_IDX(st
->ring_idx
);
587 static int __fe_tx_dma_map_page(struct fe_tx_ring
*ring
, struct fe_map_state
*st
,
588 struct page
*page
, size_t offset
, size_t size
)
590 struct device
*dev
= st
->dev
;
591 struct fe_tx_buf
*tx_buf
;
592 dma_addr_t mapped_addr
;
594 mapped_addr
= dma_map_page(dev
, page
, offset
, size
, DMA_TO_DEVICE
);
595 if (unlikely(dma_mapping_error(dev
, mapped_addr
)))
598 if (st
->i
&& !(st
->i
& 1))
599 fe_tx_dma_write_desc(ring
, st
);
601 tx_buf
= &ring
->tx_buf
[st
->ring_idx
];
603 st
->txd
.txd3
= mapped_addr
;
604 st
->txd
.txd2
|= TX_DMA_PLEN1(size
);
605 dma_unmap_addr_set(tx_buf
, dma_addr1
, mapped_addr
);
606 dma_unmap_len_set(tx_buf
, dma_len1
, size
);
608 tx_buf
->skb
= (struct sk_buff
*)DMA_DUMMY_DESC
;
609 st
->txd
.txd1
= mapped_addr
;
610 st
->txd
.txd2
= TX_DMA_PLEN0(size
);
611 dma_unmap_addr_set(tx_buf
, dma_addr0
, mapped_addr
);
612 dma_unmap_len_set(tx_buf
, dma_len0
, size
);
619 static int fe_tx_dma_map_page(struct fe_tx_ring
*ring
, struct fe_map_state
*st
,
620 struct page
*page
, size_t offset
, size_t size
)
626 cur_size
= min_t(size_t, size
, TX_DMA_BUF_LEN
);
628 ret
= __fe_tx_dma_map_page(ring
, st
, page
, offset
, cur_size
);
639 static int fe_tx_dma_map_skb(struct fe_tx_ring
*ring
, struct fe_map_state
*st
,
642 struct page
*page
= virt_to_page(skb
->data
);
643 size_t offset
= offset_in_page(skb
->data
);
644 size_t size
= skb_headlen(skb
);
646 return fe_tx_dma_map_page(ring
, st
, page
, offset
, size
);
649 static inline struct sk_buff
*
650 fe_next_frag(struct sk_buff
*head
, struct sk_buff
*skb
)
655 if (skb_has_frag_list(skb
))
656 return skb_shinfo(skb
)->frag_list
;
662 static int fe_tx_map_dma(struct sk_buff
*skb
, struct net_device
*dev
,
663 int tx_num
, struct fe_tx_ring
*ring
)
665 struct fe_priv
*priv
= netdev_priv(dev
);
666 struct fe_map_state st
= {
668 .ring_idx
= ring
->tx_next_idx
,
670 struct sk_buff
*head
= skb
;
671 struct fe_tx_buf
*tx_buf
;
672 unsigned int nr_frags
;
675 /* init tx descriptor */
676 if (priv
->soc
->tx_dma
)
677 priv
->soc
->tx_dma(&st
.txd
);
679 st
.txd
.txd4
= TX_DMA_DESP4_DEF
;
680 st
.def_txd4
= st
.txd
.txd4
;
682 /* TX Checksum offload */
683 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
684 st
.txd
.txd4
|= TX_DMA_CHKSUM
;
686 /* VLAN header offload */
687 if (skb_vlan_tag_present(skb
)) {
688 u16 tag
= skb_vlan_tag_get(skb
);
690 if (IS_ENABLED(CONFIG_SOC_MT7621
))
691 st
.txd
.txd4
|= TX_DMA_INS_VLAN_MT7621
| tag
;
693 st
.txd
.txd4
|= TX_DMA_INS_VLAN
|
694 ((tag
>> VLAN_PRIO_SHIFT
) << 4) |
698 /* TSO: fill MSS info in tcp checksum field */
699 if (skb_is_gso(skb
)) {
700 if (skb_cow_head(skb
, 0)) {
701 netif_warn(priv
, tx_err
, dev
,
702 "GSO expand head fail.\n");
705 if (skb_shinfo(skb
)->gso_type
&
706 (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
707 st
.txd
.txd4
|= TX_DMA_TSO
;
708 tcp_hdr(skb
)->check
= htons(skb_shinfo(skb
)->gso_size
);
713 if (skb_headlen(skb
) && fe_tx_dma_map_skb(ring
, &st
, skb
))
717 nr_frags
= skb_shinfo(skb
)->nr_frags
;
718 for (i
= 0; i
< nr_frags
; i
++) {
719 struct skb_frag_struct
*frag
;
721 frag
= &skb_shinfo(skb
)->frags
[i
];
722 if (fe_tx_dma_map_page(ring
, &st
, skb_frag_page(frag
),
723 frag
->page_offset
, skb_frag_size(frag
)))
727 skb
= fe_next_frag(head
, skb
);
731 /* set last segment */
733 st
.txd
.txd2
|= TX_DMA_LS0
;
735 st
.txd
.txd2
|= TX_DMA_LS1
;
737 /* store skb to cleanup */
738 tx_buf
= &ring
->tx_buf
[st
.ring_idx
];
741 netdev_sent_queue(dev
, head
->len
);
742 skb_tx_timestamp(head
);
744 fe_tx_dma_write_desc(ring
, &st
);
745 ring
->tx_next_idx
= st
.ring_idx
;
747 /* make sure that all changes to the dma ring are flushed before we
751 if (unlikely(fe_empty_txd(ring
) <= ring
->tx_thresh
)) {
752 netif_stop_queue(dev
);
754 if (unlikely(fe_empty_txd(ring
) > ring
->tx_thresh
))
755 netif_wake_queue(dev
);
758 if (netif_xmit_stopped(netdev_get_tx_queue(dev
, 0)) || !head
->xmit_more
)
759 fe_reg_w32(ring
->tx_next_idx
, FE_REG_TX_CTX_IDX0
);
764 j
= ring
->tx_next_idx
;
765 for (i
= 0; i
< tx_num
; i
++) {
767 fe_txd_unmap(&dev
->dev
, &ring
->tx_buf
[j
]);
768 ring
->tx_dma
[j
].txd2
= TX_DMA_DESP2_DEF
;
770 j
= NEXT_TX_DESP_IDX(j
);
772 /* make sure that all changes to the dma ring are flushed before we
781 static inline int fe_skb_padto(struct sk_buff
*skb
, struct fe_priv
*priv
)
787 if (unlikely(skb
->len
< VLAN_ETH_ZLEN
)) {
788 if ((priv
->flags
& FE_FLAG_PADDING_64B
) &&
789 !(priv
->flags
& FE_FLAG_PADDING_BUG
))
792 if (skb_vlan_tag_present(skb
))
794 else if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
))
796 else if (!(priv
->flags
& FE_FLAG_PADDING_64B
))
801 if (skb
->len
< len
) {
802 ret
= skb_pad(skb
, len
- skb
->len
);
806 skb_set_tail_pointer(skb
, len
);
813 static inline int fe_cal_txd_req(struct sk_buff
*skb
)
815 struct sk_buff
*head
= skb
;
817 struct skb_frag_struct
*frag
;
821 if (skb_is_gso(skb
)) {
822 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
823 frag
= &skb_shinfo(skb
)->frags
[i
];
824 nfrags
+= DIV_ROUND_UP(frag
->size
, TX_DMA_BUF_LEN
);
827 nfrags
+= skb_shinfo(skb
)->nr_frags
;
830 skb
= fe_next_frag(head
, skb
);
834 return DIV_ROUND_UP(nfrags
, 2);
837 static int fe_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
839 struct fe_priv
*priv
= netdev_priv(dev
);
840 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
841 struct net_device_stats
*stats
= &dev
->stats
;
845 if (fe_skb_padto(skb
, priv
)) {
846 netif_warn(priv
, tx_err
, dev
, "tx padding failed!\n");
850 tx_num
= fe_cal_txd_req(skb
);
851 if (unlikely(fe_empty_txd(ring
) <= tx_num
)) {
852 netif_stop_queue(dev
);
853 netif_err(priv
, tx_queued
, dev
,
854 "Tx Ring full when queue awake!\n");
855 return NETDEV_TX_BUSY
;
858 if (fe_tx_map_dma(skb
, dev
, tx_num
, ring
) < 0) {
862 stats
->tx_bytes
+= len
;
868 static int fe_poll_rx(struct napi_struct
*napi
, int budget
,
869 struct fe_priv
*priv
, u32 rx_intr
)
871 struct net_device
*netdev
= priv
->netdev
;
872 struct net_device_stats
*stats
= &netdev
->stats
;
873 struct fe_soc_data
*soc
= priv
->soc
;
874 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
875 int idx
= ring
->rx_calc_idx
;
879 struct fe_rx_dma
*rxd
, trxd
;
882 if (netdev
->features
& NETIF_F_RXCSUM
)
883 checksum_bit
= soc
->checksum_bit
;
887 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
892 while (done
< budget
) {
896 idx
= NEXT_RX_DESP_IDX(idx
);
897 rxd
= &ring
->rx_dma
[idx
];
898 data
= ring
->rx_data
[idx
];
900 fe_get_rxd(&trxd
, rxd
);
901 if (!(trxd
.rxd2
& RX_DMA_DONE
))
904 /* alloc new buffer */
905 new_data
= page_frag_alloc(&ring
->frag_cache
, ring
->frag_size
,
907 if (unlikely(!new_data
)) {
911 dma_addr
= dma_map_single(&netdev
->dev
,
912 new_data
+ NET_SKB_PAD
+ pad
,
915 if (unlikely(dma_mapping_error(&netdev
->dev
, dma_addr
))) {
916 skb_free_frag(new_data
);
921 skb
= build_skb(data
, ring
->frag_size
);
922 if (unlikely(!skb
)) {
923 skb_free_frag(new_data
);
926 skb_reserve(skb
, NET_SKB_PAD
+ NET_IP_ALIGN
);
928 dma_unmap_single(&netdev
->dev
, trxd
.rxd1
,
929 ring
->rx_buf_size
, DMA_FROM_DEVICE
);
930 pktlen
= RX_DMA_GET_PLEN0(trxd
.rxd2
);
932 skb_put(skb
, pktlen
);
933 if (trxd
.rxd4
& checksum_bit
)
934 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
936 skb_checksum_none_assert(skb
);
937 skb
->protocol
= eth_type_trans(skb
, netdev
);
939 if (netdev
->features
& NETIF_F_HW_VLAN_CTAG_RX
&&
940 RX_DMA_VID(trxd
.rxd3
))
941 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
),
942 RX_DMA_VID(trxd
.rxd3
));
944 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
945 if (mtk_offload_check_rx(priv
, skb
, trxd
.rxd4
) == 0) {
948 stats
->rx_bytes
+= pktlen
;
950 napi_gro_receive(napi
, skb
);
951 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
956 ring
->rx_data
[idx
] = new_data
;
957 rxd
->rxd1
= (unsigned int)dma_addr
;
960 if (priv
->flags
& FE_FLAG_RX_SG_DMA
)
961 rxd
->rxd2
= RX_DMA_PLEN0(ring
->rx_buf_size
);
963 rxd
->rxd2
= RX_DMA_LSO
;
965 ring
->rx_calc_idx
= idx
;
966 /* make sure that all changes to the dma ring are flushed before
970 fe_reg_w32(ring
->rx_calc_idx
, FE_REG_RX_CALC_IDX0
);
975 fe_reg_w32(rx_intr
, FE_REG_FE_INT_STATUS
);
980 static int fe_poll_tx(struct fe_priv
*priv
, int budget
, u32 tx_intr
,
983 struct net_device
*netdev
= priv
->netdev
;
984 struct device
*dev
= &netdev
->dev
;
985 unsigned int bytes_compl
= 0;
987 struct fe_tx_buf
*tx_buf
;
990 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
992 idx
= ring
->tx_free_idx
;
993 hwidx
= fe_reg_r32(FE_REG_TX_DTX_IDX0
);
995 while ((idx
!= hwidx
) && budget
) {
996 tx_buf
= &ring
->tx_buf
[idx
];
1002 if (skb
!= (struct sk_buff
*)DMA_DUMMY_DESC
) {
1003 bytes_compl
+= skb
->len
;
1007 fe_txd_unmap(dev
, tx_buf
);
1008 idx
= NEXT_TX_DESP_IDX(idx
);
1010 ring
->tx_free_idx
= idx
;
1013 /* read hw index again make sure no new tx packet */
1014 hwidx
= fe_reg_r32(FE_REG_TX_DTX_IDX0
);
1016 fe_reg_w32(tx_intr
, FE_REG_FE_INT_STATUS
);
1024 netdev_completed_queue(netdev
, done
, bytes_compl
);
1026 if (unlikely(netif_queue_stopped(netdev
) &&
1027 (fe_empty_txd(ring
) > ring
->tx_thresh
)))
1028 netif_wake_queue(netdev
);
1034 static int fe_poll(struct napi_struct
*napi
, int budget
)
1036 struct fe_priv
*priv
= container_of(napi
, struct fe_priv
, rx_napi
);
1037 struct fe_hw_stats
*hwstat
= priv
->hw_stats
;
1038 int tx_done
, rx_done
, tx_again
;
1039 u32 status
, fe_status
, status_reg
, mask
;
1040 u32 tx_intr
, rx_intr
, status_intr
;
1042 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1044 tx_intr
= priv
->soc
->tx_int
;
1045 rx_intr
= priv
->soc
->rx_int
;
1046 status_intr
= priv
->soc
->status_int
;
1051 if (fe_reg_table
[FE_REG_FE_INT_STATUS2
]) {
1052 fe_status
= fe_reg_r32(FE_REG_FE_INT_STATUS2
);
1053 status_reg
= FE_REG_FE_INT_STATUS2
;
1055 status_reg
= FE_REG_FE_INT_STATUS
;
1058 if (status
& tx_intr
)
1059 tx_done
= fe_poll_tx(priv
, budget
, tx_intr
, &tx_again
);
1061 if (status
& rx_intr
)
1062 rx_done
= fe_poll_rx(napi
, budget
, priv
, rx_intr
);
1064 if (unlikely(fe_status
& status_intr
)) {
1065 if (hwstat
&& spin_trylock(&hwstat
->stats_lock
)) {
1066 fe_stats_update(priv
);
1067 spin_unlock(&hwstat
->stats_lock
);
1069 fe_reg_w32(status_intr
, status_reg
);
1072 if (unlikely(netif_msg_intr(priv
))) {
1073 mask
= fe_reg_r32(FE_REG_FE_INT_ENABLE
);
1074 netdev_info(priv
->netdev
,
1075 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1076 tx_done
, rx_done
, status
, mask
);
1079 if (!tx_again
&& (rx_done
< budget
)) {
1080 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1081 if (status
& (tx_intr
| rx_intr
)) {
1082 /* let napi poll again */
1087 napi_complete_done(napi
, rx_done
);
1088 fe_int_enable(tx_intr
| rx_intr
);
1097 static void fe_tx_timeout(struct net_device
*dev
)
1099 struct fe_priv
*priv
= netdev_priv(dev
);
1100 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
1102 priv
->netdev
->stats
.tx_errors
++;
1103 netif_err(priv
, tx_err
, dev
,
1104 "transmit timed out\n");
1105 netif_info(priv
, drv
, dev
, "dma_cfg:%08x\n",
1106 fe_reg_r32(FE_REG_PDMA_GLO_CFG
));
1107 netif_info(priv
, drv
, dev
, "tx_ring=%d, "
1108 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1109 0, fe_reg_r32(FE_REG_TX_BASE_PTR0
),
1110 fe_reg_r32(FE_REG_TX_MAX_CNT0
),
1111 fe_reg_r32(FE_REG_TX_CTX_IDX0
),
1112 fe_reg_r32(FE_REG_TX_DTX_IDX0
),
1115 netif_info(priv
, drv
, dev
,
1116 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1117 0, fe_reg_r32(FE_REG_RX_BASE_PTR0
),
1118 fe_reg_r32(FE_REG_RX_MAX_CNT0
),
1119 fe_reg_r32(FE_REG_RX_CALC_IDX0
),
1120 fe_reg_r32(FE_REG_RX_DRX_IDX0
));
1122 if (!test_and_set_bit(FE_FLAG_RESET_PENDING
, priv
->pending_flags
))
1123 schedule_work(&priv
->pending_work
);
1126 static irqreturn_t
fe_handle_irq(int irq
, void *dev
)
1128 struct fe_priv
*priv
= netdev_priv(dev
);
1129 u32 status
, int_mask
;
1131 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1133 if (unlikely(!status
))
1136 int_mask
= (priv
->soc
->rx_int
| priv
->soc
->tx_int
);
1137 if (likely(status
& int_mask
)) {
1138 if (likely(napi_schedule_prep(&priv
->rx_napi
))) {
1139 fe_int_disable(int_mask
);
1140 __napi_schedule(&priv
->rx_napi
);
1143 fe_reg_w32(status
, FE_REG_FE_INT_STATUS
);
1149 #ifdef CONFIG_NET_POLL_CONTROLLER
1150 static void fe_poll_controller(struct net_device
*dev
)
1152 struct fe_priv
*priv
= netdev_priv(dev
);
1153 u32 int_mask
= priv
->soc
->tx_int
| priv
->soc
->rx_int
;
1155 fe_int_disable(int_mask
);
1156 fe_handle_irq(dev
->irq
, dev
);
1157 fe_int_enable(int_mask
);
1161 int fe_set_clock_cycle(struct fe_priv
*priv
)
1163 unsigned long sysclk
= priv
->sysclk
;
1165 sysclk
/= FE_US_CYC_CNT_DIVISOR
;
1166 sysclk
<<= FE_US_CYC_CNT_SHIFT
;
1168 fe_w32((fe_r32(FE_FE_GLO_CFG
) &
1169 ~(FE_US_CYC_CNT_MASK
<< FE_US_CYC_CNT_SHIFT
)) |
1175 void fe_fwd_config(struct fe_priv
*priv
)
1179 fwd_cfg
= fe_r32(FE_GDMA1_FWD_CFG
);
1181 /* disable jumbo frame */
1182 if (priv
->flags
& FE_FLAG_JUMBO_FRAME
)
1183 fwd_cfg
&= ~FE_GDM1_JMB_EN
;
1185 /* set unicast/multicast/broadcast frame to cpu */
1188 fe_w32(fwd_cfg
, FE_GDMA1_FWD_CFG
);
1191 static void fe_rxcsum_config(bool enable
)
1194 fe_w32(fe_r32(FE_GDMA1_FWD_CFG
) | (FE_GDM1_ICS_EN
|
1195 FE_GDM1_TCS_EN
| FE_GDM1_UCS_EN
),
1198 fe_w32(fe_r32(FE_GDMA1_FWD_CFG
) & ~(FE_GDM1_ICS_EN
|
1199 FE_GDM1_TCS_EN
| FE_GDM1_UCS_EN
),
1203 static void fe_txcsum_config(bool enable
)
1206 fe_w32(fe_r32(FE_CDMA_CSG_CFG
) | (FE_ICS_GEN_EN
|
1207 FE_TCS_GEN_EN
| FE_UCS_GEN_EN
),
1210 fe_w32(fe_r32(FE_CDMA_CSG_CFG
) & ~(FE_ICS_GEN_EN
|
1211 FE_TCS_GEN_EN
| FE_UCS_GEN_EN
),
1215 void fe_csum_config(struct fe_priv
*priv
)
1217 struct net_device
*dev
= priv_netdev(priv
);
1219 fe_txcsum_config((dev
->features
& NETIF_F_IP_CSUM
));
1220 fe_rxcsum_config((dev
->features
& NETIF_F_RXCSUM
));
1223 static int fe_hw_init(struct net_device
*dev
)
1225 struct fe_priv
*priv
= netdev_priv(dev
);
1228 err
= devm_request_irq(priv
->dev
, dev
->irq
, fe_handle_irq
, 0,
1229 dev_name(priv
->dev
), dev
);
1233 if (priv
->soc
->set_mac
)
1234 priv
->soc
->set_mac(priv
, dev
->dev_addr
);
1236 fe_hw_set_macaddr(priv
, dev
->dev_addr
);
1238 /* disable delay interrupt */
1239 fe_reg_w32(0, FE_REG_DLY_INT_CFG
);
1241 fe_int_disable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1243 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1244 if (fe_reg_table
[FE_REG_FE_DMA_VID_BASE
])
1245 for (i
= 0; i
< 16; i
+= 2)
1246 fe_w32(((i
+ 1) << 16) + i
,
1247 fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
1250 if (priv
->soc
->fwd_config(priv
))
1251 netdev_err(dev
, "unable to get clock\n");
1253 if (fe_reg_table
[FE_REG_FE_RST_GL
]) {
1254 fe_reg_w32(1, FE_REG_FE_RST_GL
);
1255 fe_reg_w32(0, FE_REG_FE_RST_GL
);
1261 static int fe_open(struct net_device
*dev
)
1263 struct fe_priv
*priv
= netdev_priv(dev
);
1264 unsigned long flags
;
1268 err
= fe_init_dma(priv
);
1274 spin_lock_irqsave(&priv
->page_lock
, flags
);
1276 val
= FE_TX_WB_DDONE
| FE_RX_DMA_EN
| FE_TX_DMA_EN
;
1277 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
1278 val
|= FE_RX_2B_OFFSET
;
1279 val
|= priv
->soc
->pdma_glo_cfg
;
1280 fe_reg_w32(val
, FE_REG_PDMA_GLO_CFG
);
1282 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
1285 priv
->phy
->start(priv
);
1287 if (priv
->soc
->has_carrier
&& priv
->soc
->has_carrier(priv
))
1288 netif_carrier_on(dev
);
1290 napi_enable(&priv
->rx_napi
);
1291 fe_int_enable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1292 netif_start_queue(dev
);
1293 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1294 mtk_ppe_probe(priv
);
1300 static int fe_stop(struct net_device
*dev
)
1302 struct fe_priv
*priv
= netdev_priv(dev
);
1303 unsigned long flags
;
1306 netif_tx_disable(dev
);
1307 fe_int_disable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1308 napi_disable(&priv
->rx_napi
);
1311 priv
->phy
->stop(priv
);
1313 spin_lock_irqsave(&priv
->page_lock
, flags
);
1315 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG
) &
1316 ~(FE_TX_WB_DDONE
| FE_RX_DMA_EN
| FE_TX_DMA_EN
),
1317 FE_REG_PDMA_GLO_CFG
);
1318 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
1321 for (i
= 0; i
< 10; i
++) {
1322 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG
) &
1323 (FE_TX_DMA_BUSY
| FE_RX_DMA_BUSY
)) {
1332 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1333 mtk_ppe_remove(priv
);
1339 static void fe_reset_phy(struct fe_priv
*priv
)
1342 struct gpio_desc
*phy_reset
;
1344 phy_reset
= devm_gpiod_get_optional(priv
->dev
, "phy-reset",
1349 if (IS_ERR(phy_reset
)) {
1350 dev_err(priv
->dev
, "Error acquiring reset gpio pins: %ld\n",
1351 PTR_ERR(phy_reset
));
1355 err
= of_property_read_u32(priv
->dev
->of_node
, "phy-reset-duration",
1357 if (!err
&& msec
> 1000)
1363 usleep_range(msec
* 1000, msec
* 1000 + 1000);
1365 gpiod_set_value(phy_reset
, 0);
1368 static int __init
fe_init(struct net_device
*dev
)
1370 struct fe_priv
*priv
= netdev_priv(dev
);
1371 struct device_node
*port
;
1372 const char *mac_addr
;
1375 priv
->soc
->reset_fe();
1377 if (priv
->soc
->switch_init
)
1378 if (priv
->soc
->switch_init(priv
)) {
1379 netdev_err(dev
, "failed to initialize switch core\n");
1385 mac_addr
= of_get_mac_address(priv
->dev
->of_node
);
1387 ether_addr_copy(dev
->dev_addr
, mac_addr
);
1389 /* If the mac address is invalid, use random mac address */
1390 if (!is_valid_ether_addr(dev
->dev_addr
)) {
1391 random_ether_addr(dev
->dev_addr
);
1392 dev_err(priv
->dev
, "generated random MAC address %pM\n",
1396 err
= fe_mdio_init(priv
);
1400 if (priv
->soc
->port_init
)
1401 for_each_child_of_node(priv
->dev
->of_node
, port
)
1402 if (of_device_is_compatible(port
, "mediatek,eth-port") &&
1403 of_device_is_available(port
))
1404 priv
->soc
->port_init(priv
, port
);
1407 err
= priv
->phy
->connect(priv
);
1409 goto err_phy_disconnect
;
1412 err
= fe_hw_init(dev
);
1414 goto err_phy_disconnect
;
1416 if ((priv
->flags
& FE_FLAG_HAS_SWITCH
) && priv
->soc
->switch_config
)
1417 priv
->soc
->switch_config(priv
);
1423 priv
->phy
->disconnect(priv
);
1424 fe_mdio_cleanup(priv
);
1429 static void fe_uninit(struct net_device
*dev
)
1431 struct fe_priv
*priv
= netdev_priv(dev
);
1434 priv
->phy
->disconnect(priv
);
1435 fe_mdio_cleanup(priv
);
1437 fe_reg_w32(0, FE_REG_FE_INT_ENABLE
);
1438 free_irq(dev
->irq
, dev
);
1441 static int fe_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1443 struct fe_priv
*priv
= netdev_priv(dev
);
1449 return phy_mii_ioctl(priv
->phy_dev
, ifr
, cmd
);
1452 static int fe_change_mtu(struct net_device
*dev
, int new_mtu
)
1454 struct fe_priv
*priv
= netdev_priv(dev
);
1455 int frag_size
, old_mtu
;
1461 if (!(priv
->flags
& FE_FLAG_JUMBO_FRAME
))
1464 /* return early if the buffer sizes will not change */
1465 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
1467 if (old_mtu
> ETH_DATA_LEN
&& new_mtu
> ETH_DATA_LEN
)
1470 if (new_mtu
<= ETH_DATA_LEN
)
1471 priv
->rx_ring
.frag_size
= fe_max_frag_size(ETH_DATA_LEN
);
1473 priv
->rx_ring
.frag_size
= PAGE_SIZE
;
1474 priv
->rx_ring
.rx_buf_size
= fe_max_buf_size(priv
->rx_ring
.frag_size
);
1476 if (!netif_running(dev
))
1480 if (!IS_ENABLED(CONFIG_SOC_MT7621
)) {
1481 fwd_cfg
= fe_r32(FE_GDMA1_FWD_CFG
);
1482 if (new_mtu
<= ETH_DATA_LEN
) {
1483 fwd_cfg
&= ~FE_GDM1_JMB_EN
;
1485 frag_size
= fe_max_frag_size(new_mtu
);
1486 fwd_cfg
&= ~(FE_GDM1_JMB_LEN_MASK
<< FE_GDM1_JMB_LEN_SHIFT
);
1487 fwd_cfg
|= (DIV_ROUND_UP(frag_size
, 1024) <<
1488 FE_GDM1_JMB_LEN_SHIFT
) | FE_GDM1_JMB_EN
;
1490 fe_w32(fwd_cfg
, FE_GDMA1_FWD_CFG
);
1493 return fe_open(dev
);
1496 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1498 fe_flow_offload(enum flow_offload_type type
, struct flow_offload
*flow
,
1499 struct flow_offload_hw_path
*src
,
1500 struct flow_offload_hw_path
*dest
)
1502 struct fe_priv
*priv
;
1504 if (src
->dev
!= dest
->dev
)
1507 priv
= netdev_priv(src
->dev
);
1509 return mtk_flow_offload(priv
, type
, flow
, src
, dest
);
1513 static const struct net_device_ops fe_netdev_ops
= {
1514 .ndo_init
= fe_init
,
1515 .ndo_uninit
= fe_uninit
,
1516 .ndo_open
= fe_open
,
1517 .ndo_stop
= fe_stop
,
1518 .ndo_start_xmit
= fe_start_xmit
,
1519 .ndo_set_mac_address
= fe_set_mac_address
,
1520 .ndo_validate_addr
= eth_validate_addr
,
1521 .ndo_do_ioctl
= fe_do_ioctl
,
1522 .ndo_change_mtu
= fe_change_mtu
,
1523 .ndo_tx_timeout
= fe_tx_timeout
,
1524 .ndo_get_stats64
= fe_get_stats64
,
1525 .ndo_vlan_rx_add_vid
= fe_vlan_rx_add_vid
,
1526 .ndo_vlan_rx_kill_vid
= fe_vlan_rx_kill_vid
,
1527 #ifdef CONFIG_NET_POLL_CONTROLLER
1528 .ndo_poll_controller
= fe_poll_controller
,
1530 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1531 .ndo_flow_offload
= fe_flow_offload
,
1535 static void fe_reset_pending(struct fe_priv
*priv
)
1537 struct net_device
*dev
= priv
->netdev
;
1545 netif_alert(priv
, ifup
, dev
,
1546 "Driver up/down cycle failed, closing device.\n");
1552 static const struct fe_work_t fe_work
[] = {
1553 {FE_FLAG_RESET_PENDING
, fe_reset_pending
},
1556 static void fe_pending_work(struct work_struct
*work
)
1558 struct fe_priv
*priv
= container_of(work
, struct fe_priv
, pending_work
);
1562 for (i
= 0; i
< ARRAY_SIZE(fe_work
); i
++) {
1563 pending
= test_and_clear_bit(fe_work
[i
].bitnr
,
1564 priv
->pending_flags
);
1566 fe_work
[i
].action(priv
);
1570 static int fe_probe(struct platform_device
*pdev
)
1572 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1573 const struct of_device_id
*match
;
1574 struct fe_soc_data
*soc
;
1575 struct net_device
*netdev
;
1576 struct fe_priv
*priv
;
1578 int err
, napi_weight
;
1580 device_reset(&pdev
->dev
);
1582 match
= of_match_device(of_fe_match
, &pdev
->dev
);
1583 soc
= (struct fe_soc_data
*)match
->data
;
1586 fe_reg_table
= soc
->reg_table
;
1588 soc
->reg_table
= fe_reg_table
;
1590 fe_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1591 if (IS_ERR(fe_base
)) {
1592 err
= -EADDRNOTAVAIL
;
1596 netdev
= alloc_etherdev(sizeof(*priv
));
1598 dev_err(&pdev
->dev
, "alloc_etherdev failed\n");
1603 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
1604 netdev
->netdev_ops
= &fe_netdev_ops
;
1605 netdev
->base_addr
= (unsigned long)fe_base
;
1607 netdev
->irq
= platform_get_irq(pdev
, 0);
1608 if (netdev
->irq
< 0) {
1609 dev_err(&pdev
->dev
, "no IRQ resource found\n");
1615 soc
->init_data(soc
, netdev
);
1616 netdev
->vlan_features
= netdev
->hw_features
&
1617 ~(NETIF_F_HW_VLAN_CTAG_TX
|
1618 NETIF_F_HW_VLAN_CTAG_RX
);
1619 netdev
->features
|= netdev
->hw_features
;
1621 if (IS_ENABLED(CONFIG_SOC_MT7621
))
1622 netdev
->max_mtu
= 2048;
1624 /* fake rx vlan filter func. to support tx vlan offload func */
1625 if (fe_reg_table
[FE_REG_FE_DMA_VID_BASE
])
1626 netdev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
1628 priv
= netdev_priv(netdev
);
1629 spin_lock_init(&priv
->page_lock
);
1630 if (fe_reg_table
[FE_REG_FE_COUNTER_BASE
]) {
1631 priv
->hw_stats
= kzalloc(sizeof(*priv
->hw_stats
), GFP_KERNEL
);
1632 if (!priv
->hw_stats
) {
1636 spin_lock_init(&priv
->hw_stats
->stats_lock
);
1639 sysclk
= devm_clk_get(&pdev
->dev
, NULL
);
1640 if (!IS_ERR(sysclk
)) {
1641 priv
->sysclk
= clk_get_rate(sysclk
);
1642 } else if ((priv
->flags
& FE_FLAG_CALIBRATE_CLK
)) {
1643 dev_err(&pdev
->dev
, "this soc needs a clk for calibration\n");
1648 priv
->switch_np
= of_parse_phandle(pdev
->dev
.of_node
, "mediatek,switch", 0);
1649 if ((priv
->flags
& FE_FLAG_HAS_SWITCH
) && !priv
->switch_np
) {
1650 dev_err(&pdev
->dev
, "failed to read switch phandle\n");
1655 priv
->netdev
= netdev
;
1656 priv
->dev
= &pdev
->dev
;
1658 priv
->msg_enable
= netif_msg_init(fe_msg_level
, FE_DEFAULT_MSG_ENABLE
);
1659 priv
->rx_ring
.frag_size
= fe_max_frag_size(ETH_DATA_LEN
);
1660 priv
->rx_ring
.rx_buf_size
= fe_max_buf_size(priv
->rx_ring
.frag_size
);
1661 priv
->tx_ring
.tx_ring_size
= NUM_DMA_DESC
;
1662 priv
->rx_ring
.rx_ring_size
= NUM_DMA_DESC
;
1663 INIT_WORK(&priv
->pending_work
, fe_pending_work
);
1664 u64_stats_init(&priv
->hw_stats
->syncp
);
1667 if (priv
->flags
& FE_FLAG_NAPI_WEIGHT
) {
1669 priv
->tx_ring
.tx_ring_size
*= 4;
1670 priv
->rx_ring
.rx_ring_size
*= 4;
1672 netif_napi_add(netdev
, &priv
->rx_napi
, fe_poll
, napi_weight
);
1673 fe_set_ethtool_ops(netdev
);
1675 err
= register_netdev(netdev
);
1677 dev_err(&pdev
->dev
, "error bringing up device\n");
1681 platform_set_drvdata(pdev
, netdev
);
1683 netif_info(priv
, probe
, netdev
, "mediatek frame engine at 0x%08lx, irq %d\n",
1684 netdev
->base_addr
, netdev
->irq
);
1689 free_netdev(netdev
);
1691 devm_iounmap(&pdev
->dev
, fe_base
);
1696 static int fe_remove(struct platform_device
*pdev
)
1698 struct net_device
*dev
= platform_get_drvdata(pdev
);
1699 struct fe_priv
*priv
= netdev_priv(dev
);
1701 netif_napi_del(&priv
->rx_napi
);
1702 kfree(priv
->hw_stats
);
1704 cancel_work_sync(&priv
->pending_work
);
1706 unregister_netdev(dev
);
1708 platform_set_drvdata(pdev
, NULL
);
1713 static struct platform_driver fe_driver
= {
1715 .remove
= fe_remove
,
1717 .name
= "mtk_soc_eth",
1718 .owner
= THIS_MODULE
,
1719 .of_match_table
= of_fe_match
,
1723 module_platform_driver(fe_driver
);
1725 MODULE_LICENSE("GPL");
1726 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1727 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1728 MODULE_VERSION(MTK_FE_DRV_VERSION
);