1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
32 #include <linux/bug.h>
33 #include <linux/netfilter.h>
34 #include <net/netfilter/nf_flow_table.h>
36 #include <asm/mach-ralink/ralink_regs.h>
38 #include "mtk_eth_soc.h"
42 #define MAX_RX_LENGTH 1536
43 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
44 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
45 #define DMA_DUMMY_DESC 0xffffffff
46 #define FE_DEFAULT_MSG_ENABLE \
56 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
57 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
58 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
59 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
61 #define SYSC_REG_RSTCTRL 0x34
63 static int fe_msg_level
= -1;
64 module_param_named(msg_level
, fe_msg_level
, int, 0);
65 MODULE_PARM_DESC(msg_level
, "Message level (-1=defaults,0=none,...,16=all)");
67 static const u16 fe_reg_table_default
[FE_REG_COUNT
] = {
68 [FE_REG_PDMA_GLO_CFG
] = FE_PDMA_GLO_CFG
,
69 [FE_REG_PDMA_RST_CFG
] = FE_PDMA_RST_CFG
,
70 [FE_REG_DLY_INT_CFG
] = FE_DLY_INT_CFG
,
71 [FE_REG_TX_BASE_PTR0
] = FE_TX_BASE_PTR0
,
72 [FE_REG_TX_MAX_CNT0
] = FE_TX_MAX_CNT0
,
73 [FE_REG_TX_CTX_IDX0
] = FE_TX_CTX_IDX0
,
74 [FE_REG_TX_DTX_IDX0
] = FE_TX_DTX_IDX0
,
75 [FE_REG_RX_BASE_PTR0
] = FE_RX_BASE_PTR0
,
76 [FE_REG_RX_MAX_CNT0
] = FE_RX_MAX_CNT0
,
77 [FE_REG_RX_CALC_IDX0
] = FE_RX_CALC_IDX0
,
78 [FE_REG_RX_DRX_IDX0
] = FE_RX_DRX_IDX0
,
79 [FE_REG_FE_INT_ENABLE
] = FE_FE_INT_ENABLE
,
80 [FE_REG_FE_INT_STATUS
] = FE_FE_INT_STATUS
,
81 [FE_REG_FE_DMA_VID_BASE
] = FE_DMA_VID0
,
82 [FE_REG_FE_COUNTER_BASE
] = FE_GDMA1_TX_GBCNT
,
83 [FE_REG_FE_RST_GL
] = FE_FE_RST_GL
,
86 static const u16
*fe_reg_table
= fe_reg_table_default
;
90 void (*action
)(struct fe_priv
*);
93 static void __iomem
*fe_base
;
95 void fe_w32(u32 val
, unsigned reg
)
97 __raw_writel(val
, fe_base
+ reg
);
100 u32
fe_r32(unsigned reg
)
102 return __raw_readl(fe_base
+ reg
);
105 void fe_reg_w32(u32 val
, enum fe_reg reg
)
107 fe_w32(val
, fe_reg_table
[reg
]);
110 u32
fe_reg_r32(enum fe_reg reg
)
112 return fe_r32(fe_reg_table
[reg
]);
115 void fe_m32(struct fe_priv
*eth
, u32 clear
, u32 set
, unsigned reg
)
119 spin_lock(ð
->page_lock
);
120 val
= __raw_readl(fe_base
+ reg
);
123 __raw_writel(val
, fe_base
+ reg
);
124 spin_unlock(ð
->page_lock
);
127 void fe_reset(u32 reset_bits
)
131 t
= rt_sysc_r32(SYSC_REG_RSTCTRL
);
133 rt_sysc_w32(t
, SYSC_REG_RSTCTRL
);
134 usleep_range(10, 20);
137 rt_sysc_w32(t
, SYSC_REG_RSTCTRL
);
138 usleep_range(10, 20);
141 static inline void fe_int_disable(u32 mask
)
143 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE
) & ~mask
,
144 FE_REG_FE_INT_ENABLE
);
146 fe_reg_r32(FE_REG_FE_INT_ENABLE
);
149 static inline void fe_int_enable(u32 mask
)
151 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE
) | mask
,
152 FE_REG_FE_INT_ENABLE
);
154 fe_reg_r32(FE_REG_FE_INT_ENABLE
);
157 static inline void fe_hw_set_macaddr(struct fe_priv
*priv
, unsigned char *mac
)
161 spin_lock_irqsave(&priv
->page_lock
, flags
);
162 fe_w32((mac
[0] << 8) | mac
[1], FE_GDMA1_MAC_ADRH
);
163 fe_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
165 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
168 static int fe_set_mac_address(struct net_device
*dev
, void *p
)
170 int ret
= eth_mac_addr(dev
, p
);
173 struct fe_priv
*priv
= netdev_priv(dev
);
175 if (priv
->soc
->set_mac
)
176 priv
->soc
->set_mac(priv
, dev
->dev_addr
);
178 fe_hw_set_macaddr(priv
, p
);
184 static inline int fe_max_frag_size(int mtu
)
186 /* make sure buf_size will be at least MAX_RX_LENGTH */
187 if (mtu
+ FE_RX_ETH_HLEN
< MAX_RX_LENGTH
)
188 mtu
= MAX_RX_LENGTH
- FE_RX_ETH_HLEN
;
190 return SKB_DATA_ALIGN(FE_RX_HLEN
+ mtu
) +
191 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
194 static inline int fe_max_buf_size(int frag_size
)
196 int buf_size
= frag_size
- NET_SKB_PAD
- NET_IP_ALIGN
-
197 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
199 BUG_ON(buf_size
< MAX_RX_LENGTH
);
203 static inline void fe_get_rxd(struct fe_rx_dma
*rxd
, struct fe_rx_dma
*dma_rxd
)
205 rxd
->rxd1
= dma_rxd
->rxd1
;
206 rxd
->rxd2
= dma_rxd
->rxd2
;
207 rxd
->rxd3
= dma_rxd
->rxd3
;
208 rxd
->rxd4
= dma_rxd
->rxd4
;
211 static inline void fe_set_txd(struct fe_tx_dma
*txd
, struct fe_tx_dma
*dma_txd
)
213 dma_txd
->txd1
= txd
->txd1
;
214 dma_txd
->txd3
= txd
->txd3
;
215 dma_txd
->txd4
= txd
->txd4
;
216 /* clean dma done flag last */
217 dma_txd
->txd2
= txd
->txd2
;
220 static void fe_clean_rx(struct fe_priv
*priv
)
223 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
226 for (i
= 0; i
< ring
->rx_ring_size
; i
++)
227 if (ring
->rx_data
[i
]) {
228 if (ring
->rx_dma
&& ring
->rx_dma
[i
].rxd1
)
229 dma_unmap_single(&priv
->netdev
->dev
,
230 ring
->rx_dma
[i
].rxd1
,
233 put_page(virt_to_head_page(ring
->rx_data
[i
]));
236 kfree(ring
->rx_data
);
237 ring
->rx_data
= NULL
;
241 dma_free_coherent(&priv
->netdev
->dev
,
242 ring
->rx_ring_size
* sizeof(*ring
->rx_dma
),
249 static int fe_alloc_rx(struct fe_priv
*priv
)
251 struct net_device
*netdev
= priv
->netdev
;
252 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
255 ring
->rx_data
= kcalloc(ring
->rx_ring_size
, sizeof(*ring
->rx_data
),
260 for (i
= 0; i
< ring
->rx_ring_size
; i
++) {
261 ring
->rx_data
[i
] = netdev_alloc_frag(ring
->frag_size
);
262 if (!ring
->rx_data
[i
])
266 ring
->rx_dma
= dma_alloc_coherent(&netdev
->dev
,
267 ring
->rx_ring_size
* sizeof(*ring
->rx_dma
),
269 GFP_ATOMIC
| __GFP_ZERO
);
273 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
277 for (i
= 0; i
< ring
->rx_ring_size
; i
++) {
278 dma_addr_t dma_addr
= dma_map_single(&netdev
->dev
,
279 ring
->rx_data
[i
] + NET_SKB_PAD
+ pad
,
282 if (unlikely(dma_mapping_error(&netdev
->dev
, dma_addr
)))
284 ring
->rx_dma
[i
].rxd1
= (unsigned int)dma_addr
;
286 if (priv
->flags
& FE_FLAG_RX_SG_DMA
)
287 ring
->rx_dma
[i
].rxd2
= RX_DMA_PLEN0(ring
->rx_buf_size
);
289 ring
->rx_dma
[i
].rxd2
= RX_DMA_LSO
;
291 ring
->rx_calc_idx
= ring
->rx_ring_size
- 1;
292 /* make sure that all changes to the dma ring are flushed before we
297 fe_reg_w32(ring
->rx_phys
, FE_REG_RX_BASE_PTR0
);
298 fe_reg_w32(ring
->rx_ring_size
, FE_REG_RX_MAX_CNT0
);
299 fe_reg_w32(ring
->rx_calc_idx
, FE_REG_RX_CALC_IDX0
);
300 fe_reg_w32(FE_PST_DRX_IDX0
, FE_REG_PDMA_RST_CFG
);
308 static void fe_txd_unmap(struct device
*dev
, struct fe_tx_buf
*tx_buf
)
310 if (dma_unmap_len(tx_buf
, dma_len0
))
312 dma_unmap_addr(tx_buf
, dma_addr0
),
313 dma_unmap_len(tx_buf
, dma_len0
),
316 if (dma_unmap_len(tx_buf
, dma_len1
))
318 dma_unmap_addr(tx_buf
, dma_addr1
),
319 dma_unmap_len(tx_buf
, dma_len1
),
322 dma_unmap_len_set(tx_buf
, dma_addr0
, 0);
323 dma_unmap_len_set(tx_buf
, dma_addr1
, 0);
324 if (tx_buf
->skb
&& (tx_buf
->skb
!= (struct sk_buff
*)DMA_DUMMY_DESC
))
325 dev_kfree_skb_any(tx_buf
->skb
);
329 static void fe_clean_tx(struct fe_priv
*priv
)
332 struct device
*dev
= &priv
->netdev
->dev
;
333 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
336 for (i
= 0; i
< ring
->tx_ring_size
; i
++)
337 fe_txd_unmap(dev
, &ring
->tx_buf
[i
]);
343 dma_free_coherent(dev
,
344 ring
->tx_ring_size
* sizeof(*ring
->tx_dma
),
350 netdev_reset_queue(priv
->netdev
);
353 static int fe_alloc_tx(struct fe_priv
*priv
)
356 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
358 ring
->tx_free_idx
= 0;
359 ring
->tx_next_idx
= 0;
360 ring
->tx_thresh
= max((unsigned long)ring
->tx_ring_size
>> 2,
363 ring
->tx_buf
= kcalloc(ring
->tx_ring_size
, sizeof(*ring
->tx_buf
),
368 ring
->tx_dma
= dma_alloc_coherent(&priv
->netdev
->dev
,
369 ring
->tx_ring_size
* sizeof(*ring
->tx_dma
),
371 GFP_ATOMIC
| __GFP_ZERO
);
375 for (i
= 0; i
< ring
->tx_ring_size
; i
++) {
376 if (priv
->soc
->tx_dma
)
377 priv
->soc
->tx_dma(&ring
->tx_dma
[i
]);
378 ring
->tx_dma
[i
].txd2
= TX_DMA_DESP2_DEF
;
380 /* make sure that all changes to the dma ring are flushed before we
385 fe_reg_w32(ring
->tx_phys
, FE_REG_TX_BASE_PTR0
);
386 fe_reg_w32(ring
->tx_ring_size
, FE_REG_TX_MAX_CNT0
);
387 fe_reg_w32(0, FE_REG_TX_CTX_IDX0
);
388 fe_reg_w32(FE_PST_DTX_IDX0
, FE_REG_PDMA_RST_CFG
);
396 static int fe_init_dma(struct fe_priv
*priv
)
400 err
= fe_alloc_tx(priv
);
404 err
= fe_alloc_rx(priv
);
411 static void fe_free_dma(struct fe_priv
*priv
)
417 void fe_stats_update(struct fe_priv
*priv
)
419 struct fe_hw_stats
*hwstats
= priv
->hw_stats
;
420 unsigned int base
= fe_reg_table
[FE_REG_FE_COUNTER_BASE
];
423 u64_stats_update_begin(&hwstats
->syncp
);
425 if (IS_ENABLED(CONFIG_SOC_MT7621
)) {
426 hwstats
->rx_bytes
+= fe_r32(base
);
427 stats
= fe_r32(base
+ 0x04);
429 hwstats
->rx_bytes
+= (stats
<< 32);
430 hwstats
->rx_packets
+= fe_r32(base
+ 0x08);
431 hwstats
->rx_overflow
+= fe_r32(base
+ 0x10);
432 hwstats
->rx_fcs_errors
+= fe_r32(base
+ 0x14);
433 hwstats
->rx_short_errors
+= fe_r32(base
+ 0x18);
434 hwstats
->rx_long_errors
+= fe_r32(base
+ 0x1c);
435 hwstats
->rx_checksum_errors
+= fe_r32(base
+ 0x20);
436 hwstats
->rx_flow_control_packets
+= fe_r32(base
+ 0x24);
437 hwstats
->tx_skip
+= fe_r32(base
+ 0x28);
438 hwstats
->tx_collisions
+= fe_r32(base
+ 0x2c);
439 hwstats
->tx_bytes
+= fe_r32(base
+ 0x30);
440 stats
= fe_r32(base
+ 0x34);
442 hwstats
->tx_bytes
+= (stats
<< 32);
443 hwstats
->tx_packets
+= fe_r32(base
+ 0x38);
445 hwstats
->tx_bytes
+= fe_r32(base
);
446 hwstats
->tx_packets
+= fe_r32(base
+ 0x04);
447 hwstats
->tx_skip
+= fe_r32(base
+ 0x08);
448 hwstats
->tx_collisions
+= fe_r32(base
+ 0x0c);
449 hwstats
->rx_bytes
+= fe_r32(base
+ 0x20);
450 hwstats
->rx_packets
+= fe_r32(base
+ 0x24);
451 hwstats
->rx_overflow
+= fe_r32(base
+ 0x28);
452 hwstats
->rx_fcs_errors
+= fe_r32(base
+ 0x2c);
453 hwstats
->rx_short_errors
+= fe_r32(base
+ 0x30);
454 hwstats
->rx_long_errors
+= fe_r32(base
+ 0x34);
455 hwstats
->rx_checksum_errors
+= fe_r32(base
+ 0x38);
456 hwstats
->rx_flow_control_packets
+= fe_r32(base
+ 0x3c);
459 u64_stats_update_end(&hwstats
->syncp
);
462 static void fe_get_stats64(struct net_device
*dev
,
463 struct rtnl_link_stats64
*storage
)
465 struct fe_priv
*priv
= netdev_priv(dev
);
466 struct fe_hw_stats
*hwstats
= priv
->hw_stats
;
467 unsigned int base
= fe_reg_table
[FE_REG_FE_COUNTER_BASE
];
471 netdev_stats_to_stats64(storage
, &dev
->stats
);
475 if (netif_running(dev
) && netif_device_present(dev
)) {
476 if (spin_trylock_bh(&hwstats
->stats_lock
)) {
477 fe_stats_update(priv
);
478 spin_unlock_bh(&hwstats
->stats_lock
);
483 start
= u64_stats_fetch_begin_irq(&hwstats
->syncp
);
484 storage
->rx_packets
= hwstats
->rx_packets
;
485 storage
->tx_packets
= hwstats
->tx_packets
;
486 storage
->rx_bytes
= hwstats
->rx_bytes
;
487 storage
->tx_bytes
= hwstats
->tx_bytes
;
488 storage
->collisions
= hwstats
->tx_collisions
;
489 storage
->rx_length_errors
= hwstats
->rx_short_errors
+
490 hwstats
->rx_long_errors
;
491 storage
->rx_over_errors
= hwstats
->rx_overflow
;
492 storage
->rx_crc_errors
= hwstats
->rx_fcs_errors
;
493 storage
->rx_errors
= hwstats
->rx_checksum_errors
;
494 storage
->tx_aborted_errors
= hwstats
->tx_skip
;
495 } while (u64_stats_fetch_retry_irq(&hwstats
->syncp
, start
));
497 storage
->tx_errors
= priv
->netdev
->stats
.tx_errors
;
498 storage
->rx_dropped
= priv
->netdev
->stats
.rx_dropped
;
499 storage
->tx_dropped
= priv
->netdev
->stats
.tx_dropped
;
502 static int fe_vlan_rx_add_vid(struct net_device
*dev
,
503 __be16 proto
, u16 vid
)
505 struct fe_priv
*priv
= netdev_priv(dev
);
506 u32 idx
= (vid
& 0xf);
509 if (!((fe_reg_table
[FE_REG_FE_DMA_VID_BASE
]) &&
510 (dev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)))
513 if (test_bit(idx
, &priv
->vlan_map
)) {
514 netdev_warn(dev
, "disable tx vlan offload\n");
515 dev
->wanted_features
&= ~NETIF_F_HW_VLAN_CTAG_TX
;
516 netdev_update_features(dev
);
518 vlan_cfg
= fe_r32(fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
522 vlan_cfg
|= (vid
<< 16);
524 vlan_cfg
&= 0xffff0000;
527 fe_w32(vlan_cfg
, fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
529 set_bit(idx
, &priv
->vlan_map
);
535 static int fe_vlan_rx_kill_vid(struct net_device
*dev
,
536 __be16 proto
, u16 vid
)
538 struct fe_priv
*priv
= netdev_priv(dev
);
539 u32 idx
= (vid
& 0xf);
541 if (!((fe_reg_table
[FE_REG_FE_DMA_VID_BASE
]) &&
542 (dev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)))
545 clear_bit(idx
, &priv
->vlan_map
);
550 static inline u32
fe_empty_txd(struct fe_tx_ring
*ring
)
553 return (u32
)(ring
->tx_ring_size
-
554 ((ring
->tx_next_idx
- ring
->tx_free_idx
) &
555 (ring
->tx_ring_size
- 1)));
558 static int fe_tx_dma_map_page(struct device
*dev
, struct fe_tx_buf
*tx_buf
,
559 struct fe_tx_dma
*txd
, int idx
,
560 struct page
*page
, size_t offset
, size_t size
)
562 dma_addr_t mapped_addr
;
564 mapped_addr
= dma_map_page(dev
, page
, offset
, size
, DMA_TO_DEVICE
);
565 if (unlikely(dma_mapping_error(dev
, mapped_addr
)))
569 txd
->txd3
= mapped_addr
;
570 txd
->txd2
|= TX_DMA_PLEN1(size
);
571 dma_unmap_addr_set(tx_buf
, dma_addr1
, mapped_addr
);
572 dma_unmap_len_set(tx_buf
, dma_len1
, size
);
574 tx_buf
->skb
= (struct sk_buff
*)DMA_DUMMY_DESC
;
575 txd
->txd1
= mapped_addr
;
576 txd
->txd2
= TX_DMA_PLEN0(size
);
577 dma_unmap_addr_set(tx_buf
, dma_addr0
, mapped_addr
);
578 dma_unmap_len_set(tx_buf
, dma_len0
, size
);
583 static int fe_tx_dma_map_skb(struct device
*dev
, struct fe_tx_buf
*tx_buf
,
584 struct fe_tx_dma
*txd
, int idx
,
587 struct page
*page
= virt_to_page(skb
->data
);
588 size_t offset
= offset_in_page(skb
->data
);
589 size_t size
= skb_headlen(skb
);
591 return fe_tx_dma_map_page(dev
, tx_buf
, txd
, idx
, page
, offset
, size
);
594 static inline struct sk_buff
*
595 fe_next_frag(struct sk_buff
*head
, struct sk_buff
*skb
)
600 if (skb_has_frag_list(skb
))
601 return skb_shinfo(skb
)->frag_list
;
606 static int fe_tx_map_dma(struct sk_buff
*skb
, struct net_device
*dev
,
607 int tx_num
, struct fe_tx_ring
*ring
)
609 struct fe_priv
*priv
= netdev_priv(dev
);
610 struct skb_frag_struct
*frag
;
611 struct fe_tx_dma txd
, *ptxd
;
612 struct fe_tx_buf
*tx_buf
;
613 struct sk_buff
*head
= skb
;
614 unsigned int nr_frags
;
616 int i
, j
, k
, frag_size
, frag_map_size
, offset
;
618 tx_buf
= &ring
->tx_buf
[ring
->tx_next_idx
];
619 memset(tx_buf
, 0, sizeof(*tx_buf
));
620 memset(&txd
, 0, sizeof(txd
));
622 /* init tx descriptor */
623 if (priv
->soc
->tx_dma
)
624 priv
->soc
->tx_dma(&txd
);
626 txd
.txd4
= TX_DMA_DESP4_DEF
;
629 /* TX Checksum offload */
630 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
631 txd
.txd4
|= TX_DMA_CHKSUM
;
633 /* VLAN header offload */
634 if (skb_vlan_tag_present(skb
)) {
635 u16 tag
= skb_vlan_tag_get(skb
);
637 if (IS_ENABLED(CONFIG_SOC_MT7621
))
638 txd
.txd4
|= TX_DMA_INS_VLAN_MT7621
| tag
;
640 txd
.txd4
|= TX_DMA_INS_VLAN
|
641 ((tag
>> VLAN_PRIO_SHIFT
) << 4) |
645 /* TSO: fill MSS info in tcp checksum field */
646 if (skb_is_gso(skb
)) {
647 if (skb_cow_head(skb
, 0)) {
648 netif_warn(priv
, tx_err
, dev
,
649 "GSO expand head fail.\n");
652 if (skb_shinfo(skb
)->gso_type
&
653 (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
654 txd
.txd4
|= TX_DMA_TSO
;
655 tcp_hdr(skb
)->check
= htons(skb_shinfo(skb
)->gso_size
);
660 j
= ring
->tx_next_idx
;
663 if (skb_headlen(skb
)) {
664 if (fe_tx_dma_map_skb(&dev
->dev
, tx_buf
, &txd
, k
++, skb
))
669 nr_frags
= skb_shinfo(skb
)->nr_frags
;
670 for (i
= 0; i
< nr_frags
; i
++) {
673 frag
= &skb_shinfo(skb
)->frags
[i
];
674 frag_size
= skb_frag_size(frag
);
675 offset
= frag
->page_offset
;
676 page
= skb_frag_page(frag
);
678 while (frag_size
> 0) {
679 frag_map_size
= min(frag_size
, TX_DMA_BUF_LEN
);
681 fe_set_txd(&txd
, &ring
->tx_dma
[j
]);
682 memset(&txd
, 0, sizeof(txd
));
684 j
= NEXT_TX_DESP_IDX(j
);
685 tx_buf
= &ring
->tx_buf
[j
];
688 if (fe_tx_dma_map_page(&dev
->dev
, tx_buf
, &txd
, k
++,
689 page
, offset
, frag_map_size
))
692 frag_size
-= frag_map_size
;
693 offset
+= frag_map_size
;
697 skb
= fe_next_frag(head
, skb
);
700 fe_set_txd(&txd
, &ring
->tx_dma
[j
]);
701 memset(&txd
, 0, sizeof(txd
));
703 j
= NEXT_TX_DESP_IDX(j
);
704 tx_buf
= &ring
->tx_buf
[j
];
709 /* set last segment */
711 txd
.txd2
|= TX_DMA_LS0
;
713 txd
.txd2
|= TX_DMA_LS1
;
714 fe_set_txd(&txd
, &ring
->tx_dma
[j
]);
716 /* store skb to cleanup */
719 netdev_sent_queue(dev
, head
->len
);
720 skb_tx_timestamp(head
);
722 ring
->tx_next_idx
= NEXT_TX_DESP_IDX(j
);
723 /* make sure that all changes to the dma ring are flushed before we
727 if (unlikely(fe_empty_txd(ring
) <= ring
->tx_thresh
)) {
728 netif_stop_queue(dev
);
730 if (unlikely(fe_empty_txd(ring
) > ring
->tx_thresh
))
731 netif_wake_queue(dev
);
734 if (netif_xmit_stopped(netdev_get_tx_queue(dev
, 0)) || !head
->xmit_more
)
735 fe_reg_w32(ring
->tx_next_idx
, FE_REG_TX_CTX_IDX0
);
740 j
= ring
->tx_next_idx
;
741 for (i
= 0; i
< tx_num
; i
++) {
742 ptxd
= &ring
->tx_dma
[j
];
743 tx_buf
= &ring
->tx_buf
[j
];
746 fe_txd_unmap(&dev
->dev
, tx_buf
);
748 ptxd
->txd2
= TX_DMA_DESP2_DEF
;
749 j
= NEXT_TX_DESP_IDX(j
);
751 /* make sure that all changes to the dma ring are flushed before we
760 static inline int fe_skb_padto(struct sk_buff
*skb
, struct fe_priv
*priv
)
766 if (unlikely(skb
->len
< VLAN_ETH_ZLEN
)) {
767 if ((priv
->flags
& FE_FLAG_PADDING_64B
) &&
768 !(priv
->flags
& FE_FLAG_PADDING_BUG
))
771 if (skb_vlan_tag_present(skb
))
773 else if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
))
775 else if (!(priv
->flags
& FE_FLAG_PADDING_64B
))
780 if (skb
->len
< len
) {
781 ret
= skb_pad(skb
, len
- skb
->len
);
785 skb_set_tail_pointer(skb
, len
);
792 static inline int fe_cal_txd_req(struct sk_buff
*skb
)
794 struct sk_buff
*head
= skb
;
796 struct skb_frag_struct
*frag
;
800 if (skb_is_gso(skb
)) {
801 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
802 frag
= &skb_shinfo(skb
)->frags
[i
];
803 nfrags
+= DIV_ROUND_UP(frag
->size
, TX_DMA_BUF_LEN
);
806 nfrags
+= skb_shinfo(skb
)->nr_frags
;
809 skb
= fe_next_frag(head
, skb
);
813 return DIV_ROUND_UP(nfrags
, 2);
816 static int fe_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
818 struct fe_priv
*priv
= netdev_priv(dev
);
819 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
820 struct net_device_stats
*stats
= &dev
->stats
;
824 if (fe_skb_padto(skb
, priv
)) {
825 netif_warn(priv
, tx_err
, dev
, "tx padding failed!\n");
829 tx_num
= fe_cal_txd_req(skb
);
830 if (unlikely(fe_empty_txd(ring
) <= tx_num
)) {
831 netif_stop_queue(dev
);
832 netif_err(priv
, tx_queued
, dev
,
833 "Tx Ring full when queue awake!\n");
834 return NETDEV_TX_BUSY
;
837 if (fe_tx_map_dma(skb
, dev
, tx_num
, ring
) < 0) {
841 stats
->tx_bytes
+= len
;
847 static int fe_poll_rx(struct napi_struct
*napi
, int budget
,
848 struct fe_priv
*priv
, u32 rx_intr
)
850 struct net_device
*netdev
= priv
->netdev
;
851 struct net_device_stats
*stats
= &netdev
->stats
;
852 struct fe_soc_data
*soc
= priv
->soc
;
853 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
854 int idx
= ring
->rx_calc_idx
;
858 struct fe_rx_dma
*rxd
, trxd
;
861 if (netdev
->features
& NETIF_F_RXCSUM
)
862 checksum_bit
= soc
->checksum_bit
;
866 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
871 while (done
< budget
) {
875 idx
= NEXT_RX_DESP_IDX(idx
);
876 rxd
= &ring
->rx_dma
[idx
];
877 data
= ring
->rx_data
[idx
];
879 fe_get_rxd(&trxd
, rxd
);
880 if (!(trxd
.rxd2
& RX_DMA_DONE
))
883 /* alloc new buffer */
884 new_data
= netdev_alloc_frag(ring
->frag_size
);
885 if (unlikely(!new_data
)) {
889 dma_addr
= dma_map_single(&netdev
->dev
,
890 new_data
+ NET_SKB_PAD
+ pad
,
893 if (unlikely(dma_mapping_error(&netdev
->dev
, dma_addr
))) {
894 put_page(virt_to_head_page(new_data
));
899 skb
= build_skb(data
, ring
->frag_size
);
900 if (unlikely(!skb
)) {
901 put_page(virt_to_head_page(new_data
));
904 skb_reserve(skb
, NET_SKB_PAD
+ NET_IP_ALIGN
);
906 dma_unmap_single(&netdev
->dev
, trxd
.rxd1
,
907 ring
->rx_buf_size
, DMA_FROM_DEVICE
);
908 pktlen
= RX_DMA_GET_PLEN0(trxd
.rxd2
);
910 skb_put(skb
, pktlen
);
911 if (trxd
.rxd4
& checksum_bit
)
912 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
914 skb_checksum_none_assert(skb
);
915 skb
->protocol
= eth_type_trans(skb
, netdev
);
917 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
918 if (mtk_offload_check_rx(priv
, skb
, trxd
.rxd4
) == 0) {
921 stats
->rx_bytes
+= pktlen
;
923 napi_gro_receive(napi
, skb
);
924 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
929 ring
->rx_data
[idx
] = new_data
;
930 rxd
->rxd1
= (unsigned int)dma_addr
;
933 if (priv
->flags
& FE_FLAG_RX_SG_DMA
)
934 rxd
->rxd2
= RX_DMA_PLEN0(ring
->rx_buf_size
);
936 rxd
->rxd2
= RX_DMA_LSO
;
938 ring
->rx_calc_idx
= idx
;
939 /* make sure that all changes to the dma ring are flushed before
943 fe_reg_w32(ring
->rx_calc_idx
, FE_REG_RX_CALC_IDX0
);
948 fe_reg_w32(rx_intr
, FE_REG_FE_INT_STATUS
);
953 static int fe_poll_tx(struct fe_priv
*priv
, int budget
, u32 tx_intr
,
956 struct net_device
*netdev
= priv
->netdev
;
957 struct device
*dev
= &netdev
->dev
;
958 unsigned int bytes_compl
= 0;
960 struct fe_tx_buf
*tx_buf
;
963 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
965 idx
= ring
->tx_free_idx
;
966 hwidx
= fe_reg_r32(FE_REG_TX_DTX_IDX0
);
968 while ((idx
!= hwidx
) && budget
) {
969 tx_buf
= &ring
->tx_buf
[idx
];
975 if (skb
!= (struct sk_buff
*)DMA_DUMMY_DESC
) {
976 bytes_compl
+= skb
->len
;
980 fe_txd_unmap(dev
, tx_buf
);
981 idx
= NEXT_TX_DESP_IDX(idx
);
983 ring
->tx_free_idx
= idx
;
986 /* read hw index again make sure no new tx packet */
987 hwidx
= fe_reg_r32(FE_REG_TX_DTX_IDX0
);
989 fe_reg_w32(tx_intr
, FE_REG_FE_INT_STATUS
);
997 netdev_completed_queue(netdev
, done
, bytes_compl
);
999 if (unlikely(netif_queue_stopped(netdev
) &&
1000 (fe_empty_txd(ring
) > ring
->tx_thresh
)))
1001 netif_wake_queue(netdev
);
1007 static int fe_poll(struct napi_struct
*napi
, int budget
)
1009 struct fe_priv
*priv
= container_of(napi
, struct fe_priv
, rx_napi
);
1010 struct fe_hw_stats
*hwstat
= priv
->hw_stats
;
1011 int tx_done
, rx_done
, tx_again
;
1012 u32 status
, fe_status
, status_reg
, mask
;
1013 u32 tx_intr
, rx_intr
, status_intr
;
1015 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1017 tx_intr
= priv
->soc
->tx_int
;
1018 rx_intr
= priv
->soc
->rx_int
;
1019 status_intr
= priv
->soc
->status_int
;
1024 if (fe_reg_table
[FE_REG_FE_INT_STATUS2
]) {
1025 fe_status
= fe_reg_r32(FE_REG_FE_INT_STATUS2
);
1026 status_reg
= FE_REG_FE_INT_STATUS2
;
1028 status_reg
= FE_REG_FE_INT_STATUS
;
1031 if (status
& tx_intr
)
1032 tx_done
= fe_poll_tx(priv
, budget
, tx_intr
, &tx_again
);
1034 if (status
& rx_intr
)
1035 rx_done
= fe_poll_rx(napi
, budget
, priv
, rx_intr
);
1037 if (unlikely(fe_status
& status_intr
)) {
1038 if (hwstat
&& spin_trylock(&hwstat
->stats_lock
)) {
1039 fe_stats_update(priv
);
1040 spin_unlock(&hwstat
->stats_lock
);
1042 fe_reg_w32(status_intr
, status_reg
);
1045 if (unlikely(netif_msg_intr(priv
))) {
1046 mask
= fe_reg_r32(FE_REG_FE_INT_ENABLE
);
1047 netdev_info(priv
->netdev
,
1048 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1049 tx_done
, rx_done
, status
, mask
);
1052 if (!tx_again
&& (rx_done
< budget
)) {
1053 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1054 if (status
& (tx_intr
| rx_intr
)) {
1055 /* let napi poll again */
1060 napi_complete_done(napi
, rx_done
);
1061 fe_int_enable(tx_intr
| rx_intr
);
1070 static void fe_tx_timeout(struct net_device
*dev
)
1072 struct fe_priv
*priv
= netdev_priv(dev
);
1073 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
1075 priv
->netdev
->stats
.tx_errors
++;
1076 netif_err(priv
, tx_err
, dev
,
1077 "transmit timed out\n");
1078 netif_info(priv
, drv
, dev
, "dma_cfg:%08x\n",
1079 fe_reg_r32(FE_REG_PDMA_GLO_CFG
));
1080 netif_info(priv
, drv
, dev
, "tx_ring=%d, "
1081 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1082 0, fe_reg_r32(FE_REG_TX_BASE_PTR0
),
1083 fe_reg_r32(FE_REG_TX_MAX_CNT0
),
1084 fe_reg_r32(FE_REG_TX_CTX_IDX0
),
1085 fe_reg_r32(FE_REG_TX_DTX_IDX0
),
1088 netif_info(priv
, drv
, dev
,
1089 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1090 0, fe_reg_r32(FE_REG_RX_BASE_PTR0
),
1091 fe_reg_r32(FE_REG_RX_MAX_CNT0
),
1092 fe_reg_r32(FE_REG_RX_CALC_IDX0
),
1093 fe_reg_r32(FE_REG_RX_DRX_IDX0
));
1095 if (!test_and_set_bit(FE_FLAG_RESET_PENDING
, priv
->pending_flags
))
1096 schedule_work(&priv
->pending_work
);
1099 static irqreturn_t
fe_handle_irq(int irq
, void *dev
)
1101 struct fe_priv
*priv
= netdev_priv(dev
);
1102 u32 status
, int_mask
;
1104 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1106 if (unlikely(!status
))
1109 int_mask
= (priv
->soc
->rx_int
| priv
->soc
->tx_int
);
1110 if (likely(status
& int_mask
)) {
1111 if (likely(napi_schedule_prep(&priv
->rx_napi
))) {
1112 fe_int_disable(int_mask
);
1113 __napi_schedule(&priv
->rx_napi
);
1116 fe_reg_w32(status
, FE_REG_FE_INT_STATUS
);
1122 #ifdef CONFIG_NET_POLL_CONTROLLER
1123 static void fe_poll_controller(struct net_device
*dev
)
1125 struct fe_priv
*priv
= netdev_priv(dev
);
1126 u32 int_mask
= priv
->soc
->tx_int
| priv
->soc
->rx_int
;
1128 fe_int_disable(int_mask
);
1129 fe_handle_irq(dev
->irq
, dev
);
1130 fe_int_enable(int_mask
);
1134 int fe_set_clock_cycle(struct fe_priv
*priv
)
1136 unsigned long sysclk
= priv
->sysclk
;
1138 sysclk
/= FE_US_CYC_CNT_DIVISOR
;
1139 sysclk
<<= FE_US_CYC_CNT_SHIFT
;
1141 fe_w32((fe_r32(FE_FE_GLO_CFG
) &
1142 ~(FE_US_CYC_CNT_MASK
<< FE_US_CYC_CNT_SHIFT
)) |
1148 void fe_fwd_config(struct fe_priv
*priv
)
1152 fwd_cfg
= fe_r32(FE_GDMA1_FWD_CFG
);
1154 /* disable jumbo frame */
1155 if (priv
->flags
& FE_FLAG_JUMBO_FRAME
)
1156 fwd_cfg
&= ~FE_GDM1_JMB_EN
;
1158 /* set unicast/multicast/broadcast frame to cpu */
1161 fe_w32(fwd_cfg
, FE_GDMA1_FWD_CFG
);
1164 static void fe_rxcsum_config(bool enable
)
1167 fe_w32(fe_r32(FE_GDMA1_FWD_CFG
) | (FE_GDM1_ICS_EN
|
1168 FE_GDM1_TCS_EN
| FE_GDM1_UCS_EN
),
1171 fe_w32(fe_r32(FE_GDMA1_FWD_CFG
) & ~(FE_GDM1_ICS_EN
|
1172 FE_GDM1_TCS_EN
| FE_GDM1_UCS_EN
),
1176 static void fe_txcsum_config(bool enable
)
1179 fe_w32(fe_r32(FE_CDMA_CSG_CFG
) | (FE_ICS_GEN_EN
|
1180 FE_TCS_GEN_EN
| FE_UCS_GEN_EN
),
1183 fe_w32(fe_r32(FE_CDMA_CSG_CFG
) & ~(FE_ICS_GEN_EN
|
1184 FE_TCS_GEN_EN
| FE_UCS_GEN_EN
),
1188 void fe_csum_config(struct fe_priv
*priv
)
1190 struct net_device
*dev
= priv_netdev(priv
);
1192 fe_txcsum_config((dev
->features
& NETIF_F_IP_CSUM
));
1193 fe_rxcsum_config((dev
->features
& NETIF_F_RXCSUM
));
1196 static int fe_hw_init(struct net_device
*dev
)
1198 struct fe_priv
*priv
= netdev_priv(dev
);
1201 err
= devm_request_irq(priv
->dev
, dev
->irq
, fe_handle_irq
, 0,
1202 dev_name(priv
->dev
), dev
);
1206 if (priv
->soc
->set_mac
)
1207 priv
->soc
->set_mac(priv
, dev
->dev_addr
);
1209 fe_hw_set_macaddr(priv
, dev
->dev_addr
);
1211 /* disable delay interrupt */
1212 fe_reg_w32(0, FE_REG_DLY_INT_CFG
);
1214 fe_int_disable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1216 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1217 if (fe_reg_table
[FE_REG_FE_DMA_VID_BASE
])
1218 for (i
= 0; i
< 16; i
+= 2)
1219 fe_w32(((i
+ 1) << 16) + i
,
1220 fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
1223 if (priv
->soc
->fwd_config(priv
))
1224 netdev_err(dev
, "unable to get clock\n");
1226 if (fe_reg_table
[FE_REG_FE_RST_GL
]) {
1227 fe_reg_w32(1, FE_REG_FE_RST_GL
);
1228 fe_reg_w32(0, FE_REG_FE_RST_GL
);
1234 static int fe_open(struct net_device
*dev
)
1236 struct fe_priv
*priv
= netdev_priv(dev
);
1237 unsigned long flags
;
1241 err
= fe_init_dma(priv
);
1247 spin_lock_irqsave(&priv
->page_lock
, flags
);
1249 val
= FE_TX_WB_DDONE
| FE_RX_DMA_EN
| FE_TX_DMA_EN
;
1250 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
1251 val
|= FE_RX_2B_OFFSET
;
1252 val
|= priv
->soc
->pdma_glo_cfg
;
1253 fe_reg_w32(val
, FE_REG_PDMA_GLO_CFG
);
1255 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
1258 priv
->phy
->start(priv
);
1260 if (priv
->soc
->has_carrier
&& priv
->soc
->has_carrier(priv
))
1261 netif_carrier_on(dev
);
1263 napi_enable(&priv
->rx_napi
);
1264 fe_int_enable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1265 netif_start_queue(dev
);
1266 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1267 mtk_ppe_probe(priv
);
1273 static int fe_stop(struct net_device
*dev
)
1275 struct fe_priv
*priv
= netdev_priv(dev
);
1276 unsigned long flags
;
1279 netif_tx_disable(dev
);
1280 fe_int_disable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1281 napi_disable(&priv
->rx_napi
);
1284 priv
->phy
->stop(priv
);
1286 spin_lock_irqsave(&priv
->page_lock
, flags
);
1288 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG
) &
1289 ~(FE_TX_WB_DDONE
| FE_RX_DMA_EN
| FE_TX_DMA_EN
),
1290 FE_REG_PDMA_GLO_CFG
);
1291 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
1294 for (i
= 0; i
< 10; i
++) {
1295 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG
) &
1296 (FE_TX_DMA_BUSY
| FE_RX_DMA_BUSY
)) {
1305 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1306 mtk_ppe_remove(priv
);
1312 static int __init
fe_init(struct net_device
*dev
)
1314 struct fe_priv
*priv
= netdev_priv(dev
);
1315 struct device_node
*port
;
1316 const char *mac_addr
;
1319 priv
->soc
->reset_fe();
1321 if (priv
->soc
->switch_init
)
1322 if (priv
->soc
->switch_init(priv
)) {
1323 netdev_err(dev
, "failed to initialize switch core\n");
1327 mac_addr
= of_get_mac_address(priv
->dev
->of_node
);
1329 ether_addr_copy(dev
->dev_addr
, mac_addr
);
1331 /* If the mac address is invalid, use random mac address */
1332 if (!is_valid_ether_addr(dev
->dev_addr
)) {
1333 random_ether_addr(dev
->dev_addr
);
1334 dev_err(priv
->dev
, "generated random MAC address %pM\n",
1338 err
= fe_mdio_init(priv
);
1342 if (priv
->soc
->port_init
)
1343 for_each_child_of_node(priv
->dev
->of_node
, port
)
1344 if (of_device_is_compatible(port
, "mediatek,eth-port") &&
1345 of_device_is_available(port
))
1346 priv
->soc
->port_init(priv
, port
);
1349 err
= priv
->phy
->connect(priv
);
1351 goto err_phy_disconnect
;
1354 err
= fe_hw_init(dev
);
1356 goto err_phy_disconnect
;
1358 if ((priv
->flags
& FE_FLAG_HAS_SWITCH
) && priv
->soc
->switch_config
)
1359 priv
->soc
->switch_config(priv
);
1365 priv
->phy
->disconnect(priv
);
1366 fe_mdio_cleanup(priv
);
1371 static void fe_uninit(struct net_device
*dev
)
1373 struct fe_priv
*priv
= netdev_priv(dev
);
1376 priv
->phy
->disconnect(priv
);
1377 fe_mdio_cleanup(priv
);
1379 fe_reg_w32(0, FE_REG_FE_INT_ENABLE
);
1380 free_irq(dev
->irq
, dev
);
1383 static int fe_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1385 struct fe_priv
*priv
= netdev_priv(dev
);
1392 return phy_ethtool_ioctl(priv
->phy_dev
,
1393 (void *) ifr
->ifr_data
);
1397 return phy_mii_ioctl(priv
->phy_dev
, ifr
, cmd
);
1405 static int fe_change_mtu(struct net_device
*dev
, int new_mtu
)
1407 struct fe_priv
*priv
= netdev_priv(dev
);
1408 int frag_size
, old_mtu
;
1414 if (!(priv
->flags
& FE_FLAG_JUMBO_FRAME
))
1417 /* return early if the buffer sizes will not change */
1418 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
1420 if (old_mtu
> ETH_DATA_LEN
&& new_mtu
> ETH_DATA_LEN
)
1423 if (new_mtu
<= ETH_DATA_LEN
)
1424 priv
->rx_ring
.frag_size
= fe_max_frag_size(ETH_DATA_LEN
);
1426 priv
->rx_ring
.frag_size
= PAGE_SIZE
;
1427 priv
->rx_ring
.rx_buf_size
= fe_max_buf_size(priv
->rx_ring
.frag_size
);
1429 if (!netif_running(dev
))
1433 if (!IS_ENABLED(CONFIG_SOC_MT7621
)) {
1434 fwd_cfg
= fe_r32(FE_GDMA1_FWD_CFG
);
1435 if (new_mtu
<= ETH_DATA_LEN
) {
1436 fwd_cfg
&= ~FE_GDM1_JMB_EN
;
1438 frag_size
= fe_max_frag_size(new_mtu
);
1439 fwd_cfg
&= ~(FE_GDM1_JMB_LEN_MASK
<< FE_GDM1_JMB_LEN_SHIFT
);
1440 fwd_cfg
|= (DIV_ROUND_UP(frag_size
, 1024) <<
1441 FE_GDM1_JMB_LEN_SHIFT
) | FE_GDM1_JMB_EN
;
1443 fe_w32(fwd_cfg
, FE_GDMA1_FWD_CFG
);
1446 return fe_open(dev
);
1449 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1451 fe_flow_offload(enum flow_offload_type type
, struct flow_offload
*flow
,
1452 struct flow_offload_hw_path
*src
,
1453 struct flow_offload_hw_path
*dest
)
1455 struct fe_priv
*priv
;
1457 if (src
->dev
!= dest
->dev
)
1460 priv
= netdev_priv(src
->dev
);
1462 return mtk_flow_offload(priv
, type
, flow
, src
, dest
);
1466 static const struct net_device_ops fe_netdev_ops
= {
1467 .ndo_init
= fe_init
,
1468 .ndo_uninit
= fe_uninit
,
1469 .ndo_open
= fe_open
,
1470 .ndo_stop
= fe_stop
,
1471 .ndo_start_xmit
= fe_start_xmit
,
1472 .ndo_set_mac_address
= fe_set_mac_address
,
1473 .ndo_validate_addr
= eth_validate_addr
,
1474 .ndo_do_ioctl
= fe_do_ioctl
,
1475 .ndo_change_mtu
= fe_change_mtu
,
1476 .ndo_tx_timeout
= fe_tx_timeout
,
1477 .ndo_get_stats64
= fe_get_stats64
,
1478 .ndo_vlan_rx_add_vid
= fe_vlan_rx_add_vid
,
1479 .ndo_vlan_rx_kill_vid
= fe_vlan_rx_kill_vid
,
1480 #ifdef CONFIG_NET_POLL_CONTROLLER
1481 .ndo_poll_controller
= fe_poll_controller
,
1483 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1484 .ndo_flow_offload
= fe_flow_offload
,
1488 static void fe_reset_pending(struct fe_priv
*priv
)
1490 struct net_device
*dev
= priv
->netdev
;
1498 netif_alert(priv
, ifup
, dev
,
1499 "Driver up/down cycle failed, closing device.\n");
1505 static const struct fe_work_t fe_work
[] = {
1506 {FE_FLAG_RESET_PENDING
, fe_reset_pending
},
1509 static void fe_pending_work(struct work_struct
*work
)
1511 struct fe_priv
*priv
= container_of(work
, struct fe_priv
, pending_work
);
1515 for (i
= 0; i
< ARRAY_SIZE(fe_work
); i
++) {
1516 pending
= test_and_clear_bit(fe_work
[i
].bitnr
,
1517 priv
->pending_flags
);
1519 fe_work
[i
].action(priv
);
1523 static int fe_probe(struct platform_device
*pdev
)
1525 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1526 const struct of_device_id
*match
;
1527 struct fe_soc_data
*soc
;
1528 struct net_device
*netdev
;
1529 struct fe_priv
*priv
;
1531 int err
, napi_weight
;
1533 device_reset(&pdev
->dev
);
1535 match
= of_match_device(of_fe_match
, &pdev
->dev
);
1536 soc
= (struct fe_soc_data
*)match
->data
;
1539 fe_reg_table
= soc
->reg_table
;
1541 soc
->reg_table
= fe_reg_table
;
1543 fe_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1544 if (IS_ERR(fe_base
)) {
1545 err
= -EADDRNOTAVAIL
;
1549 netdev
= alloc_etherdev(sizeof(*priv
));
1551 dev_err(&pdev
->dev
, "alloc_etherdev failed\n");
1556 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
1557 netdev
->netdev_ops
= &fe_netdev_ops
;
1558 netdev
->base_addr
= (unsigned long)fe_base
;
1560 netdev
->irq
= platform_get_irq(pdev
, 0);
1561 if (netdev
->irq
< 0) {
1562 dev_err(&pdev
->dev
, "no IRQ resource found\n");
1568 soc
->init_data(soc
, netdev
);
1569 netdev
->vlan_features
= netdev
->hw_features
& ~NETIF_F_HW_VLAN_CTAG_TX
;
1570 netdev
->features
|= netdev
->hw_features
;
1572 if (IS_ENABLED(CONFIG_SOC_MT7621
))
1573 netdev
->max_mtu
= 2048;
1575 /* fake rx vlan filter func. to support tx vlan offload func */
1576 if (fe_reg_table
[FE_REG_FE_DMA_VID_BASE
])
1577 netdev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
1579 priv
= netdev_priv(netdev
);
1580 spin_lock_init(&priv
->page_lock
);
1581 if (fe_reg_table
[FE_REG_FE_COUNTER_BASE
]) {
1582 priv
->hw_stats
= kzalloc(sizeof(*priv
->hw_stats
), GFP_KERNEL
);
1583 if (!priv
->hw_stats
) {
1587 spin_lock_init(&priv
->hw_stats
->stats_lock
);
1590 sysclk
= devm_clk_get(&pdev
->dev
, NULL
);
1591 if (!IS_ERR(sysclk
)) {
1592 priv
->sysclk
= clk_get_rate(sysclk
);
1593 } else if ((priv
->flags
& FE_FLAG_CALIBRATE_CLK
)) {
1594 dev_err(&pdev
->dev
, "this soc needs a clk for calibration\n");
1599 priv
->switch_np
= of_parse_phandle(pdev
->dev
.of_node
, "mediatek,switch", 0);
1600 if ((priv
->flags
& FE_FLAG_HAS_SWITCH
) && !priv
->switch_np
) {
1601 dev_err(&pdev
->dev
, "failed to read switch phandle\n");
1606 priv
->netdev
= netdev
;
1607 priv
->dev
= &pdev
->dev
;
1609 priv
->msg_enable
= netif_msg_init(fe_msg_level
, FE_DEFAULT_MSG_ENABLE
);
1610 priv
->rx_ring
.frag_size
= fe_max_frag_size(ETH_DATA_LEN
);
1611 priv
->rx_ring
.rx_buf_size
= fe_max_buf_size(priv
->rx_ring
.frag_size
);
1612 priv
->tx_ring
.tx_ring_size
= NUM_DMA_DESC
;
1613 priv
->rx_ring
.rx_ring_size
= NUM_DMA_DESC
;
1614 INIT_WORK(&priv
->pending_work
, fe_pending_work
);
1615 u64_stats_init(&priv
->hw_stats
->syncp
);
1618 if (priv
->flags
& FE_FLAG_NAPI_WEIGHT
) {
1620 priv
->tx_ring
.tx_ring_size
*= 4;
1621 priv
->rx_ring
.rx_ring_size
*= 4;
1623 netif_napi_add(netdev
, &priv
->rx_napi
, fe_poll
, napi_weight
);
1624 fe_set_ethtool_ops(netdev
);
1626 err
= register_netdev(netdev
);
1628 dev_err(&pdev
->dev
, "error bringing up device\n");
1632 platform_set_drvdata(pdev
, netdev
);
1634 netif_info(priv
, probe
, netdev
, "mediatek frame engine at 0x%08lx, irq %d\n",
1635 netdev
->base_addr
, netdev
->irq
);
1640 free_netdev(netdev
);
1642 devm_iounmap(&pdev
->dev
, fe_base
);
1647 static int fe_remove(struct platform_device
*pdev
)
1649 struct net_device
*dev
= platform_get_drvdata(pdev
);
1650 struct fe_priv
*priv
= netdev_priv(dev
);
1652 netif_napi_del(&priv
->rx_napi
);
1653 kfree(priv
->hw_stats
);
1655 cancel_work_sync(&priv
->pending_work
);
1657 unregister_netdev(dev
);
1659 platform_set_drvdata(pdev
, NULL
);
1664 static struct platform_driver fe_driver
= {
1666 .remove
= fe_remove
,
1668 .name
= "mtk_soc_eth",
1669 .owner
= THIS_MODULE
,
1670 .of_match_table
= of_fe_match
,
1674 module_platform_driver(fe_driver
);
1676 MODULE_LICENSE("GPL");
1677 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1678 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1679 MODULE_VERSION(MTK_FE_DRV_VERSION
);