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[openwrt/staging/lynxis.git] / target / linux / ramips / files-4.14 / drivers / net / ethernet / mtk / mtk_eth_soc.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
31 #include <linux/io.h>
32 #include <linux/bug.h>
33 #include <linux/netfilter.h>
34 #include <net/netfilter/nf_flow_table.h>
35
36 #include <asm/mach-ralink/ralink_regs.h>
37
38 #include "mtk_eth_soc.h"
39 #include "mdio.h"
40 #include "ethtool.h"
41
42 #define MAX_RX_LENGTH 1536
43 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
44 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
45 #define DMA_DUMMY_DESC 0xffffffff
46 #define FE_DEFAULT_MSG_ENABLE \
47 (NETIF_MSG_DRV | \
48 NETIF_MSG_PROBE | \
49 NETIF_MSG_LINK | \
50 NETIF_MSG_TIMER | \
51 NETIF_MSG_IFDOWN | \
52 NETIF_MSG_IFUP | \
53 NETIF_MSG_RX_ERR | \
54 NETIF_MSG_TX_ERR)
55
56 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
57 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
58 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
59 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
60
61 #define SYSC_REG_RSTCTRL 0x34
62
63 static int fe_msg_level = -1;
64 module_param_named(msg_level, fe_msg_level, int, 0);
65 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
66
67 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
68 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
69 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
70 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
71 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
72 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
73 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
74 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
75 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
76 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
77 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
78 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
79 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
80 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
81 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
82 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
83 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
84 };
85
86 static const u16 *fe_reg_table = fe_reg_table_default;
87
88 struct fe_work_t {
89 int bitnr;
90 void (*action)(struct fe_priv *);
91 };
92
93 static void __iomem *fe_base;
94
95 void fe_w32(u32 val, unsigned reg)
96 {
97 __raw_writel(val, fe_base + reg);
98 }
99
100 u32 fe_r32(unsigned reg)
101 {
102 return __raw_readl(fe_base + reg);
103 }
104
105 void fe_reg_w32(u32 val, enum fe_reg reg)
106 {
107 fe_w32(val, fe_reg_table[reg]);
108 }
109
110 u32 fe_reg_r32(enum fe_reg reg)
111 {
112 return fe_r32(fe_reg_table[reg]);
113 }
114
115 void fe_m32(struct fe_priv *eth, u32 clear, u32 set, unsigned reg)
116 {
117 u32 val;
118
119 spin_lock(&eth->page_lock);
120 val = __raw_readl(fe_base + reg);
121 val &= ~clear;
122 val |= set;
123 __raw_writel(val, fe_base + reg);
124 spin_unlock(&eth->page_lock);
125 }
126
127 void fe_reset(u32 reset_bits)
128 {
129 u32 t;
130
131 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
132 t |= reset_bits;
133 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
134 usleep_range(10, 20);
135
136 t &= ~reset_bits;
137 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
138 usleep_range(10, 20);
139 }
140
141 static inline void fe_int_disable(u32 mask)
142 {
143 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
144 FE_REG_FE_INT_ENABLE);
145 /* flush write */
146 fe_reg_r32(FE_REG_FE_INT_ENABLE);
147 }
148
149 static inline void fe_int_enable(u32 mask)
150 {
151 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
152 FE_REG_FE_INT_ENABLE);
153 /* flush write */
154 fe_reg_r32(FE_REG_FE_INT_ENABLE);
155 }
156
157 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
158 {
159 unsigned long flags;
160
161 spin_lock_irqsave(&priv->page_lock, flags);
162 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
163 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
164 FE_GDMA1_MAC_ADRL);
165 spin_unlock_irqrestore(&priv->page_lock, flags);
166 }
167
168 static int fe_set_mac_address(struct net_device *dev, void *p)
169 {
170 int ret = eth_mac_addr(dev, p);
171
172 if (!ret) {
173 struct fe_priv *priv = netdev_priv(dev);
174
175 if (priv->soc->set_mac)
176 priv->soc->set_mac(priv, dev->dev_addr);
177 else
178 fe_hw_set_macaddr(priv, p);
179 }
180
181 return ret;
182 }
183
184 static inline int fe_max_frag_size(int mtu)
185 {
186 /* make sure buf_size will be at least MAX_RX_LENGTH */
187 if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)
188 mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;
189
190 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
191 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
192 }
193
194 static inline int fe_max_buf_size(int frag_size)
195 {
196 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
197 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
198
199 BUG_ON(buf_size < MAX_RX_LENGTH);
200 return buf_size;
201 }
202
203 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
204 {
205 rxd->rxd1 = dma_rxd->rxd1;
206 rxd->rxd2 = dma_rxd->rxd2;
207 rxd->rxd3 = dma_rxd->rxd3;
208 rxd->rxd4 = dma_rxd->rxd4;
209 }
210
211 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
212 {
213 dma_txd->txd1 = txd->txd1;
214 dma_txd->txd3 = txd->txd3;
215 dma_txd->txd4 = txd->txd4;
216 /* clean dma done flag last */
217 dma_txd->txd2 = txd->txd2;
218 }
219
220 static void fe_clean_rx(struct fe_priv *priv)
221 {
222 int i;
223 struct fe_rx_ring *ring = &priv->rx_ring;
224
225 if (ring->rx_data) {
226 for (i = 0; i < ring->rx_ring_size; i++)
227 if (ring->rx_data[i]) {
228 if (ring->rx_dma && ring->rx_dma[i].rxd1)
229 dma_unmap_single(&priv->netdev->dev,
230 ring->rx_dma[i].rxd1,
231 ring->rx_buf_size,
232 DMA_FROM_DEVICE);
233 put_page(virt_to_head_page(ring->rx_data[i]));
234 }
235
236 kfree(ring->rx_data);
237 ring->rx_data = NULL;
238 }
239
240 if (ring->rx_dma) {
241 dma_free_coherent(&priv->netdev->dev,
242 ring->rx_ring_size * sizeof(*ring->rx_dma),
243 ring->rx_dma,
244 ring->rx_phys);
245 ring->rx_dma = NULL;
246 }
247 }
248
249 static int fe_alloc_rx(struct fe_priv *priv)
250 {
251 struct net_device *netdev = priv->netdev;
252 struct fe_rx_ring *ring = &priv->rx_ring;
253 int i, pad;
254
255 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
256 GFP_KERNEL);
257 if (!ring->rx_data)
258 goto no_rx_mem;
259
260 for (i = 0; i < ring->rx_ring_size; i++) {
261 ring->rx_data[i] = netdev_alloc_frag(ring->frag_size);
262 if (!ring->rx_data[i])
263 goto no_rx_mem;
264 }
265
266 ring->rx_dma = dma_alloc_coherent(&netdev->dev,
267 ring->rx_ring_size * sizeof(*ring->rx_dma),
268 &ring->rx_phys,
269 GFP_ATOMIC | __GFP_ZERO);
270 if (!ring->rx_dma)
271 goto no_rx_mem;
272
273 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
274 pad = 0;
275 else
276 pad = NET_IP_ALIGN;
277 for (i = 0; i < ring->rx_ring_size; i++) {
278 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
279 ring->rx_data[i] + NET_SKB_PAD + pad,
280 ring->rx_buf_size,
281 DMA_FROM_DEVICE);
282 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
283 goto no_rx_mem;
284 ring->rx_dma[i].rxd1 = (unsigned int)dma_addr;
285
286 if (priv->flags & FE_FLAG_RX_SG_DMA)
287 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
288 else
289 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
290 }
291 ring->rx_calc_idx = ring->rx_ring_size - 1;
292 /* make sure that all changes to the dma ring are flushed before we
293 * continue
294 */
295 wmb();
296
297 fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
298 fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
299 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
300 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
301
302 return 0;
303
304 no_rx_mem:
305 return -ENOMEM;
306 }
307
308 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
309 {
310 if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) {
311 dma_unmap_single(dev,
312 dma_unmap_addr(tx_buf, dma_addr0),
313 dma_unmap_len(tx_buf, dma_len0),
314 DMA_TO_DEVICE);
315 } else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) {
316 dma_unmap_page(dev,
317 dma_unmap_addr(tx_buf, dma_addr0),
318 dma_unmap_len(tx_buf, dma_len0),
319 DMA_TO_DEVICE);
320 }
321 if (tx_buf->flags & FE_TX_FLAGS_PAGE1)
322 dma_unmap_page(dev,
323 dma_unmap_addr(tx_buf, dma_addr1),
324 dma_unmap_len(tx_buf, dma_len1),
325 DMA_TO_DEVICE);
326
327 tx_buf->flags = 0;
328 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC))
329 dev_kfree_skb_any(tx_buf->skb);
330 tx_buf->skb = NULL;
331 }
332
333 static void fe_clean_tx(struct fe_priv *priv)
334 {
335 int i;
336 struct device *dev = &priv->netdev->dev;
337 struct fe_tx_ring *ring = &priv->tx_ring;
338
339 if (ring->tx_buf) {
340 for (i = 0; i < ring->tx_ring_size; i++)
341 fe_txd_unmap(dev, &ring->tx_buf[i]);
342 kfree(ring->tx_buf);
343 ring->tx_buf = NULL;
344 }
345
346 if (ring->tx_dma) {
347 dma_free_coherent(dev,
348 ring->tx_ring_size * sizeof(*ring->tx_dma),
349 ring->tx_dma,
350 ring->tx_phys);
351 ring->tx_dma = NULL;
352 }
353
354 netdev_reset_queue(priv->netdev);
355 }
356
357 static int fe_alloc_tx(struct fe_priv *priv)
358 {
359 int i;
360 struct fe_tx_ring *ring = &priv->tx_ring;
361
362 ring->tx_free_idx = 0;
363 ring->tx_next_idx = 0;
364 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
365 MAX_SKB_FRAGS);
366
367 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
368 GFP_KERNEL);
369 if (!ring->tx_buf)
370 goto no_tx_mem;
371
372 ring->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
373 ring->tx_ring_size * sizeof(*ring->tx_dma),
374 &ring->tx_phys,
375 GFP_ATOMIC | __GFP_ZERO);
376 if (!ring->tx_dma)
377 goto no_tx_mem;
378
379 for (i = 0; i < ring->tx_ring_size; i++) {
380 if (priv->soc->tx_dma)
381 priv->soc->tx_dma(&ring->tx_dma[i]);
382 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
383 }
384 /* make sure that all changes to the dma ring are flushed before we
385 * continue
386 */
387 wmb();
388
389 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
390 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
391 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
392 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
393
394 return 0;
395
396 no_tx_mem:
397 return -ENOMEM;
398 }
399
400 static int fe_init_dma(struct fe_priv *priv)
401 {
402 int err;
403
404 err = fe_alloc_tx(priv);
405 if (err)
406 return err;
407
408 err = fe_alloc_rx(priv);
409 if (err)
410 return err;
411
412 return 0;
413 }
414
415 static void fe_free_dma(struct fe_priv *priv)
416 {
417 fe_clean_tx(priv);
418 fe_clean_rx(priv);
419 }
420
421 void fe_stats_update(struct fe_priv *priv)
422 {
423 struct fe_hw_stats *hwstats = priv->hw_stats;
424 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
425 u64 stats;
426
427 u64_stats_update_begin(&hwstats->syncp);
428
429 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
430 hwstats->rx_bytes += fe_r32(base);
431 stats = fe_r32(base + 0x04);
432 if (stats)
433 hwstats->rx_bytes += (stats << 32);
434 hwstats->rx_packets += fe_r32(base + 0x08);
435 hwstats->rx_overflow += fe_r32(base + 0x10);
436 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
437 hwstats->rx_short_errors += fe_r32(base + 0x18);
438 hwstats->rx_long_errors += fe_r32(base + 0x1c);
439 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
440 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
441 hwstats->tx_skip += fe_r32(base + 0x28);
442 hwstats->tx_collisions += fe_r32(base + 0x2c);
443 hwstats->tx_bytes += fe_r32(base + 0x30);
444 stats = fe_r32(base + 0x34);
445 if (stats)
446 hwstats->tx_bytes += (stats << 32);
447 hwstats->tx_packets += fe_r32(base + 0x38);
448 } else {
449 hwstats->tx_bytes += fe_r32(base);
450 hwstats->tx_packets += fe_r32(base + 0x04);
451 hwstats->tx_skip += fe_r32(base + 0x08);
452 hwstats->tx_collisions += fe_r32(base + 0x0c);
453 hwstats->rx_bytes += fe_r32(base + 0x20);
454 hwstats->rx_packets += fe_r32(base + 0x24);
455 hwstats->rx_overflow += fe_r32(base + 0x28);
456 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
457 hwstats->rx_short_errors += fe_r32(base + 0x30);
458 hwstats->rx_long_errors += fe_r32(base + 0x34);
459 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
460 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
461 }
462
463 u64_stats_update_end(&hwstats->syncp);
464 }
465
466 static void fe_get_stats64(struct net_device *dev,
467 struct rtnl_link_stats64 *storage)
468 {
469 struct fe_priv *priv = netdev_priv(dev);
470 struct fe_hw_stats *hwstats = priv->hw_stats;
471 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
472 unsigned int start;
473
474 if (!base) {
475 netdev_stats_to_stats64(storage, &dev->stats);
476 return;
477 }
478
479 if (netif_running(dev) && netif_device_present(dev)) {
480 if (spin_trylock(&hwstats->stats_lock)) {
481 fe_stats_update(priv);
482 spin_unlock(&hwstats->stats_lock);
483 }
484 }
485
486 do {
487 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
488 storage->rx_packets = hwstats->rx_packets;
489 storage->tx_packets = hwstats->tx_packets;
490 storage->rx_bytes = hwstats->rx_bytes;
491 storage->tx_bytes = hwstats->tx_bytes;
492 storage->collisions = hwstats->tx_collisions;
493 storage->rx_length_errors = hwstats->rx_short_errors +
494 hwstats->rx_long_errors;
495 storage->rx_over_errors = hwstats->rx_overflow;
496 storage->rx_crc_errors = hwstats->rx_fcs_errors;
497 storage->rx_errors = hwstats->rx_checksum_errors;
498 storage->tx_aborted_errors = hwstats->tx_skip;
499 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
500
501 storage->tx_errors = priv->netdev->stats.tx_errors;
502 storage->rx_dropped = priv->netdev->stats.rx_dropped;
503 storage->tx_dropped = priv->netdev->stats.tx_dropped;
504 }
505
506 static int fe_vlan_rx_add_vid(struct net_device *dev,
507 __be16 proto, u16 vid)
508 {
509 struct fe_priv *priv = netdev_priv(dev);
510 u32 idx = (vid & 0xf);
511 u32 vlan_cfg;
512
513 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
514 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
515 return 0;
516
517 if (test_bit(idx, &priv->vlan_map)) {
518 netdev_warn(dev, "disable tx vlan offload\n");
519 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
520 netdev_update_features(dev);
521 } else {
522 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
523 ((idx >> 1) << 2));
524 if (idx & 0x1) {
525 vlan_cfg &= 0xffff;
526 vlan_cfg |= (vid << 16);
527 } else {
528 vlan_cfg &= 0xffff0000;
529 vlan_cfg |= vid;
530 }
531 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
532 ((idx >> 1) << 2));
533 set_bit(idx, &priv->vlan_map);
534 }
535
536 return 0;
537 }
538
539 static int fe_vlan_rx_kill_vid(struct net_device *dev,
540 __be16 proto, u16 vid)
541 {
542 struct fe_priv *priv = netdev_priv(dev);
543 u32 idx = (vid & 0xf);
544
545 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
546 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
547 return 0;
548
549 clear_bit(idx, &priv->vlan_map);
550
551 return 0;
552 }
553
554 static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
555 {
556 barrier();
557 return (u32)(ring->tx_ring_size -
558 ((ring->tx_next_idx - ring->tx_free_idx) &
559 (ring->tx_ring_size - 1)));
560 }
561
562 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
563 int tx_num, struct fe_tx_ring *ring)
564 {
565 struct fe_priv *priv = netdev_priv(dev);
566 struct skb_frag_struct *frag;
567 struct fe_tx_dma txd, *ptxd;
568 struct fe_tx_buf *tx_buf;
569 dma_addr_t mapped_addr;
570 unsigned int nr_frags;
571 u32 def_txd4;
572 int i, j, k, frag_size, frag_map_size, offset;
573
574 tx_buf = &ring->tx_buf[ring->tx_next_idx];
575 memset(tx_buf, 0, sizeof(*tx_buf));
576 memset(&txd, 0, sizeof(txd));
577 nr_frags = skb_shinfo(skb)->nr_frags;
578
579 /* init tx descriptor */
580 if (priv->soc->tx_dma)
581 priv->soc->tx_dma(&txd);
582 else
583 txd.txd4 = TX_DMA_DESP4_DEF;
584 def_txd4 = txd.txd4;
585
586 /* TX Checksum offload */
587 if (skb->ip_summed == CHECKSUM_PARTIAL)
588 txd.txd4 |= TX_DMA_CHKSUM;
589
590 /* VLAN header offload */
591 if (skb_vlan_tag_present(skb)) {
592 u16 tag = skb_vlan_tag_get(skb);
593
594 if (IS_ENABLED(CONFIG_SOC_MT7621))
595 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | tag;
596 else
597 txd.txd4 |= TX_DMA_INS_VLAN |
598 ((tag >> VLAN_PRIO_SHIFT) << 4) |
599 (tag & 0xF);
600 }
601
602 /* TSO: fill MSS info in tcp checksum field */
603 if (skb_is_gso(skb)) {
604 if (skb_cow_head(skb, 0)) {
605 netif_warn(priv, tx_err, dev,
606 "GSO expand head fail.\n");
607 goto err_out;
608 }
609 if (skb_shinfo(skb)->gso_type &
610 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
611 txd.txd4 |= TX_DMA_TSO;
612 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
613 }
614 }
615
616 mapped_addr = dma_map_single(&dev->dev, skb->data,
617 skb_headlen(skb), DMA_TO_DEVICE);
618 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
619 goto err_out;
620 txd.txd1 = mapped_addr;
621 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
622
623 tx_buf->flags |= FE_TX_FLAGS_SINGLE0;
624 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
625 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
626
627 /* TX SG offload */
628 j = ring->tx_next_idx;
629 k = 0;
630 for (i = 0; i < nr_frags; i++) {
631 offset = 0;
632 frag = &skb_shinfo(skb)->frags[i];
633 frag_size = skb_frag_size(frag);
634
635 while (frag_size > 0) {
636 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
637 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
638 frag_map_size,
639 DMA_TO_DEVICE);
640 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
641 goto err_dma;
642
643 if (k & 0x1) {
644 j = NEXT_TX_DESP_IDX(j);
645 txd.txd1 = mapped_addr;
646 txd.txd2 = TX_DMA_PLEN0(frag_map_size);
647 txd.txd4 = def_txd4;
648
649 tx_buf = &ring->tx_buf[j];
650 memset(tx_buf, 0, sizeof(*tx_buf));
651
652 tx_buf->flags |= FE_TX_FLAGS_PAGE0;
653 dma_unmap_addr_set(tx_buf, dma_addr0,
654 mapped_addr);
655 dma_unmap_len_set(tx_buf, dma_len0,
656 frag_map_size);
657 } else {
658 txd.txd3 = mapped_addr;
659 txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
660
661 tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
662 tx_buf->flags |= FE_TX_FLAGS_PAGE1;
663 dma_unmap_addr_set(tx_buf, dma_addr1,
664 mapped_addr);
665 dma_unmap_len_set(tx_buf, dma_len1,
666 frag_map_size);
667
668 if (!((i == (nr_frags - 1)) &&
669 (frag_map_size == frag_size))) {
670 fe_set_txd(&txd, &ring->tx_dma[j]);
671 memset(&txd, 0, sizeof(txd));
672 }
673 }
674 frag_size -= frag_map_size;
675 offset += frag_map_size;
676 k++;
677 }
678 }
679
680 /* set last segment */
681 if (k & 0x1)
682 txd.txd2 |= TX_DMA_LS1;
683 else
684 txd.txd2 |= TX_DMA_LS0;
685 fe_set_txd(&txd, &ring->tx_dma[j]);
686
687 /* store skb to cleanup */
688 tx_buf->skb = skb;
689
690 netdev_sent_queue(dev, skb->len);
691 skb_tx_timestamp(skb);
692
693 ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
694 /* make sure that all changes to the dma ring are flushed before we
695 * continue
696 */
697 wmb();
698 if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
699 netif_stop_queue(dev);
700 smp_mb();
701 if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
702 netif_wake_queue(dev);
703 }
704
705 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
706 fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
707
708 return 0;
709
710 err_dma:
711 j = ring->tx_next_idx;
712 for (i = 0; i < tx_num; i++) {
713 ptxd = &ring->tx_dma[j];
714 tx_buf = &ring->tx_buf[j];
715
716 /* unmap dma */
717 fe_txd_unmap(&dev->dev, tx_buf);
718
719 ptxd->txd2 = TX_DMA_DESP2_DEF;
720 j = NEXT_TX_DESP_IDX(j);
721 }
722 /* make sure that all changes to the dma ring are flushed before we
723 * continue
724 */
725 wmb();
726
727 err_out:
728 return -1;
729 }
730
731 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv)
732 {
733 unsigned int len;
734 int ret;
735
736 ret = 0;
737 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
738 if ((priv->flags & FE_FLAG_PADDING_64B) &&
739 !(priv->flags & FE_FLAG_PADDING_BUG))
740 return ret;
741
742 if (skb_vlan_tag_present(skb))
743 len = ETH_ZLEN;
744 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
745 len = VLAN_ETH_ZLEN;
746 else if (!(priv->flags & FE_FLAG_PADDING_64B))
747 len = ETH_ZLEN;
748 else
749 return ret;
750
751 if (skb->len < len) {
752 ret = skb_pad(skb, len - skb->len);
753 if (ret < 0)
754 return ret;
755 skb->len = len;
756 skb_set_tail_pointer(skb, len);
757 }
758 }
759
760 return ret;
761 }
762
763 static inline int fe_cal_txd_req(struct sk_buff *skb)
764 {
765 int i, nfrags;
766 struct skb_frag_struct *frag;
767
768 nfrags = 1;
769 if (skb_is_gso(skb)) {
770 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
771 frag = &skb_shinfo(skb)->frags[i];
772 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
773 }
774 } else {
775 nfrags += skb_shinfo(skb)->nr_frags;
776 }
777
778 return DIV_ROUND_UP(nfrags, 2);
779 }
780
781 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
782 {
783 struct fe_priv *priv = netdev_priv(dev);
784 struct fe_tx_ring *ring = &priv->tx_ring;
785 struct net_device_stats *stats = &dev->stats;
786 int tx_num;
787 int len = skb->len;
788
789 if (fe_skb_padto(skb, priv)) {
790 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
791 return NETDEV_TX_OK;
792 }
793
794 tx_num = fe_cal_txd_req(skb);
795 if (unlikely(fe_empty_txd(ring) <= tx_num)) {
796 netif_stop_queue(dev);
797 netif_err(priv, tx_queued, dev,
798 "Tx Ring full when queue awake!\n");
799 return NETDEV_TX_BUSY;
800 }
801
802 if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
803 stats->tx_dropped++;
804 } else {
805 stats->tx_packets++;
806 stats->tx_bytes += len;
807 }
808
809 return NETDEV_TX_OK;
810 }
811
812 static int fe_poll_rx(struct napi_struct *napi, int budget,
813 struct fe_priv *priv, u32 rx_intr)
814 {
815 struct net_device *netdev = priv->netdev;
816 struct net_device_stats *stats = &netdev->stats;
817 struct fe_soc_data *soc = priv->soc;
818 struct fe_rx_ring *ring = &priv->rx_ring;
819 int idx = ring->rx_calc_idx;
820 u32 checksum_bit;
821 struct sk_buff *skb;
822 u8 *data, *new_data;
823 struct fe_rx_dma *rxd, trxd;
824 int done = 0, pad;
825
826 if (netdev->features & NETIF_F_RXCSUM)
827 checksum_bit = soc->checksum_bit;
828 else
829 checksum_bit = 0;
830
831 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
832 pad = 0;
833 else
834 pad = NET_IP_ALIGN;
835
836 while (done < budget) {
837 unsigned int pktlen;
838 dma_addr_t dma_addr;
839
840 idx = NEXT_RX_DESP_IDX(idx);
841 rxd = &ring->rx_dma[idx];
842 data = ring->rx_data[idx];
843
844 fe_get_rxd(&trxd, rxd);
845 if (!(trxd.rxd2 & RX_DMA_DONE))
846 break;
847
848 /* alloc new buffer */
849 new_data = netdev_alloc_frag(ring->frag_size);
850 if (unlikely(!new_data)) {
851 stats->rx_dropped++;
852 goto release_desc;
853 }
854 dma_addr = dma_map_single(&netdev->dev,
855 new_data + NET_SKB_PAD + pad,
856 ring->rx_buf_size,
857 DMA_FROM_DEVICE);
858 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
859 put_page(virt_to_head_page(new_data));
860 goto release_desc;
861 }
862
863 /* receive data */
864 skb = build_skb(data, ring->frag_size);
865 if (unlikely(!skb)) {
866 put_page(virt_to_head_page(new_data));
867 goto release_desc;
868 }
869 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
870
871 dma_unmap_single(&netdev->dev, trxd.rxd1,
872 ring->rx_buf_size, DMA_FROM_DEVICE);
873 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
874 skb->dev = netdev;
875 skb_put(skb, pktlen);
876 if (trxd.rxd4 & checksum_bit)
877 skb->ip_summed = CHECKSUM_UNNECESSARY;
878 else
879 skb_checksum_none_assert(skb);
880 skb->protocol = eth_type_trans(skb, netdev);
881
882 if (mtk_offload_check_rx(priv, skb, trxd.rxd4) == 0) {
883 stats->rx_packets++;
884 stats->rx_bytes += pktlen;
885
886 napi_gro_receive(napi, skb);
887 } else {
888 dev_kfree_skb(skb);
889 }
890
891 ring->rx_data[idx] = new_data;
892 rxd->rxd1 = (unsigned int)dma_addr;
893
894 release_desc:
895 if (priv->flags & FE_FLAG_RX_SG_DMA)
896 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
897 else
898 rxd->rxd2 = RX_DMA_LSO;
899
900 ring->rx_calc_idx = idx;
901 /* make sure that all changes to the dma ring are flushed before
902 * we continue
903 */
904 wmb();
905 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
906 done++;
907 }
908
909 if (done < budget)
910 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
911
912 return done;
913 }
914
915 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
916 int *tx_again)
917 {
918 struct net_device *netdev = priv->netdev;
919 struct device *dev = &netdev->dev;
920 unsigned int bytes_compl = 0;
921 struct sk_buff *skb;
922 struct fe_tx_buf *tx_buf;
923 int done = 0;
924 u32 idx, hwidx;
925 struct fe_tx_ring *ring = &priv->tx_ring;
926
927 idx = ring->tx_free_idx;
928 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
929
930 while ((idx != hwidx) && budget) {
931 tx_buf = &ring->tx_buf[idx];
932 skb = tx_buf->skb;
933
934 if (!skb)
935 break;
936
937 if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
938 bytes_compl += skb->len;
939 done++;
940 budget--;
941 }
942 fe_txd_unmap(dev, tx_buf);
943 idx = NEXT_TX_DESP_IDX(idx);
944 }
945 ring->tx_free_idx = idx;
946
947 if (idx == hwidx) {
948 /* read hw index again make sure no new tx packet */
949 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
950 if (idx == hwidx)
951 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
952 else
953 *tx_again = 1;
954 } else {
955 *tx_again = 1;
956 }
957
958 if (done) {
959 netdev_completed_queue(netdev, done, bytes_compl);
960 smp_mb();
961 if (unlikely(netif_queue_stopped(netdev) &&
962 (fe_empty_txd(ring) > ring->tx_thresh)))
963 netif_wake_queue(netdev);
964 }
965
966 return done;
967 }
968
969 static int fe_poll(struct napi_struct *napi, int budget)
970 {
971 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
972 struct fe_hw_stats *hwstat = priv->hw_stats;
973 int tx_done, rx_done, tx_again;
974 u32 status, fe_status, status_reg, mask;
975 u32 tx_intr, rx_intr, status_intr;
976
977 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
978 fe_status = status;
979 tx_intr = priv->soc->tx_int;
980 rx_intr = priv->soc->rx_int;
981 status_intr = priv->soc->status_int;
982 tx_done = 0;
983 rx_done = 0;
984 tx_again = 0;
985
986 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
987 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
988 status_reg = FE_REG_FE_INT_STATUS2;
989 } else {
990 status_reg = FE_REG_FE_INT_STATUS;
991 }
992
993 if (status & tx_intr)
994 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
995
996 if (status & rx_intr)
997 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
998
999 if (unlikely(fe_status & status_intr)) {
1000 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
1001 fe_stats_update(priv);
1002 spin_unlock(&hwstat->stats_lock);
1003 }
1004 fe_reg_w32(status_intr, status_reg);
1005 }
1006
1007 if (unlikely(netif_msg_intr(priv))) {
1008 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
1009 netdev_info(priv->netdev,
1010 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
1011 tx_done, rx_done, status, mask);
1012 }
1013
1014 if (!tx_again && (rx_done < budget)) {
1015 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1016 if (status & (tx_intr | rx_intr)) {
1017 /* let napi poll again */
1018 rx_done = budget;
1019 goto poll_again;
1020 }
1021
1022 napi_complete_done(napi, rx_done);
1023 fe_int_enable(tx_intr | rx_intr);
1024 } else {
1025 rx_done = budget;
1026 }
1027
1028 poll_again:
1029 return rx_done;
1030 }
1031
1032 static void fe_tx_timeout(struct net_device *dev)
1033 {
1034 struct fe_priv *priv = netdev_priv(dev);
1035 struct fe_tx_ring *ring = &priv->tx_ring;
1036
1037 priv->netdev->stats.tx_errors++;
1038 netif_err(priv, tx_err, dev,
1039 "transmit timed out\n");
1040 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1041 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1042 netif_info(priv, drv, dev, "tx_ring=%d, "
1043 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1044 0, fe_reg_r32(FE_REG_TX_BASE_PTR0),
1045 fe_reg_r32(FE_REG_TX_MAX_CNT0),
1046 fe_reg_r32(FE_REG_TX_CTX_IDX0),
1047 fe_reg_r32(FE_REG_TX_DTX_IDX0),
1048 ring->tx_free_idx,
1049 ring->tx_next_idx);
1050 netif_info(priv, drv, dev,
1051 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1052 0, fe_reg_r32(FE_REG_RX_BASE_PTR0),
1053 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1054 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1055 fe_reg_r32(FE_REG_RX_DRX_IDX0));
1056
1057 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1058 schedule_work(&priv->pending_work);
1059 }
1060
1061 static irqreturn_t fe_handle_irq(int irq, void *dev)
1062 {
1063 struct fe_priv *priv = netdev_priv(dev);
1064 u32 status, int_mask;
1065
1066 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1067
1068 if (unlikely(!status))
1069 return IRQ_NONE;
1070
1071 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1072 if (likely(status & int_mask)) {
1073 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1074 fe_int_disable(int_mask);
1075 __napi_schedule(&priv->rx_napi);
1076 }
1077 } else {
1078 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1079 }
1080
1081 return IRQ_HANDLED;
1082 }
1083
1084 #ifdef CONFIG_NET_POLL_CONTROLLER
1085 static void fe_poll_controller(struct net_device *dev)
1086 {
1087 struct fe_priv *priv = netdev_priv(dev);
1088 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1089
1090 fe_int_disable(int_mask);
1091 fe_handle_irq(dev->irq, dev);
1092 fe_int_enable(int_mask);
1093 }
1094 #endif
1095
1096 int fe_set_clock_cycle(struct fe_priv *priv)
1097 {
1098 unsigned long sysclk = priv->sysclk;
1099
1100 sysclk /= FE_US_CYC_CNT_DIVISOR;
1101 sysclk <<= FE_US_CYC_CNT_SHIFT;
1102
1103 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1104 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1105 sysclk,
1106 FE_FE_GLO_CFG);
1107 return 0;
1108 }
1109
1110 void fe_fwd_config(struct fe_priv *priv)
1111 {
1112 u32 fwd_cfg;
1113
1114 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1115
1116 /* disable jumbo frame */
1117 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1118 fwd_cfg &= ~FE_GDM1_JMB_EN;
1119
1120 /* set unicast/multicast/broadcast frame to cpu */
1121 fwd_cfg &= ~0xffff;
1122
1123 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1124 }
1125
1126 static void fe_rxcsum_config(bool enable)
1127 {
1128 if (enable)
1129 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1130 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1131 FE_GDMA1_FWD_CFG);
1132 else
1133 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1134 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1135 FE_GDMA1_FWD_CFG);
1136 }
1137
1138 static void fe_txcsum_config(bool enable)
1139 {
1140 if (enable)
1141 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1142 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1143 FE_CDMA_CSG_CFG);
1144 else
1145 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1146 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1147 FE_CDMA_CSG_CFG);
1148 }
1149
1150 void fe_csum_config(struct fe_priv *priv)
1151 {
1152 struct net_device *dev = priv_netdev(priv);
1153
1154 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1155 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1156 }
1157
1158 static int fe_hw_init(struct net_device *dev)
1159 {
1160 struct fe_priv *priv = netdev_priv(dev);
1161 int i, err;
1162
1163 err = devm_request_irq(priv->dev, dev->irq, fe_handle_irq, 0,
1164 dev_name(priv->dev), dev);
1165 if (err)
1166 return err;
1167
1168 if (priv->soc->set_mac)
1169 priv->soc->set_mac(priv, dev->dev_addr);
1170 else
1171 fe_hw_set_macaddr(priv, dev->dev_addr);
1172
1173 /* disable delay interrupt */
1174 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1175
1176 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1177
1178 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1179 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1180 for (i = 0; i < 16; i += 2)
1181 fe_w32(((i + 1) << 16) + i,
1182 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1183 (i * 2));
1184
1185 if (priv->soc->fwd_config(priv))
1186 netdev_err(dev, "unable to get clock\n");
1187
1188 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1189 fe_reg_w32(1, FE_REG_FE_RST_GL);
1190 fe_reg_w32(0, FE_REG_FE_RST_GL);
1191 }
1192
1193 return 0;
1194 }
1195
1196 static int fe_open(struct net_device *dev)
1197 {
1198 struct fe_priv *priv = netdev_priv(dev);
1199 unsigned long flags;
1200 u32 val;
1201 int err;
1202
1203 err = fe_init_dma(priv);
1204 if (err) {
1205 fe_free_dma(priv);
1206 return err;
1207 }
1208
1209 spin_lock_irqsave(&priv->page_lock, flags);
1210
1211 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1212 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1213 val |= FE_RX_2B_OFFSET;
1214 val |= priv->soc->pdma_glo_cfg;
1215 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1216
1217 spin_unlock_irqrestore(&priv->page_lock, flags);
1218
1219 if (priv->phy)
1220 priv->phy->start(priv);
1221
1222 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1223 netif_carrier_on(dev);
1224
1225 napi_enable(&priv->rx_napi);
1226 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1227 netif_start_queue(dev);
1228 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1229 mtk_ppe_probe(priv);
1230 #endif
1231
1232 return 0;
1233 }
1234
1235 static int fe_stop(struct net_device *dev)
1236 {
1237 struct fe_priv *priv = netdev_priv(dev);
1238 unsigned long flags;
1239 int i;
1240
1241 netif_tx_disable(dev);
1242 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1243 napi_disable(&priv->rx_napi);
1244
1245 if (priv->phy)
1246 priv->phy->stop(priv);
1247
1248 spin_lock_irqsave(&priv->page_lock, flags);
1249
1250 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1251 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1252 FE_REG_PDMA_GLO_CFG);
1253 spin_unlock_irqrestore(&priv->page_lock, flags);
1254
1255 /* wait dma stop */
1256 for (i = 0; i < 10; i++) {
1257 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1258 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1259 msleep(20);
1260 continue;
1261 }
1262 break;
1263 }
1264
1265 fe_free_dma(priv);
1266
1267 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1268 mtk_ppe_remove(priv);
1269 #endif
1270
1271 return 0;
1272 }
1273
1274 static int __init fe_init(struct net_device *dev)
1275 {
1276 struct fe_priv *priv = netdev_priv(dev);
1277 struct device_node *port;
1278 const char *mac_addr;
1279 int err;
1280
1281 priv->soc->reset_fe();
1282
1283 if (priv->soc->switch_init)
1284 if (priv->soc->switch_init(priv)) {
1285 netdev_err(dev, "failed to initialize switch core\n");
1286 return -ENODEV;
1287 }
1288
1289 mac_addr = of_get_mac_address(priv->dev->of_node);
1290 if (mac_addr)
1291 ether_addr_copy(dev->dev_addr, mac_addr);
1292
1293 /* If the mac address is invalid, use random mac address */
1294 if (!is_valid_ether_addr(dev->dev_addr)) {
1295 random_ether_addr(dev->dev_addr);
1296 dev_err(priv->dev, "generated random MAC address %pM\n",
1297 dev->dev_addr);
1298 }
1299
1300 err = fe_mdio_init(priv);
1301 if (err)
1302 return err;
1303
1304 if (priv->soc->port_init)
1305 for_each_child_of_node(priv->dev->of_node, port)
1306 if (of_device_is_compatible(port, "mediatek,eth-port") &&
1307 of_device_is_available(port))
1308 priv->soc->port_init(priv, port);
1309
1310 if (priv->phy) {
1311 err = priv->phy->connect(priv);
1312 if (err)
1313 goto err_phy_disconnect;
1314 }
1315
1316 err = fe_hw_init(dev);
1317 if (err)
1318 goto err_phy_disconnect;
1319
1320 if ((priv->flags & FE_FLAG_HAS_SWITCH) && priv->soc->switch_config)
1321 priv->soc->switch_config(priv);
1322
1323 return 0;
1324
1325 err_phy_disconnect:
1326 if (priv->phy)
1327 priv->phy->disconnect(priv);
1328 fe_mdio_cleanup(priv);
1329
1330 return err;
1331 }
1332
1333 static void fe_uninit(struct net_device *dev)
1334 {
1335 struct fe_priv *priv = netdev_priv(dev);
1336
1337 if (priv->phy)
1338 priv->phy->disconnect(priv);
1339 fe_mdio_cleanup(priv);
1340
1341 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1342 free_irq(dev->irq, dev);
1343 }
1344
1345 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1346 {
1347 struct fe_priv *priv = netdev_priv(dev);
1348
1349 if (!priv->phy_dev)
1350 return -ENODEV;
1351
1352 switch (cmd) {
1353 case SIOCETHTOOL:
1354 return phy_ethtool_ioctl(priv->phy_dev,
1355 (void *) ifr->ifr_data);
1356 case SIOCGMIIPHY:
1357 case SIOCGMIIREG:
1358 case SIOCSMIIREG:
1359 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1360 default:
1361 break;
1362 }
1363
1364 return -EOPNOTSUPP;
1365 }
1366
1367 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1368 {
1369 struct fe_priv *priv = netdev_priv(dev);
1370 int frag_size, old_mtu;
1371 u32 fwd_cfg;
1372
1373 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1374 return eth_change_mtu(dev, new_mtu);
1375
1376 if (IS_ENABLED(CONFIG_SOC_MT7621))
1377 if (new_mtu > 2048)
1378 return -EINVAL;
1379
1380 frag_size = fe_max_frag_size(new_mtu);
1381 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1382 return -EINVAL;
1383
1384 old_mtu = dev->mtu;
1385 dev->mtu = new_mtu;
1386
1387 /* return early if the buffer sizes will not change */
1388 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1389 return 0;
1390 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1391 return 0;
1392
1393 if (new_mtu <= ETH_DATA_LEN)
1394 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1395 else
1396 priv->rx_ring.frag_size = PAGE_SIZE;
1397 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1398
1399 if (!netif_running(dev))
1400 return 0;
1401
1402 fe_stop(dev);
1403 if (!IS_ENABLED(CONFIG_SOC_MT7621)) {
1404 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1405 if (new_mtu <= ETH_DATA_LEN) {
1406 fwd_cfg &= ~FE_GDM1_JMB_EN;
1407 } else {
1408 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1409 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1410 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1411 }
1412 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1413 }
1414
1415 return fe_open(dev);
1416 }
1417
1418 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1419 static int
1420 fe_flow_offload(enum flow_offload_type type, struct flow_offload *flow,
1421 struct flow_offload_hw_path *src,
1422 struct flow_offload_hw_path *dest)
1423 {
1424 struct fe_priv *priv;
1425
1426 if (src->dev != dest->dev)
1427 return -EINVAL;
1428
1429 priv = netdev_priv(src->dev);
1430
1431 return mtk_flow_offload(priv, type, flow, src, dest);
1432 }
1433 #endif
1434
1435 static const struct net_device_ops fe_netdev_ops = {
1436 .ndo_init = fe_init,
1437 .ndo_uninit = fe_uninit,
1438 .ndo_open = fe_open,
1439 .ndo_stop = fe_stop,
1440 .ndo_start_xmit = fe_start_xmit,
1441 .ndo_set_mac_address = fe_set_mac_address,
1442 .ndo_validate_addr = eth_validate_addr,
1443 .ndo_do_ioctl = fe_do_ioctl,
1444 .ndo_change_mtu = fe_change_mtu,
1445 .ndo_tx_timeout = fe_tx_timeout,
1446 .ndo_get_stats64 = fe_get_stats64,
1447 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1448 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1449 #ifdef CONFIG_NET_POLL_CONTROLLER
1450 .ndo_poll_controller = fe_poll_controller,
1451 #endif
1452 #ifdef CONFIG_NET_MEDIATEK_OFFLOAD
1453 .ndo_flow_offload = fe_flow_offload,
1454 #endif
1455 };
1456
1457 static void fe_reset_pending(struct fe_priv *priv)
1458 {
1459 struct net_device *dev = priv->netdev;
1460 int err;
1461
1462 rtnl_lock();
1463 fe_stop(dev);
1464
1465 err = fe_open(dev);
1466 if (err) {
1467 netif_alert(priv, ifup, dev,
1468 "Driver up/down cycle failed, closing device.\n");
1469 dev_close(dev);
1470 }
1471 rtnl_unlock();
1472 }
1473
1474 static const struct fe_work_t fe_work[] = {
1475 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1476 };
1477
1478 static void fe_pending_work(struct work_struct *work)
1479 {
1480 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1481 int i;
1482 bool pending;
1483
1484 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1485 pending = test_and_clear_bit(fe_work[i].bitnr,
1486 priv->pending_flags);
1487 if (pending)
1488 fe_work[i].action(priv);
1489 }
1490 }
1491
1492 static int fe_probe(struct platform_device *pdev)
1493 {
1494 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1495 const struct of_device_id *match;
1496 struct fe_soc_data *soc;
1497 struct net_device *netdev;
1498 struct fe_priv *priv;
1499 struct clk *sysclk;
1500 int err, napi_weight;
1501
1502 device_reset(&pdev->dev);
1503
1504 match = of_match_device(of_fe_match, &pdev->dev);
1505 soc = (struct fe_soc_data *)match->data;
1506
1507 if (soc->reg_table)
1508 fe_reg_table = soc->reg_table;
1509 else
1510 soc->reg_table = fe_reg_table;
1511
1512 fe_base = devm_ioremap_resource(&pdev->dev, res);
1513 if (!fe_base) {
1514 err = -EADDRNOTAVAIL;
1515 goto err_out;
1516 }
1517
1518 netdev = alloc_etherdev(sizeof(*priv));
1519 if (!netdev) {
1520 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1521 err = -ENOMEM;
1522 goto err_iounmap;
1523 }
1524
1525 SET_NETDEV_DEV(netdev, &pdev->dev);
1526 netdev->netdev_ops = &fe_netdev_ops;
1527 netdev->base_addr = (unsigned long)fe_base;
1528
1529 netdev->irq = platform_get_irq(pdev, 0);
1530 if (netdev->irq < 0) {
1531 dev_err(&pdev->dev, "no IRQ resource found\n");
1532 err = -ENXIO;
1533 goto err_free_dev;
1534 }
1535
1536 if (soc->init_data)
1537 soc->init_data(soc, netdev);
1538 netdev->vlan_features = netdev->hw_features & ~NETIF_F_HW_VLAN_CTAG_TX;
1539 netdev->features |= netdev->hw_features;
1540
1541 /* fake rx vlan filter func. to support tx vlan offload func */
1542 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1543 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1544
1545 priv = netdev_priv(netdev);
1546 spin_lock_init(&priv->page_lock);
1547 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1548 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1549 if (!priv->hw_stats) {
1550 err = -ENOMEM;
1551 goto err_free_dev;
1552 }
1553 spin_lock_init(&priv->hw_stats->stats_lock);
1554 }
1555
1556 sysclk = devm_clk_get(&pdev->dev, NULL);
1557 if (!IS_ERR(sysclk)) {
1558 priv->sysclk = clk_get_rate(sysclk);
1559 } else if ((priv->flags & FE_FLAG_CALIBRATE_CLK)) {
1560 dev_err(&pdev->dev, "this soc needs a clk for calibration\n");
1561 err = -ENXIO;
1562 goto err_free_dev;
1563 }
1564
1565 priv->switch_np = of_parse_phandle(pdev->dev.of_node, "mediatek,switch", 0);
1566 if ((priv->flags & FE_FLAG_HAS_SWITCH) && !priv->switch_np) {
1567 dev_err(&pdev->dev, "failed to read switch phandle\n");
1568 err = -ENODEV;
1569 goto err_free_dev;
1570 }
1571
1572 priv->netdev = netdev;
1573 priv->dev = &pdev->dev;
1574 priv->soc = soc;
1575 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1576 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1577 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1578 priv->tx_ring.tx_ring_size = NUM_DMA_DESC;
1579 priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
1580 INIT_WORK(&priv->pending_work, fe_pending_work);
1581
1582 napi_weight = 16;
1583 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1584 napi_weight *= 4;
1585 priv->tx_ring.tx_ring_size *= 4;
1586 priv->rx_ring.rx_ring_size *= 4;
1587 }
1588 netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
1589 fe_set_ethtool_ops(netdev);
1590
1591 err = register_netdev(netdev);
1592 if (err) {
1593 dev_err(&pdev->dev, "error bringing up device\n");
1594 goto err_free_dev;
1595 }
1596
1597 platform_set_drvdata(pdev, netdev);
1598
1599 netif_info(priv, probe, netdev, "mediatek frame engine at 0x%08lx, irq %d\n",
1600 netdev->base_addr, netdev->irq);
1601
1602 return 0;
1603
1604 err_free_dev:
1605 free_netdev(netdev);
1606 err_iounmap:
1607 devm_iounmap(&pdev->dev, fe_base);
1608 err_out:
1609 return err;
1610 }
1611
1612 static int fe_remove(struct platform_device *pdev)
1613 {
1614 struct net_device *dev = platform_get_drvdata(pdev);
1615 struct fe_priv *priv = netdev_priv(dev);
1616
1617 netif_napi_del(&priv->rx_napi);
1618 kfree(priv->hw_stats);
1619
1620 cancel_work_sync(&priv->pending_work);
1621
1622 unregister_netdev(dev);
1623 free_netdev(dev);
1624 platform_set_drvdata(pdev, NULL);
1625
1626 return 0;
1627 }
1628
1629 static struct platform_driver fe_driver = {
1630 .probe = fe_probe,
1631 .remove = fe_remove,
1632 .driver = {
1633 .name = "mtk_soc_eth",
1634 .owner = THIS_MODULE,
1635 .of_match_table = of_fe_match,
1636 },
1637 };
1638
1639 module_platform_driver(fe_driver);
1640
1641 MODULE_LICENSE("GPL");
1642 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1643 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1644 MODULE_VERSION(MTK_FE_DRV_VERSION);
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