2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
13 * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/list.h>
20 #include <linux/if_ether.h>
21 #include <linux/skbuff.h>
22 #include <linux/netdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/bitops.h>
25 #include <net/genetlink.h>
26 #include <linux/switch.h>
27 #include <linux/delay.h>
28 #include <linux/phy.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/lockdep.h>
32 #include <linux/workqueue.h>
33 #include <linux/of_device.h>
37 #define MT7530_CPU_PORT 6
38 #define MT7530_NUM_PORTS 8
39 #ifdef CONFIG_SOC_MT7621
40 #define MT7530_NUM_VLANS 4095
42 #define MT7530_NUM_VLANS 16
44 #define MT7530_MAX_VID 4095
45 #define MT7530_MIN_VID 0
48 #define REG_ESW_VLAN_VTCR 0x90
49 #define REG_ESW_VLAN_VAWD1 0x94
50 #define REG_ESW_VLAN_VAWD2 0x98
51 #define REG_ESW_VLAN_VTIM(x) (0x100 + 4 * ((x) / 2))
53 #define REG_ESW_VLAN_VAWD1_IVL_MAC BIT(30)
54 #define REG_ESW_VLAN_VAWD1_VTAG_EN BIT(28)
55 #define REG_ESW_VLAN_VAWD1_VALID BIT(0)
57 /* vlan egress mode */
65 #define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
66 #define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
67 #define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
69 #define REG_HWTRAP 0x7804
71 #define MIB_DESC(_s , _o, _n) \
78 struct mt7xxx_mib_desc
{
84 static const struct mt7xxx_mib_desc mt7620_mibs
[] = {
85 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT0
, "PPE_AC_BCNT0"),
86 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT0
, "PPE_AC_PCNT0"),
87 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT63
, "PPE_AC_BCNT63"),
88 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT63
, "PPE_AC_PCNT63"),
89 MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT0
, "PPE_MTR_CNT0"),
90 MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT63
, "PPE_MTR_CNT63"),
91 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GBCNT
, "GDM1_TX_GBCNT"),
92 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GPCNT
, "GDM1_TX_GPCNT"),
93 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_SKIPCNT
, "GDM1_TX_SKIPCNT"),
94 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_COLCNT
, "GDM1_TX_COLCNT"),
95 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GBCNT1
, "GDM1_RX_GBCNT1"),
96 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GPCNT1
, "GDM1_RX_GPCNT1"),
97 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_OERCNT
, "GDM1_RX_OERCNT"),
98 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FERCNT
, "GDM1_RX_FERCNT"),
99 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_SERCNT
, "GDM1_RX_SERCNT"),
100 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_LERCNT
, "GDM1_RX_LERCNT"),
101 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_CERCNT
, "GDM1_RX_CERCNT"),
102 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FCCNT
, "GDM1_RX_FCCNT"),
103 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GBCNT
, "GDM2_TX_GBCNT"),
104 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GPCNT
, "GDM2_TX_GPCNT"),
105 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_SKIPCNT
, "GDM2_TX_SKIPCNT"),
106 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_COLCNT
, "GDM2_TX_COLCNT"),
107 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GBCNT
, "GDM2_RX_GBCNT"),
108 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GPCNT
, "GDM2_RX_GPCNT"),
109 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_OERCNT
, "GDM2_RX_OERCNT"),
110 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FERCNT
, "GDM2_RX_FERCNT"),
111 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_SERCNT
, "GDM2_RX_SERCNT"),
112 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_LERCNT
, "GDM2_RX_LERCNT"),
113 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_CERCNT
, "GDM2_RX_CERCNT"),
114 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FCCNT
, "GDM2_RX_FCCNT")
117 static const struct mt7xxx_mib_desc mt7620_port_mibs
[] = {
118 MIB_DESC(1, MT7620_MIB_STATS_PORT_TGPCN
, "TxGPC"),
119 MIB_DESC(1, MT7620_MIB_STATS_PORT_TBOCN
, "TxBOC"),
120 MIB_DESC(1, MT7620_MIB_STATS_PORT_TGOCN
, "TxGOC"),
121 MIB_DESC(1, MT7620_MIB_STATS_PORT_TEPCN
, "TxEPC"),
122 MIB_DESC(1, MT7620_MIB_STATS_PORT_RGPCN
, "RxGPC"),
123 MIB_DESC(1, MT7620_MIB_STATS_PORT_RBOCN
, "RxBOC"),
124 MIB_DESC(1, MT7620_MIB_STATS_PORT_RGOCN
, "RxGOC"),
125 MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC1N
, "RxEPC1"),
126 MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC2N
, "RxEPC2")
129 static const struct mt7xxx_mib_desc mt7621_mibs
[] = {
130 MIB_DESC(1, MT7621_STATS_TDPC
, "TxDrop"),
131 MIB_DESC(1, MT7621_STATS_TCRC
, "TxCRC"),
132 MIB_DESC(1, MT7621_STATS_TUPC
, "TxUni"),
133 MIB_DESC(1, MT7621_STATS_TMPC
, "TxMulti"),
134 MIB_DESC(1, MT7621_STATS_TBPC
, "TxBroad"),
135 MIB_DESC(1, MT7621_STATS_TCEC
, "TxCollision"),
136 MIB_DESC(1, MT7621_STATS_TSCEC
, "TxSingleCol"),
137 MIB_DESC(1, MT7621_STATS_TMCEC
, "TxMultiCol"),
138 MIB_DESC(1, MT7621_STATS_TDEC
, "TxDefer"),
139 MIB_DESC(1, MT7621_STATS_TLCEC
, "TxLateCol"),
140 MIB_DESC(1, MT7621_STATS_TXCEC
, "TxExcCol"),
141 MIB_DESC(1, MT7621_STATS_TPPC
, "TxPause"),
142 MIB_DESC(1, MT7621_STATS_TL64PC
, "Tx64Byte"),
143 MIB_DESC(1, MT7621_STATS_TL65PC
, "Tx65Byte"),
144 MIB_DESC(1, MT7621_STATS_TL128PC
, "Tx128Byte"),
145 MIB_DESC(1, MT7621_STATS_TL256PC
, "Tx256Byte"),
146 MIB_DESC(1, MT7621_STATS_TL512PC
, "Tx512Byte"),
147 MIB_DESC(1, MT7621_STATS_TL1024PC
, "Tx1024Byte"),
148 MIB_DESC(2, MT7621_STATS_TOC
, "TxByte"),
149 MIB_DESC(1, MT7621_STATS_RDPC
, "RxDrop"),
150 MIB_DESC(1, MT7621_STATS_RFPC
, "RxFiltered"),
151 MIB_DESC(1, MT7621_STATS_RUPC
, "RxUni"),
152 MIB_DESC(1, MT7621_STATS_RMPC
, "RxMulti"),
153 MIB_DESC(1, MT7621_STATS_RBPC
, "RxBroad"),
154 MIB_DESC(1, MT7621_STATS_RAEPC
, "RxAlignErr"),
155 MIB_DESC(1, MT7621_STATS_RCEPC
, "RxCRC"),
156 MIB_DESC(1, MT7621_STATS_RUSPC
, "RxUnderSize"),
157 MIB_DESC(1, MT7621_STATS_RFEPC
, "RxFragment"),
158 MIB_DESC(1, MT7621_STATS_ROSPC
, "RxOverSize"),
159 MIB_DESC(1, MT7621_STATS_RJEPC
, "RxJabber"),
160 MIB_DESC(1, MT7621_STATS_RPPC
, "RxPause"),
161 MIB_DESC(1, MT7621_STATS_RL64PC
, "Rx64Byte"),
162 MIB_DESC(1, MT7621_STATS_RL65PC
, "Rx65Byte"),
163 MIB_DESC(1, MT7621_STATS_RL128PC
, "Rx128Byte"),
164 MIB_DESC(1, MT7621_STATS_RL256PC
, "Rx256Byte"),
165 MIB_DESC(1, MT7621_STATS_RL512PC
, "Rx512Byte"),
166 MIB_DESC(1, MT7621_STATS_RL1024PC
, "Rx1024Byte"),
167 MIB_DESC(2, MT7621_STATS_ROC
, "RxByte"),
168 MIB_DESC(1, MT7621_STATS_RDPC_CTRL
, "RxCtrlDrop"),
169 MIB_DESC(1, MT7621_STATS_RDPC_ING
, "RxIngDrop"),
170 MIB_DESC(1, MT7621_STATS_RDPC_ARL
, "RxARLDrop")
174 /* Global attributes. */
175 MT7530_ATTR_ENABLE_VLAN
,
178 struct mt7530_port_entry
{
182 struct mt7530_vlan_entry
{
191 struct switch_dev swdev
;
193 bool global_vlan_enable
;
194 struct mt7530_vlan_entry vlan_entries
[MT7530_NUM_VLANS
];
195 struct mt7530_port_entry port_entries
[MT7530_NUM_PORTS
];
198 struct mt7530_mapping
{
200 u16 pvids
[MT7530_NUM_PORTS
];
201 u8 members
[MT7530_NUM_VLANS
];
202 u8 etags
[MT7530_NUM_VLANS
];
203 u16 vids
[MT7530_NUM_VLANS
];
204 } mt7530_defaults
[] = {
207 .pvids
= { 1, 1, 1, 1, 2, 1, 1 },
208 .members
= { 0, 0x6f, 0x50 },
209 .etags
= { 0, 0x40, 0x40 },
213 .pvids
= { 2, 1, 1, 1, 1, 1, 1 },
214 .members
= { 0, 0x7e, 0x41 },
215 .etags
= { 0, 0x40, 0x40 },
220 struct mt7530_mapping
*
221 mt7530_find_mapping(struct device_node
*np
)
226 if (of_property_read_string(np
, "mediatek,portmap", &map
))
229 for (i
= 0; i
< ARRAY_SIZE(mt7530_defaults
); i
++)
230 if (!strcmp(map
, mt7530_defaults
[i
].name
))
231 return &mt7530_defaults
[i
];
237 mt7530_apply_mapping(struct mt7530_priv
*mt7530
, struct mt7530_mapping
*map
)
241 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++)
242 mt7530
->port_entries
[i
].pvid
= map
->pvids
[i
];
244 for (i
= 0; i
< MT7530_NUM_VLANS
; i
++) {
245 mt7530
->vlan_entries
[i
].member
= map
->members
[i
];
246 mt7530
->vlan_entries
[i
].etags
= map
->etags
[i
];
247 mt7530
->vlan_entries
[i
].vid
= map
->vids
[i
];
252 mt7530_reset_switch(struct switch_dev
*dev
)
254 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
257 memset(priv
->port_entries
, 0, sizeof(priv
->port_entries
));
258 memset(priv
->vlan_entries
, 0, sizeof(priv
->vlan_entries
));
260 /* set default vid of each vlan to the same number of vlan, so the vid
261 * won't need be set explicitly.
263 for (i
= 0; i
< MT7530_NUM_VLANS
; i
++) {
264 priv
->vlan_entries
[i
].vid
= i
;
271 mt7530_get_vlan_enable(struct switch_dev
*dev
,
272 const struct switch_attr
*attr
,
273 struct switch_val
*val
)
275 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
277 val
->value
.i
= priv
->global_vlan_enable
;
283 mt7530_set_vlan_enable(struct switch_dev
*dev
,
284 const struct switch_attr
*attr
,
285 struct switch_val
*val
)
287 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
289 priv
->global_vlan_enable
= val
->value
.i
!= 0;
295 mt7530_r32(struct mt7530_priv
*priv
, u32 reg
)
301 mdiobus_write(priv
->bus
, 0x1f, 0x1f, (reg
>> 6) & 0x3ff);
302 low
= mdiobus_read(priv
->bus
, 0x1f, (reg
>> 2) & 0xf);
303 high
= mdiobus_read(priv
->bus
, 0x1f, 0x10);
305 return (high
<< 16) | (low
& 0xffff);
308 val
= ioread32(priv
->base
+ reg
);
309 pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg
, val
);
315 mt7530_w32(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
318 mdiobus_write(priv
->bus
, 0x1f, 0x1f, (reg
>> 6) & 0x3ff);
319 mdiobus_write(priv
->bus
, 0x1f, (reg
>> 2) & 0xf, val
& 0xffff);
320 mdiobus_write(priv
->bus
, 0x1f, 0x10, val
>> 16);
324 pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg
, val
);
325 iowrite32(val
, priv
->base
+ reg
);
329 mt7530_vtcr(struct mt7530_priv
*priv
, u32 cmd
, u32 val
)
333 mt7530_w32(priv
, REG_ESW_VLAN_VTCR
, BIT(31) | (cmd
<< 12) | val
);
335 for (i
= 0; i
< 20; i
++) {
336 u32 val
= mt7530_r32(priv
, REG_ESW_VLAN_VTCR
);
338 if ((val
& BIT(31)) == 0)
344 printk("mt7530: vtcr timeout\n");
348 mt7530_get_port_pvid(struct switch_dev
*dev
, int port
, int *val
)
350 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
352 if (port
>= MT7530_NUM_PORTS
)
355 *val
= mt7530_r32(priv
, REG_ESW_PORT_PPBV1(port
));
362 mt7530_set_port_pvid(struct switch_dev
*dev
, int port
, int pvid
)
364 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
366 if (port
>= MT7530_NUM_PORTS
)
369 if (pvid
< MT7530_MIN_VID
|| pvid
> MT7530_MAX_VID
)
372 priv
->port_entries
[port
].pvid
= pvid
;
378 mt7530_get_vlan_ports(struct switch_dev
*dev
, struct switch_val
*val
)
380 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
387 if (val
->port_vlan
< 0 || val
->port_vlan
>= MT7530_NUM_VLANS
)
390 mt7530_vtcr(priv
, 0, val
->port_vlan
);
392 member
= mt7530_r32(priv
, REG_ESW_VLAN_VAWD1
);
396 etags
= mt7530_r32(priv
, REG_ESW_VLAN_VAWD2
);
398 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
399 struct switch_port
*p
;
402 if (!(member
& BIT(i
)))
405 p
= &val
->value
.ports
[val
->len
++];
408 etag
= (etags
>> (i
* 2)) & 0x3;
410 if (etag
== ETAG_CTRL_TAG
)
411 p
->flags
|= BIT(SWITCH_PORT_FLAG_TAGGED
);
412 else if (etag
!= ETAG_CTRL_UNTAG
)
413 printk("vlan egress tag control neither untag nor tag.\n");
420 mt7530_set_vlan_ports(struct switch_dev
*dev
, struct switch_val
*val
)
422 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
427 if (val
->port_vlan
< 0 || val
->port_vlan
>= MT7530_NUM_VLANS
||
428 val
->len
> MT7530_NUM_PORTS
)
431 for (i
= 0; i
< val
->len
; i
++) {
432 struct switch_port
*p
= &val
->value
.ports
[i
];
434 if (p
->id
>= MT7530_NUM_PORTS
)
437 member
|= BIT(p
->id
);
439 if (p
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
))
442 priv
->vlan_entries
[val
->port_vlan
].member
= member
;
443 priv
->vlan_entries
[val
->port_vlan
].etags
= etags
;
449 mt7530_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
450 struct switch_val
*val
)
452 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
456 vlan
= val
->port_vlan
;
457 vid
= (u16
)val
->value
.i
;
459 if (vlan
< 0 || vlan
>= MT7530_NUM_VLANS
)
462 if (vid
< MT7530_MIN_VID
|| vid
> MT7530_MAX_VID
)
465 priv
->vlan_entries
[vlan
].vid
= vid
;
470 mt7530_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
471 struct switch_val
*val
)
473 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
477 vlan
= val
->port_vlan
;
479 vid
= mt7530_r32(priv
, REG_ESW_VLAN_VTIM(vlan
));
489 mt7530_apply_config(struct switch_dev
*dev
)
491 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
496 if (!priv
->global_vlan_enable
) {
497 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++)
498 mt7530_w32(priv
, REG_ESW_PORT_PCR(i
), 0x00400000);
500 mt7530_w32(priv
, REG_ESW_PORT_PCR(MT7530_CPU_PORT
), 0x00ff0000);
502 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++)
503 mt7530_w32(priv
, REG_ESW_PORT_PVC(i
), 0x810000c0);
508 /* set all ports as security mode */
509 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++)
510 mt7530_w32(priv
, REG_ESW_PORT_PCR(i
), 0x00ff0003);
512 /* check if a port is used in tag/untag vlan egress mode */
516 for (i
= 0; i
< MT7530_NUM_VLANS
; i
++) {
517 u8 member
= priv
->vlan_entries
[i
].member
;
518 u8 etags
= priv
->vlan_entries
[i
].etags
;
523 for (j
= 0; j
< MT7530_NUM_PORTS
; j
++) {
524 if (!(member
& BIT(j
)))
528 tag_ports
|= 1u << j
;
530 untag_ports
|= 1u << j
;
534 /* set all untag-only ports as transparent and the rest as user port */
535 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
536 u32 pvc_mode
= 0x81000000;
538 if (untag_ports
& BIT(i
) && !(tag_ports
& BIT(i
)))
539 pvc_mode
= 0x810000c0;
541 mt7530_w32(priv
, REG_ESW_PORT_PVC(i
), pvc_mode
);
544 for (i
= 0; i
< MT7530_NUM_VLANS
; i
++) {
545 u16 vid
= priv
->vlan_entries
[i
].vid
;
546 u8 member
= priv
->vlan_entries
[i
].member
;
547 u8 etags
= priv
->vlan_entries
[i
].etags
;
550 #ifndef CONFIG_SOC_MT7621
552 val
= mt7530_r32(priv
, REG_ESW_VLAN_VTIM(i
));
560 mt7530_w32(priv
, REG_ESW_VLAN_VTIM(i
), val
);
562 /* vlan port membership */
564 mt7530_w32(priv
, REG_ESW_VLAN_VAWD1
, REG_ESW_VLAN_VAWD1_IVL_MAC
|
565 REG_ESW_VLAN_VAWD1_VTAG_EN
| (member
<< 16) |
566 REG_ESW_VLAN_VAWD1_VALID
);
568 mt7530_w32(priv
, REG_ESW_VLAN_VAWD1
, 0);
572 for (j
= 0; j
< MT7530_NUM_PORTS
; j
++) {
574 val
|= ETAG_CTRL_TAG
<< (j
* 2);
576 val
|= ETAG_CTRL_UNTAG
<< (j
* 2);
578 mt7530_w32(priv
, REG_ESW_VLAN_VAWD2
, val
);
580 /* write to vlan table */
581 #ifdef CONFIG_SOC_MT7621
582 mt7530_vtcr(priv
, 1, vid
);
584 mt7530_vtcr(priv
, 1, i
);
588 /* Port Default PVID */
589 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
591 val
= mt7530_r32(priv
, REG_ESW_PORT_PPBV1(i
));
593 val
|= priv
->port_entries
[i
].pvid
;
594 mt7530_w32(priv
, REG_ESW_PORT_PPBV1(i
), val
);
601 mt7530_get_port_link(struct switch_dev
*dev
, int port
,
602 struct switch_port_link
*link
)
604 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
607 if (port
< 0 || port
>= MT7530_NUM_PORTS
)
610 pmsr
= mt7530_r32(priv
, 0x3008 + (0x100 * port
));
612 link
->link
= pmsr
& 1;
613 link
->duplex
= (pmsr
>> 1) & 1;
614 speed
= (pmsr
>> 2) & 3;
618 link
->speed
= SWITCH_PORT_SPEED_10
;
621 link
->speed
= SWITCH_PORT_SPEED_100
;
624 case 3: /* forced gige speed can be 2 or 3 */
625 link
->speed
= SWITCH_PORT_SPEED_1000
;
628 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
635 static u64
get_mib_counter(struct mt7530_priv
*priv
, int i
, int port
)
637 unsigned int port_base
;
640 port_base
= MT7621_MIB_COUNTER_BASE
+
641 MT7621_MIB_COUNTER_PORT_OFFSET
* port
;
643 lo
= mt7530_r32(priv
, port_base
+ mt7621_mibs
[i
].offset
);
644 if (mt7621_mibs
[i
].size
== 2) {
647 hi
= mt7530_r32(priv
, port_base
+ mt7621_mibs
[i
].offset
+ 4);
654 static int mt7621_sw_get_port_mib(struct switch_dev
*dev
,
655 const struct switch_attr
*attr
,
656 struct switch_val
*val
)
658 static char buf
[4096];
659 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
662 if (val
->port_vlan
>= MT7530_NUM_PORTS
)
665 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
666 "Port %d MIB counters\n", val
->port_vlan
);
668 for (i
= 0; i
< ARRAY_SIZE(mt7621_mibs
); ++i
) {
670 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
671 "%-11s: ", mt7621_mibs
[i
].name
);
672 counter
= get_mib_counter(priv
, i
, val
->port_vlan
);
673 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
, "%llu\n",
682 static u64
get_mib_counter_7620(struct mt7530_priv
*priv
, int i
)
684 return mt7530_r32(priv
, MT7620_MIB_COUNTER_BASE
+ mt7620_mibs
[i
].offset
);
687 static u64
get_mib_counter_port_7620(struct mt7530_priv
*priv
, int i
, int port
)
689 return mt7530_r32(priv
,
690 MT7620_MIB_COUNTER_BASE_PORT
+
691 (MT7620_MIB_COUNTER_PORT_OFFSET
* port
) +
692 mt7620_port_mibs
[i
].offset
);
695 static int mt7530_sw_get_mib(struct switch_dev
*dev
,
696 const struct switch_attr
*attr
,
697 struct switch_val
*val
)
699 static char buf
[4096];
700 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
703 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
, "Switch MIB counters\n");
705 for (i
= 0; i
< ARRAY_SIZE(mt7620_mibs
); ++i
) {
707 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
708 "%-11s: ", mt7620_mibs
[i
].name
);
709 counter
= get_mib_counter_7620(priv
, i
);
710 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
, "%llu\n",
719 static int mt7530_sw_get_port_mib(struct switch_dev
*dev
,
720 const struct switch_attr
*attr
,
721 struct switch_val
*val
)
723 static char buf
[4096];
724 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
727 if (val
->port_vlan
>= MT7530_NUM_PORTS
)
730 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
731 "Port %d MIB counters\n", val
->port_vlan
);
733 for (i
= 0; i
< ARRAY_SIZE(mt7620_port_mibs
); ++i
) {
735 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
736 "%-11s: ", mt7620_port_mibs
[i
].name
);
737 counter
= get_mib_counter_port_7620(priv
, i
, val
->port_vlan
);
738 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
, "%llu\n",
747 static const struct switch_attr mt7530_global
[] = {
749 .type
= SWITCH_TYPE_INT
,
750 .name
= "enable_vlan",
751 .description
= "VLAN mode (1:enabled)",
753 .id
= MT7530_ATTR_ENABLE_VLAN
,
754 .get
= mt7530_get_vlan_enable
,
755 .set
= mt7530_set_vlan_enable
,
757 .type
= SWITCH_TYPE_STRING
,
759 .description
= "Get MIB counters for switch",
760 .get
= mt7530_sw_get_mib
,
765 static const struct switch_attr mt7621_port
[] = {
767 .type
= SWITCH_TYPE_STRING
,
769 .description
= "Get MIB counters for port",
770 .get
= mt7621_sw_get_port_mib
,
775 static const struct switch_attr mt7530_port
[] = {
777 .type
= SWITCH_TYPE_STRING
,
779 .description
= "Get MIB counters for port",
780 .get
= mt7530_sw_get_port_mib
,
785 static const struct switch_attr mt7530_vlan
[] = {
787 .type
= SWITCH_TYPE_INT
,
789 .description
= "VLAN ID (0-4094)",
790 .set
= mt7530_set_vid
,
791 .get
= mt7530_get_vid
,
796 static const struct switch_dev_ops mt7621_ops
= {
798 .attr
= mt7530_global
,
799 .n_attr
= ARRAY_SIZE(mt7530_global
),
803 .n_attr
= ARRAY_SIZE(mt7621_port
),
807 .n_attr
= ARRAY_SIZE(mt7530_vlan
),
809 .get_vlan_ports
= mt7530_get_vlan_ports
,
810 .set_vlan_ports
= mt7530_set_vlan_ports
,
811 .get_port_pvid
= mt7530_get_port_pvid
,
812 .set_port_pvid
= mt7530_set_port_pvid
,
813 .get_port_link
= mt7530_get_port_link
,
814 .apply_config
= mt7530_apply_config
,
815 .reset_switch
= mt7530_reset_switch
,
818 static const struct switch_dev_ops mt7530_ops
= {
820 .attr
= mt7530_global
,
821 .n_attr
= ARRAY_SIZE(mt7530_global
),
825 .n_attr
= ARRAY_SIZE(mt7530_port
),
829 .n_attr
= ARRAY_SIZE(mt7530_vlan
),
831 .get_vlan_ports
= mt7530_get_vlan_ports
,
832 .set_vlan_ports
= mt7530_set_vlan_ports
,
833 .get_port_pvid
= mt7530_get_port_pvid
,
834 .set_port_pvid
= mt7530_set_port_pvid
,
835 .get_port_link
= mt7530_get_port_link
,
836 .apply_config
= mt7530_apply_config
,
837 .reset_switch
= mt7530_reset_switch
,
841 mt7530_probe(struct device
*dev
, void __iomem
*base
, struct mii_bus
*bus
, int vlan
)
843 struct switch_dev
*swdev
;
844 struct mt7530_priv
*mt7530
;
845 struct mt7530_mapping
*map
;
848 mt7530
= devm_kzalloc(dev
, sizeof(struct mt7530_priv
), GFP_KERNEL
);
854 mt7530
->global_vlan_enable
= vlan
;
856 swdev
= &mt7530
->swdev
;
858 swdev
->alias
= "mt7530";
859 swdev
->name
= "mt7530";
860 } else if (IS_ENABLED(CONFIG_SOC_MT7621
)) {
861 swdev
->alias
= "mt7621";
862 swdev
->name
= "mt7621";
864 swdev
->alias
= "mt7620";
865 swdev
->name
= "mt7620";
867 swdev
->cpu_port
= MT7530_CPU_PORT
;
868 swdev
->ports
= MT7530_NUM_PORTS
;
869 swdev
->vlans
= MT7530_NUM_VLANS
;
870 if (IS_ENABLED(CONFIG_SOC_MT7621
))
871 swdev
->ops
= &mt7621_ops
;
873 swdev
->ops
= &mt7530_ops
;
875 ret
= register_switch(swdev
, NULL
);
877 dev_err(dev
, "failed to register mt7530\n");
882 map
= mt7530_find_mapping(dev
->of_node
);
884 mt7530_apply_mapping(mt7530
, map
);
885 mt7530_apply_config(swdev
);
888 if (!IS_ENABLED(CONFIG_SOC_MT7621
) && bus
&& mt7530_r32(mt7530
, REG_HWTRAP
) != 0x1117edf) {
889 dev_info(dev
, "fixing up MHWTRAP register - bootloader probably played with it\n");
890 mt7530_w32(mt7530
, REG_HWTRAP
, 0x1117edf);
892 dev_info(dev
, "loaded %s driver\n", swdev
->name
);