2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version 2
5 * of the License, or (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
13 * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/list.h>
20 #include <linux/if_ether.h>
21 #include <linux/skbuff.h>
22 #include <linux/netdevice.h>
23 #include <linux/netlink.h>
24 #include <linux/bitops.h>
25 #include <net/genetlink.h>
26 #include <linux/switch.h>
27 #include <linux/delay.h>
28 #include <linux/phy.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/lockdep.h>
32 #include <linux/workqueue.h>
33 #include <linux/of_device.h>
37 #define MT7530_CPU_PORT 6
38 #define MT7530_NUM_PORTS 8
39 #ifdef CONFIG_SOC_MT7621
40 #define MT7530_NUM_VLANS 4095
42 #define MT7530_NUM_VLANS 16
44 #define MT7530_MAX_VID 4095
45 #define MT7530_MIN_VID 0
47 #define MT7530_PORT_MIB_TXB_ID 2 /* TxGOC */
48 #define MT7530_PORT_MIB_RXB_ID 6 /* RxGOC */
50 #define MT7621_PORT_MIB_TXB_ID 18 /* TxByte */
51 #define MT7621_PORT_MIB_RXB_ID 37 /* RxByte */
54 #define REG_ESW_VLAN_VTCR 0x90
55 #define REG_ESW_VLAN_VAWD1 0x94
56 #define REG_ESW_VLAN_VAWD2 0x98
57 #define REG_ESW_VLAN_VTIM(x) (0x100 + 4 * ((x) / 2))
59 #define REG_ESW_VLAN_VAWD1_IVL_MAC BIT(30)
60 #define REG_ESW_VLAN_VAWD1_VTAG_EN BIT(28)
61 #define REG_ESW_VLAN_VAWD1_VALID BIT(0)
63 /* vlan egress mode */
71 #define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
72 #define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
73 #define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
75 #define REG_HWTRAP 0x7804
77 #define MIB_DESC(_s , _o, _n) \
84 struct mt7xxx_mib_desc
{
90 static const struct mt7xxx_mib_desc mt7620_mibs
[] = {
91 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT0
, "PPE_AC_BCNT0"),
92 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT0
, "PPE_AC_PCNT0"),
93 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT63
, "PPE_AC_BCNT63"),
94 MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT63
, "PPE_AC_PCNT63"),
95 MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT0
, "PPE_MTR_CNT0"),
96 MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT63
, "PPE_MTR_CNT63"),
97 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GBCNT
, "GDM1_TX_GBCNT"),
98 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GPCNT
, "GDM1_TX_GPCNT"),
99 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_SKIPCNT
, "GDM1_TX_SKIPCNT"),
100 MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_COLCNT
, "GDM1_TX_COLCNT"),
101 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GBCNT1
, "GDM1_RX_GBCNT1"),
102 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GPCNT1
, "GDM1_RX_GPCNT1"),
103 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_OERCNT
, "GDM1_RX_OERCNT"),
104 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FERCNT
, "GDM1_RX_FERCNT"),
105 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_SERCNT
, "GDM1_RX_SERCNT"),
106 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_LERCNT
, "GDM1_RX_LERCNT"),
107 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_CERCNT
, "GDM1_RX_CERCNT"),
108 MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FCCNT
, "GDM1_RX_FCCNT"),
109 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GBCNT
, "GDM2_TX_GBCNT"),
110 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GPCNT
, "GDM2_TX_GPCNT"),
111 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_SKIPCNT
, "GDM2_TX_SKIPCNT"),
112 MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_COLCNT
, "GDM2_TX_COLCNT"),
113 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GBCNT
, "GDM2_RX_GBCNT"),
114 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GPCNT
, "GDM2_RX_GPCNT"),
115 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_OERCNT
, "GDM2_RX_OERCNT"),
116 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FERCNT
, "GDM2_RX_FERCNT"),
117 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_SERCNT
, "GDM2_RX_SERCNT"),
118 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_LERCNT
, "GDM2_RX_LERCNT"),
119 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_CERCNT
, "GDM2_RX_CERCNT"),
120 MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FCCNT
, "GDM2_RX_FCCNT")
123 static const struct mt7xxx_mib_desc mt7620_port_mibs
[] = {
124 MIB_DESC(1, MT7620_MIB_STATS_PORT_TGPCN
, "TxGPC"),
125 MIB_DESC(1, MT7620_MIB_STATS_PORT_TBOCN
, "TxBOC"),
126 MIB_DESC(1, MT7620_MIB_STATS_PORT_TGOCN
, "TxGOC"),
127 MIB_DESC(1, MT7620_MIB_STATS_PORT_TEPCN
, "TxEPC"),
128 MIB_DESC(1, MT7620_MIB_STATS_PORT_RGPCN
, "RxGPC"),
129 MIB_DESC(1, MT7620_MIB_STATS_PORT_RBOCN
, "RxBOC"),
130 MIB_DESC(1, MT7620_MIB_STATS_PORT_RGOCN
, "RxGOC"),
131 MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC1N
, "RxEPC1"),
132 MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC2N
, "RxEPC2")
135 static const struct mt7xxx_mib_desc mt7621_mibs
[] = {
136 MIB_DESC(1, MT7621_STATS_TDPC
, "TxDrop"),
137 MIB_DESC(1, MT7621_STATS_TCRC
, "TxCRC"),
138 MIB_DESC(1, MT7621_STATS_TUPC
, "TxUni"),
139 MIB_DESC(1, MT7621_STATS_TMPC
, "TxMulti"),
140 MIB_DESC(1, MT7621_STATS_TBPC
, "TxBroad"),
141 MIB_DESC(1, MT7621_STATS_TCEC
, "TxCollision"),
142 MIB_DESC(1, MT7621_STATS_TSCEC
, "TxSingleCol"),
143 MIB_DESC(1, MT7621_STATS_TMCEC
, "TxMultiCol"),
144 MIB_DESC(1, MT7621_STATS_TDEC
, "TxDefer"),
145 MIB_DESC(1, MT7621_STATS_TLCEC
, "TxLateCol"),
146 MIB_DESC(1, MT7621_STATS_TXCEC
, "TxExcCol"),
147 MIB_DESC(1, MT7621_STATS_TPPC
, "TxPause"),
148 MIB_DESC(1, MT7621_STATS_TL64PC
, "Tx64Byte"),
149 MIB_DESC(1, MT7621_STATS_TL65PC
, "Tx65Byte"),
150 MIB_DESC(1, MT7621_STATS_TL128PC
, "Tx128Byte"),
151 MIB_DESC(1, MT7621_STATS_TL256PC
, "Tx256Byte"),
152 MIB_DESC(1, MT7621_STATS_TL512PC
, "Tx512Byte"),
153 MIB_DESC(1, MT7621_STATS_TL1024PC
, "Tx1024Byte"),
154 MIB_DESC(2, MT7621_STATS_TOC
, "TxByte"),
155 MIB_DESC(1, MT7621_STATS_RDPC
, "RxDrop"),
156 MIB_DESC(1, MT7621_STATS_RFPC
, "RxFiltered"),
157 MIB_DESC(1, MT7621_STATS_RUPC
, "RxUni"),
158 MIB_DESC(1, MT7621_STATS_RMPC
, "RxMulti"),
159 MIB_DESC(1, MT7621_STATS_RBPC
, "RxBroad"),
160 MIB_DESC(1, MT7621_STATS_RAEPC
, "RxAlignErr"),
161 MIB_DESC(1, MT7621_STATS_RCEPC
, "RxCRC"),
162 MIB_DESC(1, MT7621_STATS_RUSPC
, "RxUnderSize"),
163 MIB_DESC(1, MT7621_STATS_RFEPC
, "RxFragment"),
164 MIB_DESC(1, MT7621_STATS_ROSPC
, "RxOverSize"),
165 MIB_DESC(1, MT7621_STATS_RJEPC
, "RxJabber"),
166 MIB_DESC(1, MT7621_STATS_RPPC
, "RxPause"),
167 MIB_DESC(1, MT7621_STATS_RL64PC
, "Rx64Byte"),
168 MIB_DESC(1, MT7621_STATS_RL65PC
, "Rx65Byte"),
169 MIB_DESC(1, MT7621_STATS_RL128PC
, "Rx128Byte"),
170 MIB_DESC(1, MT7621_STATS_RL256PC
, "Rx256Byte"),
171 MIB_DESC(1, MT7621_STATS_RL512PC
, "Rx512Byte"),
172 MIB_DESC(1, MT7621_STATS_RL1024PC
, "Rx1024Byte"),
173 MIB_DESC(2, MT7621_STATS_ROC
, "RxByte"),
174 MIB_DESC(1, MT7621_STATS_RDPC_CTRL
, "RxCtrlDrop"),
175 MIB_DESC(1, MT7621_STATS_RDPC_ING
, "RxIngDrop"),
176 MIB_DESC(1, MT7621_STATS_RDPC_ARL
, "RxARLDrop")
180 /* Global attributes. */
181 MT7530_ATTR_ENABLE_VLAN
,
184 struct mt7530_port_entry
{
188 struct mt7530_vlan_entry
{
197 struct switch_dev swdev
;
199 bool global_vlan_enable
;
200 struct mt7530_vlan_entry vlan_entries
[MT7530_NUM_VLANS
];
201 struct mt7530_port_entry port_entries
[MT7530_NUM_PORTS
];
204 struct mt7530_mapping
{
206 u16 pvids
[MT7530_NUM_PORTS
];
207 u8 members
[MT7530_NUM_VLANS
];
208 u8 etags
[MT7530_NUM_VLANS
];
209 u16 vids
[MT7530_NUM_VLANS
];
210 } mt7530_defaults
[] = {
213 .pvids
= { 1, 1, 1, 1, 2, 1, 1 },
214 .members
= { 0, 0x6f, 0x50 },
215 .etags
= { 0, 0x40, 0x40 },
219 .pvids
= { 2, 1, 1, 1, 1, 1, 1 },
220 .members
= { 0, 0x7e, 0x41 },
221 .etags
= { 0, 0x40, 0x40 },
226 struct mt7530_mapping
*
227 mt7530_find_mapping(struct device_node
*np
)
232 if (of_property_read_string(np
, "mediatek,portmap", &map
))
235 for (i
= 0; i
< ARRAY_SIZE(mt7530_defaults
); i
++)
236 if (!strcmp(map
, mt7530_defaults
[i
].name
))
237 return &mt7530_defaults
[i
];
243 mt7530_apply_mapping(struct mt7530_priv
*mt7530
, struct mt7530_mapping
*map
)
247 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++)
248 mt7530
->port_entries
[i
].pvid
= map
->pvids
[i
];
250 for (i
= 0; i
< MT7530_NUM_VLANS
; i
++) {
251 mt7530
->vlan_entries
[i
].member
= map
->members
[i
];
252 mt7530
->vlan_entries
[i
].etags
= map
->etags
[i
];
253 mt7530
->vlan_entries
[i
].vid
= map
->vids
[i
];
258 mt7530_reset_switch(struct switch_dev
*dev
)
260 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
263 memset(priv
->port_entries
, 0, sizeof(priv
->port_entries
));
264 memset(priv
->vlan_entries
, 0, sizeof(priv
->vlan_entries
));
266 /* set default vid of each vlan to the same number of vlan, so the vid
267 * won't need be set explicitly.
269 for (i
= 0; i
< MT7530_NUM_VLANS
; i
++) {
270 priv
->vlan_entries
[i
].vid
= i
;
277 mt7530_get_vlan_enable(struct switch_dev
*dev
,
278 const struct switch_attr
*attr
,
279 struct switch_val
*val
)
281 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
283 val
->value
.i
= priv
->global_vlan_enable
;
289 mt7530_set_vlan_enable(struct switch_dev
*dev
,
290 const struct switch_attr
*attr
,
291 struct switch_val
*val
)
293 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
295 priv
->global_vlan_enable
= val
->value
.i
!= 0;
301 mt7530_r32(struct mt7530_priv
*priv
, u32 reg
)
307 mdiobus_write(priv
->bus
, 0x1f, 0x1f, (reg
>> 6) & 0x3ff);
308 low
= mdiobus_read(priv
->bus
, 0x1f, (reg
>> 2) & 0xf);
309 high
= mdiobus_read(priv
->bus
, 0x1f, 0x10);
311 return (high
<< 16) | (low
& 0xffff);
314 val
= ioread32(priv
->base
+ reg
);
315 pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg
, val
);
321 mt7530_w32(struct mt7530_priv
*priv
, u32 reg
, u32 val
)
324 mdiobus_write(priv
->bus
, 0x1f, 0x1f, (reg
>> 6) & 0x3ff);
325 mdiobus_write(priv
->bus
, 0x1f, (reg
>> 2) & 0xf, val
& 0xffff);
326 mdiobus_write(priv
->bus
, 0x1f, 0x10, val
>> 16);
330 pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg
, val
);
331 iowrite32(val
, priv
->base
+ reg
);
335 mt7530_vtcr(struct mt7530_priv
*priv
, u32 cmd
, u32 val
)
339 mt7530_w32(priv
, REG_ESW_VLAN_VTCR
, BIT(31) | (cmd
<< 12) | val
);
341 for (i
= 0; i
< 20; i
++) {
342 u32 val
= mt7530_r32(priv
, REG_ESW_VLAN_VTCR
);
344 if ((val
& BIT(31)) == 0)
350 printk("mt7530: vtcr timeout\n");
354 mt7530_get_port_pvid(struct switch_dev
*dev
, int port
, int *val
)
356 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
358 if (port
>= MT7530_NUM_PORTS
)
361 *val
= mt7530_r32(priv
, REG_ESW_PORT_PPBV1(port
));
368 mt7530_set_port_pvid(struct switch_dev
*dev
, int port
, int pvid
)
370 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
372 if (port
>= MT7530_NUM_PORTS
)
375 if (pvid
< MT7530_MIN_VID
|| pvid
> MT7530_MAX_VID
)
378 priv
->port_entries
[port
].pvid
= pvid
;
384 mt7530_get_vlan_ports(struct switch_dev
*dev
, struct switch_val
*val
)
386 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
393 if (val
->port_vlan
< 0 || val
->port_vlan
>= MT7530_NUM_VLANS
)
396 mt7530_vtcr(priv
, 0, val
->port_vlan
);
398 member
= mt7530_r32(priv
, REG_ESW_VLAN_VAWD1
);
402 etags
= mt7530_r32(priv
, REG_ESW_VLAN_VAWD2
);
404 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
405 struct switch_port
*p
;
408 if (!(member
& BIT(i
)))
411 p
= &val
->value
.ports
[val
->len
++];
414 etag
= (etags
>> (i
* 2)) & 0x3;
416 if (etag
== ETAG_CTRL_TAG
)
417 p
->flags
|= BIT(SWITCH_PORT_FLAG_TAGGED
);
418 else if (etag
!= ETAG_CTRL_UNTAG
)
419 printk("vlan egress tag control neither untag nor tag.\n");
426 mt7530_set_vlan_ports(struct switch_dev
*dev
, struct switch_val
*val
)
428 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
433 if (val
->port_vlan
< 0 || val
->port_vlan
>= MT7530_NUM_VLANS
||
434 val
->len
> MT7530_NUM_PORTS
)
437 for (i
= 0; i
< val
->len
; i
++) {
438 struct switch_port
*p
= &val
->value
.ports
[i
];
440 if (p
->id
>= MT7530_NUM_PORTS
)
443 member
|= BIT(p
->id
);
445 if (p
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
))
448 priv
->vlan_entries
[val
->port_vlan
].member
= member
;
449 priv
->vlan_entries
[val
->port_vlan
].etags
= etags
;
455 mt7530_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
456 struct switch_val
*val
)
458 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
462 vlan
= val
->port_vlan
;
463 vid
= (u16
)val
->value
.i
;
465 if (vlan
< 0 || vlan
>= MT7530_NUM_VLANS
)
468 if (vid
< MT7530_MIN_VID
|| vid
> MT7530_MAX_VID
)
471 priv
->vlan_entries
[vlan
].vid
= vid
;
476 mt7530_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
477 struct switch_val
*val
)
479 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
483 vlan
= val
->port_vlan
;
485 vid
= mt7530_r32(priv
, REG_ESW_VLAN_VTIM(vlan
));
495 mt7530_apply_config(struct switch_dev
*dev
)
497 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
502 if (!priv
->global_vlan_enable
) {
503 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++)
504 mt7530_w32(priv
, REG_ESW_PORT_PCR(i
), 0x00400000);
506 mt7530_w32(priv
, REG_ESW_PORT_PCR(MT7530_CPU_PORT
), 0x00ff0000);
508 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++)
509 mt7530_w32(priv
, REG_ESW_PORT_PVC(i
), 0x810000c0);
514 /* set all ports as security mode */
515 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++)
516 mt7530_w32(priv
, REG_ESW_PORT_PCR(i
), 0x00ff0003);
518 /* check if a port is used in tag/untag vlan egress mode */
522 for (i
= 0; i
< MT7530_NUM_VLANS
; i
++) {
523 u8 member
= priv
->vlan_entries
[i
].member
;
524 u8 etags
= priv
->vlan_entries
[i
].etags
;
529 for (j
= 0; j
< MT7530_NUM_PORTS
; j
++) {
530 if (!(member
& BIT(j
)))
534 tag_ports
|= 1u << j
;
536 untag_ports
|= 1u << j
;
540 /* set all untag-only ports as transparent and the rest as user port */
541 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
542 u32 pvc_mode
= 0x81000000;
544 if (untag_ports
& BIT(i
) && !(tag_ports
& BIT(i
)))
545 pvc_mode
= 0x810000c0;
547 mt7530_w32(priv
, REG_ESW_PORT_PVC(i
), pvc_mode
);
550 for (i
= 0; i
< MT7530_NUM_VLANS
; i
++) {
551 u16 vid
= priv
->vlan_entries
[i
].vid
;
552 u8 member
= priv
->vlan_entries
[i
].member
;
553 u8 etags
= priv
->vlan_entries
[i
].etags
;
556 #ifndef CONFIG_SOC_MT7621
558 val
= mt7530_r32(priv
, REG_ESW_VLAN_VTIM(i
));
566 mt7530_w32(priv
, REG_ESW_VLAN_VTIM(i
), val
);
568 /* vlan port membership */
570 mt7530_w32(priv
, REG_ESW_VLAN_VAWD1
, REG_ESW_VLAN_VAWD1_IVL_MAC
|
571 REG_ESW_VLAN_VAWD1_VTAG_EN
| (member
<< 16) |
572 REG_ESW_VLAN_VAWD1_VALID
);
574 mt7530_w32(priv
, REG_ESW_VLAN_VAWD1
, 0);
578 for (j
= 0; j
< MT7530_NUM_PORTS
; j
++) {
580 val
|= ETAG_CTRL_TAG
<< (j
* 2);
582 val
|= ETAG_CTRL_UNTAG
<< (j
* 2);
584 mt7530_w32(priv
, REG_ESW_VLAN_VAWD2
, val
);
586 /* write to vlan table */
587 #ifdef CONFIG_SOC_MT7621
588 mt7530_vtcr(priv
, 1, vid
);
590 mt7530_vtcr(priv
, 1, i
);
594 /* Port Default PVID */
595 for (i
= 0; i
< MT7530_NUM_PORTS
; i
++) {
597 val
= mt7530_r32(priv
, REG_ESW_PORT_PPBV1(i
));
599 val
|= priv
->port_entries
[i
].pvid
;
600 mt7530_w32(priv
, REG_ESW_PORT_PPBV1(i
), val
);
607 mt7530_get_port_link(struct switch_dev
*dev
, int port
,
608 struct switch_port_link
*link
)
610 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
613 if (port
< 0 || port
>= MT7530_NUM_PORTS
)
616 pmsr
= mt7530_r32(priv
, 0x3008 + (0x100 * port
));
618 link
->link
= pmsr
& 1;
619 link
->duplex
= (pmsr
>> 1) & 1;
620 speed
= (pmsr
>> 2) & 3;
624 link
->speed
= SWITCH_PORT_SPEED_10
;
627 link
->speed
= SWITCH_PORT_SPEED_100
;
630 case 3: /* forced gige speed can be 2 or 3 */
631 link
->speed
= SWITCH_PORT_SPEED_1000
;
634 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
641 static u64
get_mib_counter(struct mt7530_priv
*priv
, int i
, int port
)
643 unsigned int port_base
;
646 port_base
= MT7621_MIB_COUNTER_BASE
+
647 MT7621_MIB_COUNTER_PORT_OFFSET
* port
;
649 lo
= mt7530_r32(priv
, port_base
+ mt7621_mibs
[i
].offset
);
650 if (mt7621_mibs
[i
].size
== 2) {
653 hi
= mt7530_r32(priv
, port_base
+ mt7621_mibs
[i
].offset
+ 4);
660 static int mt7621_sw_get_port_mib(struct switch_dev
*dev
,
661 const struct switch_attr
*attr
,
662 struct switch_val
*val
)
664 static char buf
[4096];
665 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
668 if (val
->port_vlan
>= MT7530_NUM_PORTS
)
671 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
672 "Port %d MIB counters\n", val
->port_vlan
);
674 for (i
= 0; i
< ARRAY_SIZE(mt7621_mibs
); ++i
) {
676 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
677 "%-11s: ", mt7621_mibs
[i
].name
);
678 counter
= get_mib_counter(priv
, i
, val
->port_vlan
);
679 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
, "%llu\n",
688 static u64
get_mib_counter_7620(struct mt7530_priv
*priv
, int i
)
690 return mt7530_r32(priv
, MT7620_MIB_COUNTER_BASE
+ mt7620_mibs
[i
].offset
);
693 static u64
get_mib_counter_port_7620(struct mt7530_priv
*priv
, int i
, int port
)
695 return mt7530_r32(priv
,
696 MT7620_MIB_COUNTER_BASE_PORT
+
697 (MT7620_MIB_COUNTER_PORT_OFFSET
* port
) +
698 mt7620_port_mibs
[i
].offset
);
701 static int mt7530_sw_get_mib(struct switch_dev
*dev
,
702 const struct switch_attr
*attr
,
703 struct switch_val
*val
)
705 static char buf
[4096];
706 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
709 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
, "Switch MIB counters\n");
711 for (i
= 0; i
< ARRAY_SIZE(mt7620_mibs
); ++i
) {
713 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
714 "%-11s: ", mt7620_mibs
[i
].name
);
715 counter
= get_mib_counter_7620(priv
, i
);
716 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
, "%llu\n",
725 static int mt7530_sw_get_port_mib(struct switch_dev
*dev
,
726 const struct switch_attr
*attr
,
727 struct switch_val
*val
)
729 static char buf
[4096];
730 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
733 if (val
->port_vlan
>= MT7530_NUM_PORTS
)
736 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
737 "Port %d MIB counters\n", val
->port_vlan
);
739 for (i
= 0; i
< ARRAY_SIZE(mt7620_port_mibs
); ++i
) {
741 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
,
742 "%-11s: ", mt7620_port_mibs
[i
].name
);
743 counter
= get_mib_counter_port_7620(priv
, i
, val
->port_vlan
);
744 len
+= snprintf(buf
+ len
, sizeof(buf
) - len
, "%llu\n",
753 static int mt7530_get_port_stats(struct switch_dev
*dev
, int port
,
754 struct switch_port_stats
*stats
)
756 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
758 if (port
< 0 || port
>= MT7530_NUM_PORTS
)
761 stats
->tx_bytes
= get_mib_counter_port_7620(priv
, MT7530_PORT_MIB_TXB_ID
, port
);
762 stats
->rx_bytes
= get_mib_counter_port_7620(priv
, MT7530_PORT_MIB_RXB_ID
, port
);
767 static int mt7621_get_port_stats(struct switch_dev
*dev
, int port
,
768 struct switch_port_stats
*stats
)
770 struct mt7530_priv
*priv
= container_of(dev
, struct mt7530_priv
, swdev
);
772 if (port
< 0 || port
>= MT7530_NUM_PORTS
)
775 stats
->tx_bytes
= get_mib_counter(priv
, MT7621_PORT_MIB_TXB_ID
, port
);
776 stats
->rx_bytes
= get_mib_counter(priv
, MT7621_PORT_MIB_RXB_ID
, port
);
781 static const struct switch_attr mt7530_global
[] = {
783 .type
= SWITCH_TYPE_INT
,
784 .name
= "enable_vlan",
785 .description
= "VLAN mode (1:enabled)",
787 .id
= MT7530_ATTR_ENABLE_VLAN
,
788 .get
= mt7530_get_vlan_enable
,
789 .set
= mt7530_set_vlan_enable
,
791 .type
= SWITCH_TYPE_STRING
,
793 .description
= "Get MIB counters for switch",
794 .get
= mt7530_sw_get_mib
,
799 static const struct switch_attr mt7621_port
[] = {
801 .type
= SWITCH_TYPE_STRING
,
803 .description
= "Get MIB counters for port",
804 .get
= mt7621_sw_get_port_mib
,
809 static const struct switch_attr mt7530_port
[] = {
811 .type
= SWITCH_TYPE_STRING
,
813 .description
= "Get MIB counters for port",
814 .get
= mt7530_sw_get_port_mib
,
819 static const struct switch_attr mt7530_vlan
[] = {
821 .type
= SWITCH_TYPE_INT
,
823 .description
= "VLAN ID (0-4094)",
824 .set
= mt7530_set_vid
,
825 .get
= mt7530_get_vid
,
830 static const struct switch_dev_ops mt7621_ops
= {
832 .attr
= mt7530_global
,
833 .n_attr
= ARRAY_SIZE(mt7530_global
),
837 .n_attr
= ARRAY_SIZE(mt7621_port
),
841 .n_attr
= ARRAY_SIZE(mt7530_vlan
),
843 .get_vlan_ports
= mt7530_get_vlan_ports
,
844 .set_vlan_ports
= mt7530_set_vlan_ports
,
845 .get_port_pvid
= mt7530_get_port_pvid
,
846 .set_port_pvid
= mt7530_set_port_pvid
,
847 .get_port_link
= mt7530_get_port_link
,
848 .get_port_stats
= mt7621_get_port_stats
,
849 .apply_config
= mt7530_apply_config
,
850 .reset_switch
= mt7530_reset_switch
,
853 static const struct switch_dev_ops mt7530_ops
= {
855 .attr
= mt7530_global
,
856 .n_attr
= ARRAY_SIZE(mt7530_global
),
860 .n_attr
= ARRAY_SIZE(mt7530_port
),
864 .n_attr
= ARRAY_SIZE(mt7530_vlan
),
866 .get_vlan_ports
= mt7530_get_vlan_ports
,
867 .set_vlan_ports
= mt7530_set_vlan_ports
,
868 .get_port_pvid
= mt7530_get_port_pvid
,
869 .set_port_pvid
= mt7530_set_port_pvid
,
870 .get_port_link
= mt7530_get_port_link
,
871 .get_port_stats
= mt7530_get_port_stats
,
872 .apply_config
= mt7530_apply_config
,
873 .reset_switch
= mt7530_reset_switch
,
877 mt7530_probe(struct device
*dev
, void __iomem
*base
, struct mii_bus
*bus
, int vlan
)
879 struct switch_dev
*swdev
;
880 struct mt7530_priv
*mt7530
;
881 struct mt7530_mapping
*map
;
884 mt7530
= devm_kzalloc(dev
, sizeof(struct mt7530_priv
), GFP_KERNEL
);
890 mt7530
->global_vlan_enable
= vlan
;
892 swdev
= &mt7530
->swdev
;
894 swdev
->alias
= "mt7530";
895 swdev
->name
= "mt7530";
896 } else if (IS_ENABLED(CONFIG_SOC_MT7621
)) {
897 swdev
->alias
= "mt7621";
898 swdev
->name
= "mt7621";
900 swdev
->alias
= "mt7620";
901 swdev
->name
= "mt7620";
903 swdev
->cpu_port
= MT7530_CPU_PORT
;
904 swdev
->ports
= MT7530_NUM_PORTS
;
905 swdev
->vlans
= MT7530_NUM_VLANS
;
906 if (IS_ENABLED(CONFIG_SOC_MT7621
))
907 swdev
->ops
= &mt7621_ops
;
909 swdev
->ops
= &mt7530_ops
;
911 ret
= register_switch(swdev
, NULL
);
913 dev_err(dev
, "failed to register mt7530\n");
918 map
= mt7530_find_mapping(dev
->of_node
);
920 mt7530_apply_mapping(mt7530
, map
);
921 mt7530_apply_config(swdev
);
924 if (!IS_ENABLED(CONFIG_SOC_MT7621
) && bus
&& mt7530_r32(mt7530
, REG_HWTRAP
) != 0x1117edf) {
925 dev_info(dev
, "fixing up MHWTRAP register - bootloader probably played with it\n");
926 mt7530_w32(mt7530
, REG_HWTRAP
, 0x1117edf);
928 dev_info(dev
, "loaded %s driver\n", swdev
->name
);