2 * Arch specific code for ramips based boards
4 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2018 Tobias Schramm <tobleminer@gmail.com>
6 * Copyright (C) 2023 Antonio Vázquez <antoniovazquezblanco@gmail.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
16 #define KSEG0 0x80000000
17 #define KSEG1 0xa0000000
19 #define _ATYPE_ __PTRDIFF_TYPE__
22 #define _ACAST32_ (_ATYPE_)(_ATYPE32_)
24 #define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
26 #define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
27 #define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
29 #if defined(SOC_MT7620) || defined(SOC_RT3883)
30 #define UART_BASE KSEG1ADDR(0x10000c00)
31 #define UART_THR (UART_BASE + 0x04)
32 #define UART_LSR (UART_BASE + 0x1c)
33 #define UART_LSR_THRE_MASK 0x40
34 #elif defined(SOC_MT7621)
35 #define UART_BASE KSEG1ADDR(0x1e000c00)
36 #define UART_THR (UART_BASE + 0x00)
37 #define UART_LSR (UART_BASE + 0x14)
38 #define UART_LSR_THRE_MASK 0x20
39 #elif defined(SOC_RT305X)
40 #define UART_BASE KSEG1ADDR(0x10000500)
41 #define UART_THR (UART_BASE + 0x04)
42 #define UART_LSR (UART_BASE + 0x1c)
43 #define UART_LSR_THRE_MASK 0x20
45 #error "Unsupported SOC..."
49 #define READREG(r) (*(volatile uint32_t *)(r))
50 #define WRITEREG(r,v) (*(volatile uint32_t *)(r)) = v
57 void board_putc(int ch
)
59 while ((READREG(UART_LSR
) & UART_LSR_THRE_MASK
) == 0);
60 WRITEREG(UART_THR
, ch
);
61 while ((READREG(UART_LSR
) & UART_LSR_THRE_MASK
) == 0);