ae9da380738b900cd2994facc94dc8c81d2410a0
2 * Arch specific code for ramips based boards
4 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2018 Tobias Schramm <tobleminer@gmail.com>
6 * Copyright (C) 2023 Antonio Vázquez <antoniovazquezblanco@gmail.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
15 #if defined(SOC_MT7620) || defined(SOC_RT3883)
16 #define UART_BASE 0xb0000c00
17 #define UART_THR (UART_BASE + 0x04)
18 #define UART_LSR (UART_BASE + 0x1c)
19 #define UART_LSR_THRE_MASK 0x40
20 #elif defined(SOC_MT7621)
21 #define UART_BASE 0xbe000c00
22 #define UART_THR (UART_BASE + 0x00)
23 #define UART_LSR (UART_BASE + 0x14)
24 #define UART_LSR_THRE_MASK 0x20
25 #elif defined(SOC_RT305X)
26 #define UART_BASE 0x10000500
27 #define UART_THR (UART_BASE + 0x04)
28 #define UART_LSR (UART_BASE + 0x1c)
29 #define UART_LSR_THRE_MASK 0x20
31 #error "Unsupported SOC..."
35 #define READREG(r) (*(volatile uint32_t *)(r))
36 #define WRITEREG(r,v) (*(volatile uint32_t *)(r)) = v
43 void board_putc(int ch
)
45 while ((READREG(UART_LSR
) & UART_LSR_THRE_MASK
) == 0);
46 WRITEREG(UART_THR
, ch
);
47 while ((READREG(UART_LSR
) & UART_LSR_THRE_MASK
) == 0);