1 From 55833373cf527dc94bc6c63b68d0f39591667a5d Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 28 Jul 2013 14:00:25 +0200
4 Subject: [PATCH 06/25] GPIO: MIPS: ralink: add gpio driver for ralink SoC
6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
10 Cc: linux-mips@linux-mips.org
11 Cc: linux-gpio@vger.kernel.org
13 arch/mips/Kconfig | 1 +
14 arch/mips/include/asm/mach-ralink/gpio.h | 24 +++
15 drivers/gpio/Kconfig | 6 +
16 drivers/gpio/Makefile | 1 +
17 drivers/gpio/gpio-ralink.c | 337 ++++++++++++++++++++++++++++++
18 5 files changed, 369 insertions(+)
19 create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
20 create mode 100644 drivers/gpio/gpio-ralink.c
22 --- a/arch/mips/Kconfig
23 +++ b/arch/mips/Kconfig
24 @@ -443,6 +443,7 @@ config RALINK
25 select SYS_HAS_EARLY_PRINTK
26 select HAVE_MACH_CLKDEV
28 + select ARCH_REQUIRE_GPIOLIB
31 bool "SGI IP22 (Indy/Indigo2)"
33 +++ b/arch/mips/include/asm/mach-ralink/gpio.h
36 + * Ralink SoC GPIO API support
38 + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
39 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
41 + * This program is free software; you can redistribute it and/or modify it
42 + * under the terms of the GNU General Public License version 2 as published
43 + * by the Free Software Foundation.
47 +#ifndef __ASM_MACH_RALINK_GPIO_H
48 +#define __ASM_MACH_RALINK_GPIO_H
50 +#define ARCH_NR_GPIOS 128
51 +#include <asm-generic/gpio.h>
53 +#define gpio_get_value __gpio_get_value
54 +#define gpio_set_value __gpio_set_value
55 +#define gpio_cansleep __gpio_cansleep
56 +#define gpio_to_irq __gpio_to_irq
58 +#endif /* __ASM_MACH_RALINK_GPIO_H */
59 --- a/drivers/gpio/Kconfig
60 +++ b/drivers/gpio/Kconfig
61 @@ -209,6 +209,12 @@ config GPIO_RCAR
63 Say yes here to support GPIO on Renesas R-Car SoCs.
66 + bool "Ralink GPIO Support"
69 + Say yes here to support the Ralink SoC GPIO device
71 config GPIO_SPEAR_SPICS
72 bool "ST SPEAr13xx SPI Chip Select as GPIO support"
74 --- a/drivers/gpio/Makefile
75 +++ b/drivers/gpio/Makefile
76 @@ -56,6 +56,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf85
77 obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
78 obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
79 obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
80 +obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
81 obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
82 obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
83 obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
85 +++ b/drivers/gpio/gpio-ralink.c
88 + * This program is free software; you can redistribute it and/or modify it
89 + * under the terms of the GNU General Public License version 2 as published
90 + * by the Free Software Foundation.
92 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
93 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
96 +#include <linux/module.h>
97 +#include <linux/io.h>
98 +#include <linux/gpio.h>
99 +#include <linux/spinlock.h>
100 +#include <linux/platform_device.h>
101 +#include <linux/of_irq.h>
102 +#include <linux/irqdomain.h>
103 +#include <linux/interrupt.h>
105 +enum ralink_gpio_reg {
119 +struct ralink_gpio_chip {
120 + struct gpio_chip chip;
121 + u8 regs[GPIO_REG_MAX];
124 + void __iomem *membase;
125 + struct irq_domain *domain;
133 +static struct irq_domain *irq_map[MAP_MAX];
134 +static int irq_map_count;
135 +static atomic_t irq_refcount = ATOMIC_INIT(0);
137 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
139 + struct ralink_gpio_chip *rg;
141 + rg = container_of(chip, struct ralink_gpio_chip, chip);
146 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
148 + iowrite32(val, rg->membase + rg->regs[reg]);
151 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
153 + return ioread32(rg->membase + rg->regs[reg]);
156 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
158 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
160 + rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
163 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
165 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
167 + return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
170 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
172 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
173 + unsigned long flags;
176 + spin_lock_irqsave(&rg->lock, flags);
177 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
179 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
180 + spin_unlock_irqrestore(&rg->lock, flags);
185 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
186 + unsigned offset, int value)
188 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
189 + unsigned long flags;
192 + spin_lock_irqsave(&rg->lock, flags);
193 + ralink_gpio_set(chip, offset, value);
194 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
196 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
197 + spin_unlock_irqrestore(&rg->lock, flags);
202 +static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
204 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
209 + return irq_create_mapping(rg->domain, pin);
212 +static void ralink_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
216 + for (i = 0; i < irq_map_count; i++) {
217 + struct irq_domain *domain = irq_map[i];
218 + struct ralink_gpio_chip *rg;
219 + unsigned long pending;
222 + rg = (struct ralink_gpio_chip *) domain->host_data;
223 + pending = rt_gpio_r32(rg, GPIO_REG_INT);
225 + for_each_set_bit(bit, &pending, rg->chip.ngpio) {
226 + u32 map = irq_find_mapping(domain, bit);
227 + generic_handle_irq(map);
228 + rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
233 +static void ralink_gpio_irq_unmask(struct irq_data *d)
235 + struct ralink_gpio_chip *rg;
236 + unsigned long flags;
239 + rg = (struct ralink_gpio_chip *) d->domain->host_data;
240 + val = rt_gpio_r32(rg, GPIO_REG_RENA);
242 + spin_lock_irqsave(&rg->lock, flags);
243 + rt_gpio_w32(rg, GPIO_REG_RENA, val | (BIT(d->hwirq) & rg->rising));
244 + rt_gpio_w32(rg, GPIO_REG_FENA, val | (BIT(d->hwirq) & rg->falling));
245 + spin_unlock_irqrestore(&rg->lock, flags);
248 +static void ralink_gpio_irq_mask(struct irq_data *d)
250 + struct ralink_gpio_chip *rg;
251 + unsigned long flags;
254 + rg = (struct ralink_gpio_chip *) d->domain->host_data;
255 + val = rt_gpio_r32(rg, GPIO_REG_RENA);
257 + spin_lock_irqsave(&rg->lock, flags);
258 + rt_gpio_w32(rg, GPIO_REG_FENA, val & ~BIT(d->hwirq));
259 + rt_gpio_w32(rg, GPIO_REG_RENA, val & ~BIT(d->hwirq));
260 + spin_unlock_irqrestore(&rg->lock, flags);
263 +static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
265 + struct ralink_gpio_chip *rg;
266 + u32 mask = BIT(d->hwirq);
268 + rg = (struct ralink_gpio_chip *) d->domain->host_data;
270 + if (type == IRQ_TYPE_PROBE) {
271 + if ((rg->rising | rg->falling) & mask)
274 + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_RISING;
277 + if (type & IRQ_TYPE_EDGE_RISING)
278 + rg->rising |= mask;
280 + rg->rising &= mask;
282 + if (type & IRQ_TYPE_EDGE_RISING)
283 + rg->falling |= mask;
285 + rg->falling &= mask;
290 +static struct irq_chip ralink_gpio_irq_chip = {
292 + .irq_unmask = ralink_gpio_irq_unmask,
293 + .irq_mask = ralink_gpio_irq_mask,
294 + .irq_mask_ack = ralink_gpio_irq_mask,
295 + .irq_set_type = ralink_gpio_irq_type,
298 +static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
300 + irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
301 + irq_set_handler_data(irq, d);
306 +static const struct irq_domain_ops irq_domain_ops = {
307 + .xlate = irq_domain_xlate_onecell,
311 +static void ralink_gpio_irq_init(struct device_node *np,
312 + struct ralink_gpio_chip *rg)
314 + if (irq_map_count >= MAP_MAX)
317 + rg->irq = irq_of_parse_and_map(np, 0);
321 + rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
322 + &irq_domain_ops, rg);
324 + dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
328 + irq_map[irq_map_count++] = rg->domain;
330 + rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
331 + rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
333 + if (!atomic_read(&irq_refcount))
334 + irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
335 + atomic_inc(&irq_refcount);
337 + dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
340 +static int ralink_gpio_probe(struct platform_device *pdev)
342 + struct device_node *np = pdev->dev.of_node;
343 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
344 + struct ralink_gpio_chip *rg;
345 + const __be32 *ngpio, *gpiobase;
348 + dev_err(&pdev->dev, "failed to find resource\n");
352 + rg = devm_kzalloc(&pdev->dev,
353 + sizeof(struct ralink_gpio_chip), GFP_KERNEL);
357 + rg->membase = devm_request_and_ioremap(&pdev->dev, res);
358 + if (!rg->membase) {
359 + dev_err(&pdev->dev, "cannot remap I/O memory region\n");
363 + if (of_property_read_u8_array(np, "ralink,register-map",
364 + rg->regs, GPIO_REG_MAX)) {
365 + dev_err(&pdev->dev, "failed to read register definition\n");
369 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
371 + dev_err(&pdev->dev, "failed to read number of pins\n");
375 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
377 + rg->chip.base = be32_to_cpu(*gpiobase);
379 + rg->chip.base = -1;
381 + spin_lock_init(&rg->lock);
383 + rg->chip.dev = &pdev->dev;
384 + rg->chip.label = dev_name(&pdev->dev);
385 + rg->chip.of_node = np;
386 + rg->chip.ngpio = be32_to_cpu(*ngpio);
387 + rg->chip.direction_input = ralink_gpio_direction_input;
388 + rg->chip.direction_output = ralink_gpio_direction_output;
389 + rg->chip.get = ralink_gpio_get;
390 + rg->chip.set = ralink_gpio_set;
391 + rg->chip.to_irq = ralink_gpio_to_irq;
393 + /* set polarity to low for all lines */
394 + rt_gpio_w32(rg, GPIO_REG_POL, 0);
396 + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
398 + ralink_gpio_irq_init(np, rg);
400 + return gpiochip_add(&rg->chip);
403 +static const struct of_device_id ralink_gpio_match[] = {
404 + { .compatible = "ralink,rt2880-gpio" },
407 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
409 +static struct platform_driver ralink_gpio_driver = {
410 + .probe = ralink_gpio_probe,
412 + .name = "rt2880_gpio",
413 + .owner = THIS_MODULE,
414 + .of_match_table = ralink_gpio_match,
418 +static int __init ralink_gpio_init(void)
420 + return platform_driver_register(&ralink_gpio_driver);
423 +subsys_initcall(ralink_gpio_init);