1 From 3af8b2904d2d4758f88bc96c7c9ecff4a708347f Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 14 Jul 2013 23:17:27 +0200
4 Subject: [PATCH 23/33] GPIO: MIPS: ralink: adds ralink gpio support
6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 arch/mips/Kconfig | 1 +
12 arch/mips/include/asm/mach-ralink/gpio.h | 24 +++
13 drivers/gpio/Kconfig | 6 +
14 drivers/gpio/Makefile | 1 +
15 drivers/gpio/gpio-ralink.c | 326 ++++++++++++++++++++++++++++++
16 5 files changed, 358 insertions(+)
17 create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
18 create mode 100644 drivers/gpio/gpio-ralink.c
20 --- a/arch/mips/Kconfig
21 +++ b/arch/mips/Kconfig
22 @@ -443,6 +443,7 @@ config RALINK
23 select SYS_HAS_EARLY_PRINTK
24 select HAVE_MACH_CLKDEV
26 + select ARCH_REQUIRE_GPIOLIB
29 bool "SGI IP22 (Indy/Indigo2)"
31 +++ b/arch/mips/include/asm/mach-ralink/gpio.h
34 + * Ralink SoC GPIO API support
36 + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
37 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
39 + * This program is free software; you can redistribute it and/or modify it
40 + * under the terms of the GNU General Public License version 2 as published
41 + * by the Free Software Foundation.
45 +#ifndef __ASM_MACH_RALINK_GPIO_H
46 +#define __ASM_MACH_RALINK_GPIO_H
48 +#define ARCH_NR_GPIOS 128
49 +#include <asm-generic/gpio.h>
51 +#define gpio_get_value __gpio_get_value
52 +#define gpio_set_value __gpio_set_value
53 +#define gpio_cansleep __gpio_cansleep
54 +#define gpio_to_irq __gpio_to_irq
56 +#endif /* __ASM_MACH_RALINK_GPIO_H */
57 --- a/drivers/gpio/Kconfig
58 +++ b/drivers/gpio/Kconfig
59 @@ -209,6 +209,12 @@ config GPIO_RCAR
61 Say yes here to support GPIO on Renesas R-Car SoCs.
64 + bool "Ralink GPIO Support"
67 + Say yes here to support the Ralink SoC GPIO device
69 config GPIO_SPEAR_SPICS
70 bool "ST SPEAr13xx SPI Chip Select as GPIO support"
72 --- a/drivers/gpio/Makefile
73 +++ b/drivers/gpio/Makefile
74 @@ -56,6 +56,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf85
75 obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
76 obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
77 obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
78 +obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
79 obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
80 obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
81 obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
83 +++ b/drivers/gpio/gpio-ralink.c
86 + * This program is free software; you can redistribute it and/or modify it
87 + * under the terms of the GNU General Public License version 2 as published
88 + * by the Free Software Foundation.
90 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
91 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
94 +#include <linux/module.h>
95 +#include <linux/io.h>
96 +#include <linux/gpio.h>
97 +#include <linux/spinlock.h>
98 +#include <linux/platform_device.h>
99 +#include <linux/of_irq.h>
100 +#include <linux/irqdomain.h>
101 +#include <linux/interrupt.h>
103 +enum ralink_gpio_reg {
117 +struct ralink_gpio_chip {
118 + struct gpio_chip chip;
119 + u8 regs[GPIO_REG_MAX];
122 + void __iomem *membase;
123 + struct irq_domain *domain;
131 +static struct irq_domain *irq_map[MAP_MAX];
132 +static int irq_map_count;
133 +static atomic_t irq_refcount = ATOMIC_INIT(0);
135 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
137 + struct ralink_gpio_chip *rg;
139 + rg = container_of(chip, struct ralink_gpio_chip, chip);
144 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
146 + iowrite32(val, rg->membase + rg->regs[reg]);
149 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
151 + return ioread32(rg->membase + rg->regs[reg]);
154 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
156 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
158 + rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
161 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
163 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
165 + return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
168 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
170 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
171 + unsigned long flags;
174 + spin_lock_irqsave(&rg->lock, flags);
175 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
177 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
178 + spin_unlock_irqrestore(&rg->lock, flags);
183 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
184 + unsigned offset, int value)
186 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
187 + unsigned long flags;
190 + spin_lock_irqsave(&rg->lock, flags);
191 + ralink_gpio_set(chip, offset, value);
192 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
194 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
195 + spin_unlock_irqrestore(&rg->lock, flags);
200 +static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
202 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
207 + ralink_gpio_direction_input(chip, pin);
209 + return irq_create_mapping(rg->domain, pin);
212 +static void ralink_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
216 + for (i = 0; i < irq_map_count; i++) {
217 + struct irq_domain *domain = irq_map[i];
218 + struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) domain->host_data;
219 + unsigned long pending = rt_gpio_r32(rg, GPIO_REG_INT);
222 + for_each_set_bit(bit, &pending, rg->chip.ngpio) {
223 + u32 map = irq_find_mapping(domain, bit);
224 + generic_handle_irq(map);
225 + rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
230 +static void ralink_gpio_irq_unmask(struct irq_data *d)
232 + struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
233 + u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
234 + unsigned long flags;
236 + spin_lock_irqsave(&rg->lock, flags);
237 + rt_gpio_w32(rg, GPIO_REG_RENA, val | (BIT(d->hwirq) & rg->rising));
238 + rt_gpio_w32(rg, GPIO_REG_FENA, val | (BIT(d->hwirq) & rg->falling));
239 + spin_unlock_irqrestore(&rg->lock, flags);
242 +static void ralink_gpio_irq_mask(struct irq_data *d)
244 + struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
245 + u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
246 + unsigned long flags;
248 + spin_lock_irqsave(&rg->lock, flags);
249 + rt_gpio_w32(rg, GPIO_REG_FENA, val & ~BIT(d->hwirq));
250 + rt_gpio_w32(rg, GPIO_REG_RENA, val & ~BIT(d->hwirq));
251 + spin_unlock_irqrestore(&rg->lock, flags);
254 +static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
256 + struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
257 + u32 mask = BIT(d->hwirq);
259 + if (type == IRQ_TYPE_PROBE) {
260 + if ((rg->rising | rg->falling) & mask)
263 + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_RISING;
266 + if (type & IRQ_TYPE_EDGE_RISING)
267 + rg->rising |= mask;
269 + rg->rising &= mask;
271 + if (type & IRQ_TYPE_EDGE_RISING)
272 + rg->falling |= mask;
274 + rg->falling &= mask;
279 +static struct irq_chip ralink_gpio_irq_chip = {
281 + .irq_unmask = ralink_gpio_irq_unmask,
282 + .irq_mask = ralink_gpio_irq_mask,
283 + .irq_mask_ack = ralink_gpio_irq_mask,
284 + .irq_set_type = ralink_gpio_irq_type,
287 +static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
289 + irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
290 + irq_set_handler_data(irq, d);
295 +static const struct irq_domain_ops irq_domain_ops = {
296 + .xlate = irq_domain_xlate_onecell,
300 +static void ralink_gpio_irq_init(struct device_node *np, struct ralink_gpio_chip *rg)
302 + if (irq_map_count >= MAP_MAX)
305 + rg->irq = irq_of_parse_and_map(np, 0);
309 + rg->domain = irq_domain_add_linear(np, rg->chip.ngpio, &irq_domain_ops, rg);
311 + dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
315 + irq_map[irq_map_count++] = rg->domain;
317 + rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
318 + rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
320 + if (!atomic_read(&irq_refcount))
321 + irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
322 + atomic_inc(&irq_refcount);
324 + dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
327 +static int ralink_gpio_probe(struct platform_device *pdev)
329 + struct device_node *np = pdev->dev.of_node;
330 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
331 + struct ralink_gpio_chip *rg;
332 + const __be32 *ngpio, *gpiobase;
335 + dev_err(&pdev->dev, "failed to find resource\n");
339 + rg = devm_kzalloc(&pdev->dev,
340 + sizeof(struct ralink_gpio_chip), GFP_KERNEL);
344 + rg->membase = devm_request_and_ioremap(&pdev->dev, res);
345 + if (!rg->membase) {
346 + dev_err(&pdev->dev, "cannot remap I/O memory region\n");
350 + if (of_property_read_u8_array(np, "ralink,register-map",
351 + rg->regs, GPIO_REG_MAX)) {
352 + dev_err(&pdev->dev, "failed to read register definition\n");
356 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
358 + dev_err(&pdev->dev, "failed to read number of pins\n");
362 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
364 + rg->chip.base = be32_to_cpu(*gpiobase);
366 + rg->chip.base = -1;
368 + spin_lock_init(&rg->lock);
370 + rg->chip.dev = &pdev->dev;
371 + rg->chip.label = dev_name(&pdev->dev);
372 + rg->chip.of_node = np;
373 + rg->chip.ngpio = be32_to_cpu(*ngpio);
374 + rg->chip.direction_input = ralink_gpio_direction_input;
375 + rg->chip.direction_output = ralink_gpio_direction_output;
376 + rg->chip.get = ralink_gpio_get;
377 + rg->chip.set = ralink_gpio_set;
378 + rg->chip.to_irq = ralink_gpio_to_irq;
380 + /* set polarity to low for all lines */
381 + rt_gpio_w32(rg, GPIO_REG_POL, 0);
383 + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
385 + ralink_gpio_irq_init(np, rg);
387 + return gpiochip_add(&rg->chip);
390 +static const struct of_device_id ralink_gpio_match[] = {
391 + { .compatible = "ralink,rt2880-gpio" },
394 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
396 +static struct platform_driver ralink_gpio_driver = {
397 + .probe = ralink_gpio_probe,
399 + .name = "rt2880_gpio",
400 + .owner = THIS_MODULE,
401 + .of_match_table = ralink_gpio_match,
405 +static int __init ralink_gpio_init(void)
407 + return platform_driver_register(&ralink_gpio_driver);
410 +subsys_initcall(ralink_gpio_init);