1 From 3af8b2904d2d4758f88bc96c7c9ecff4a708347f Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 14 Jul 2013 23:17:27 +0200
4 Subject: [PATCH 23/33] GPIO: MIPS: ralink: adds ralink gpio support
6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 arch/mips/Kconfig | 1 +
12 arch/mips/include/asm/mach-ralink/gpio.h | 24 +++
13 drivers/gpio/Kconfig | 6 +
14 drivers/gpio/Makefile | 1 +
15 drivers/gpio/gpio-ralink.c | 326 ++++++++++++++++++++++++++++++
16 5 files changed, 358 insertions(+)
17 create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
18 create mode 100644 drivers/gpio/gpio-ralink.c
20 Index: linux-3.10.3/arch/mips/Kconfig
21 ===================================================================
22 --- linux-3.10.3.orig/arch/mips/Kconfig 2013-07-27 10:24:36.376236698 +0200
23 +++ linux-3.10.3/arch/mips/Kconfig 2013-07-27 11:11:09.804861224 +0200
25 select SYS_HAS_EARLY_PRINTK
26 select HAVE_MACH_CLKDEV
28 + select ARCH_REQUIRE_GPIOLIB
31 bool "SGI IP22 (Indy/Indigo2)"
32 Index: linux-3.10.3/arch/mips/include/asm/mach-ralink/gpio.h
33 ===================================================================
34 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
35 +++ linux-3.10.3/arch/mips/include/asm/mach-ralink/gpio.h 2013-07-27 10:24:40.532236797 +0200
38 + * Ralink SoC GPIO API support
40 + * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
41 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
43 + * This program is free software; you can redistribute it and/or modify it
44 + * under the terms of the GNU General Public License version 2 as published
45 + * by the Free Software Foundation.
49 +#ifndef __ASM_MACH_RALINK_GPIO_H
50 +#define __ASM_MACH_RALINK_GPIO_H
52 +#define ARCH_NR_GPIOS 128
53 +#include <asm-generic/gpio.h>
55 +#define gpio_get_value __gpio_get_value
56 +#define gpio_set_value __gpio_set_value
57 +#define gpio_cansleep __gpio_cansleep
58 +#define gpio_to_irq __gpio_to_irq
60 +#endif /* __ASM_MACH_RALINK_GPIO_H */
61 Index: linux-3.10.3/drivers/gpio/Kconfig
62 ===================================================================
63 --- linux-3.10.3.orig/drivers/gpio/Kconfig 2013-07-26 00:16:45.000000000 +0200
64 +++ linux-3.10.3/drivers/gpio/Kconfig 2013-07-27 10:24:40.532236797 +0200
67 Say yes here to support GPIO on Renesas R-Car SoCs.
70 + bool "Ralink GPIO Support"
73 + Say yes here to support the Ralink SoC GPIO device
75 config GPIO_SPEAR_SPICS
76 bool "ST SPEAr13xx SPI Chip Select as GPIO support"
78 Index: linux-3.10.3/drivers/gpio/Makefile
79 ===================================================================
80 --- linux-3.10.3.orig/drivers/gpio/Makefile 2013-07-26 00:16:45.000000000 +0200
81 +++ linux-3.10.3/drivers/gpio/Makefile 2013-07-27 10:24:40.536236797 +0200
83 obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
84 obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
85 obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
86 +obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
87 obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
88 obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
89 obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
90 Index: linux-3.10.3/drivers/gpio/gpio-ralink.c
91 ===================================================================
92 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
93 +++ linux-3.10.3/drivers/gpio/gpio-ralink.c 2013-07-27 11:04:07.668851107 +0200
96 + * This program is free software; you can redistribute it and/or modify it
97 + * under the terms of the GNU General Public License version 2 as published
98 + * by the Free Software Foundation.
100 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
101 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
104 +#include <linux/module.h>
105 +#include <linux/io.h>
106 +#include <linux/gpio.h>
107 +#include <linux/spinlock.h>
108 +#include <linux/platform_device.h>
109 +#include <linux/of_irq.h>
110 +#include <linux/irqdomain.h>
111 +#include <linux/interrupt.h>
113 +enum ralink_gpio_reg {
127 +struct ralink_gpio_chip {
128 + struct gpio_chip chip;
129 + u8 regs[GPIO_REG_MAX];
132 + void __iomem *membase;
133 + struct irq_domain *domain;
141 +static struct irq_domain *irq_map[MAP_MAX];
142 +static int irq_map_count;
143 +static atomic_t irq_refcount = ATOMIC_INIT(0);
145 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
147 + struct ralink_gpio_chip *rg;
149 + rg = container_of(chip, struct ralink_gpio_chip, chip);
154 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
156 + iowrite32(val, rg->membase + rg->regs[reg]);
159 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
161 + return ioread32(rg->membase + rg->regs[reg]);
164 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
166 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
168 + rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
171 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
173 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
175 + return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
178 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
180 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
181 + unsigned long flags;
184 + spin_lock_irqsave(&rg->lock, flags);
185 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
187 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
188 + spin_unlock_irqrestore(&rg->lock, flags);
193 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
194 + unsigned offset, int value)
196 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
197 + unsigned long flags;
200 + spin_lock_irqsave(&rg->lock, flags);
201 + ralink_gpio_set(chip, offset, value);
202 + t = rt_gpio_r32(rg, GPIO_REG_DIR);
204 + rt_gpio_w32(rg, GPIO_REG_DIR, t);
205 + spin_unlock_irqrestore(&rg->lock, flags);
210 +static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
212 + struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
217 + return irq_create_mapping(rg->domain, pin);
220 +static void ralink_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
224 + for (i = 0; i < irq_map_count; i++) {
225 + struct irq_domain *domain = irq_map[i];
226 + struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) domain->host_data;
227 + unsigned long pending = rt_gpio_r32(rg, GPIO_REG_INT);
230 + for_each_set_bit(bit, &pending, rg->chip.ngpio) {
231 + u32 map = irq_find_mapping(domain, bit);
232 + generic_handle_irq(map);
233 + rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
238 +static void ralink_gpio_irq_unmask(struct irq_data *d)
240 + struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
241 + u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
242 + unsigned long flags;
244 + spin_lock_irqsave(&rg->lock, flags);
245 + rt_gpio_w32(rg, GPIO_REG_RENA, val | (BIT(d->hwirq) & rg->rising));
246 + rt_gpio_w32(rg, GPIO_REG_FENA, val | (BIT(d->hwirq) & rg->falling));
247 + spin_unlock_irqrestore(&rg->lock, flags);
250 +static void ralink_gpio_irq_mask(struct irq_data *d)
252 + struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
253 + u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
254 + unsigned long flags;
256 + spin_lock_irqsave(&rg->lock, flags);
257 + rt_gpio_w32(rg, GPIO_REG_FENA, val & ~BIT(d->hwirq));
258 + rt_gpio_w32(rg, GPIO_REG_RENA, val & ~BIT(d->hwirq));
259 + spin_unlock_irqrestore(&rg->lock, flags);
262 +static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
264 + struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
265 + u32 mask = BIT(d->hwirq);
267 + if (type == IRQ_TYPE_PROBE) {
268 + if ((rg->rising | rg->falling) & mask)
271 + type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_RISING;
274 + if (type & IRQ_TYPE_EDGE_RISING)
275 + rg->rising |= mask;
277 + rg->rising &= mask;
279 + if (type & IRQ_TYPE_EDGE_RISING)
280 + rg->falling |= mask;
282 + rg->falling &= mask;
287 +static struct irq_chip ralink_gpio_irq_chip = {
289 + .irq_unmask = ralink_gpio_irq_unmask,
290 + .irq_mask = ralink_gpio_irq_mask,
291 + .irq_mask_ack = ralink_gpio_irq_mask,
292 + .irq_set_type = ralink_gpio_irq_type,
295 +static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
297 + irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
298 + irq_set_handler_data(irq, d);
303 +static const struct irq_domain_ops irq_domain_ops = {
304 + .xlate = irq_domain_xlate_onecell,
308 +static void ralink_gpio_irq_init(struct device_node *np, struct ralink_gpio_chip *rg)
310 + if (irq_map_count >= MAP_MAX)
313 + rg->irq = irq_of_parse_and_map(np, 0);
317 + rg->domain = irq_domain_add_linear(np, rg->chip.ngpio, &irq_domain_ops, rg);
319 + dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
323 + irq_map[irq_map_count++] = rg->domain;
325 + rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
326 + rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
328 + if (!atomic_read(&irq_refcount))
329 + irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
330 + atomic_inc(&irq_refcount);
332 + dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
335 +static int ralink_gpio_probe(struct platform_device *pdev)
337 + struct device_node *np = pdev->dev.of_node;
338 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
339 + struct ralink_gpio_chip *rg;
340 + const __be32 *ngpio, *gpiobase;
343 + dev_err(&pdev->dev, "failed to find resource\n");
347 + rg = devm_kzalloc(&pdev->dev,
348 + sizeof(struct ralink_gpio_chip), GFP_KERNEL);
352 + rg->membase = devm_request_and_ioremap(&pdev->dev, res);
353 + if (!rg->membase) {
354 + dev_err(&pdev->dev, "cannot remap I/O memory region\n");
358 + if (of_property_read_u8_array(np, "ralink,register-map",
359 + rg->regs, GPIO_REG_MAX)) {
360 + dev_err(&pdev->dev, "failed to read register definition\n");
364 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
366 + dev_err(&pdev->dev, "failed to read number of pins\n");
370 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
372 + rg->chip.base = be32_to_cpu(*gpiobase);
374 + rg->chip.base = -1;
376 + spin_lock_init(&rg->lock);
378 + rg->chip.dev = &pdev->dev;
379 + rg->chip.label = dev_name(&pdev->dev);
380 + rg->chip.of_node = np;
381 + rg->chip.ngpio = be32_to_cpu(*ngpio);
382 + rg->chip.direction_input = ralink_gpio_direction_input;
383 + rg->chip.direction_output = ralink_gpio_direction_output;
384 + rg->chip.get = ralink_gpio_get;
385 + rg->chip.set = ralink_gpio_set;
386 + rg->chip.to_irq = ralink_gpio_to_irq;
388 + /* set polarity to low for all lines */
389 + rt_gpio_w32(rg, GPIO_REG_POL, 0);
391 + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
393 + ralink_gpio_irq_init(np, rg);
395 + return gpiochip_add(&rg->chip);
398 +static const struct of_device_id ralink_gpio_match[] = {
399 + { .compatible = "ralink,rt2880-gpio" },
402 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
404 +static struct platform_driver ralink_gpio_driver = {
405 + .probe = ralink_gpio_probe,
407 + .name = "rt2880_gpio",
408 + .owner = THIS_MODULE,
409 + .of_match_table = ralink_gpio_match,
413 +static int __init ralink_gpio_init(void)
415 + return platform_driver_register(&ralink_gpio_driver);
418 +subsys_initcall(ralink_gpio_init);