1 From ad11aedcc16574c0b3d3f5e40c67227d1846b94e Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Apr 2013 23:20:03 +0200
4 Subject: [PATCH 16/33] NET: MIPS: add ralink SoC ethernet driver
6 Add support for Ralink FE and ESW.
8 Signed-off-by: John Crispin <blogic@openwrt.org>
10 .../include/asm/mach-ralink/rt305x_esw_platform.h | 27 +
11 arch/mips/ralink/rt305x.c | 1 +
12 drivers/net/ethernet/Kconfig | 1 +
13 drivers/net/ethernet/Makefile | 1 +
14 drivers/net/ethernet/ralink/Kconfig | 31 +
15 drivers/net/ethernet/ralink/Makefile | 18 +
16 drivers/net/ethernet/ralink/esw_rt3052.c | 1463 ++++++++++++++++++++
17 drivers/net/ethernet/ralink/esw_rt3052.h | 32 +
18 drivers/net/ethernet/ralink/gsw_mt7620a.c | 1027 ++++++++++++++
19 drivers/net/ethernet/ralink/gsw_mt7620a.h | 29 +
20 drivers/net/ethernet/ralink/mdio.c | 245 ++++
21 drivers/net/ethernet/ralink/mdio.h | 29 +
22 drivers/net/ethernet/ralink/mdio_rt2880.c | 232 ++++
23 drivers/net/ethernet/ralink/mdio_rt2880.h | 26 +
24 drivers/net/ethernet/ralink/ralink_soc_eth.c | 735 ++++++++++
25 drivers/net/ethernet/ralink/ralink_soc_eth.h | 374 +++++
26 drivers/net/ethernet/ralink/soc_mt7620.c | 111 ++
27 drivers/net/ethernet/ralink/soc_rt2880.c | 51 +
28 drivers/net/ethernet/ralink/soc_rt305x.c | 113 ++
29 drivers/net/ethernet/ralink/soc_rt3883.c | 60 +
30 20 files changed, 4606 insertions(+)
31 create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
32 create mode 100644 drivers/net/ethernet/ralink/Kconfig
33 create mode 100644 drivers/net/ethernet/ralink/Makefile
34 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
35 create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
36 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
37 create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
38 create mode 100644 drivers/net/ethernet/ralink/mdio.c
39 create mode 100644 drivers/net/ethernet/ralink/mdio.h
40 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
41 create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
42 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
43 create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
44 create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
45 create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
46 create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
47 create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
50 +++ b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
53 + * Ralink RT305x SoC platform device registration
55 + * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
57 + * This program is free software; you can redistribute it and/or modify it
58 + * under the terms of the GNU General Public License version 2 as published
59 + * by the Free Software Foundation.
62 +#ifndef _RT305X_ESW_PLATFORM_H
63 +#define _RT305X_ESW_PLATFORM_H
66 + RT305X_ESW_VLAN_CONFIG_NONE = 0,
67 + RT305X_ESW_VLAN_CONFIG_LLLLW,
68 + RT305X_ESW_VLAN_CONFIG_WLLLL,
71 +struct rt305x_esw_platform_data
74 + u32 reg_initval_fct2;
75 + u32 reg_initval_fpa2;
78 +#endif /* _RT305X_ESW_PLATFORM_H */
79 --- a/arch/mips/ralink/rt305x.c
80 +++ b/arch/mips/ralink/rt305x.c
81 @@ -221,6 +221,7 @@ void __init ralink_clk_init(void)
84 ralink_clk_add("cpu", cpu_rate);
85 + ralink_clk_add("sys", sys_rate);
86 ralink_clk_add("10000b00.spi", sys_rate);
87 ralink_clk_add("10000100.timer", wdt_rate);
88 ralink_clk_add("10000120.watchdog", wdt_rate);
89 --- a/drivers/net/ethernet/Kconfig
90 +++ b/drivers/net/ethernet/Kconfig
91 @@ -135,6 +135,7 @@ config ETHOC
92 source "drivers/net/ethernet/packetengines/Kconfig"
93 source "drivers/net/ethernet/pasemi/Kconfig"
94 source "drivers/net/ethernet/qlogic/Kconfig"
95 +source "drivers/net/ethernet/ralink/Kconfig"
96 source "drivers/net/ethernet/realtek/Kconfig"
97 source "drivers/net/ethernet/renesas/Kconfig"
98 source "drivers/net/ethernet/rdc/Kconfig"
99 --- a/drivers/net/ethernet/Makefile
100 +++ b/drivers/net/ethernet/Makefile
101 @@ -53,6 +53,7 @@ obj-$(CONFIG_ETHOC) += ethoc.o
102 obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
103 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
104 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
105 +obj-$(CONFIG_NET_RALINK) += ralink/
106 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
107 obj-$(CONFIG_SH_ETH) += renesas/
108 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
110 +++ b/drivers/net/ethernet/ralink/Kconfig
113 + tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
116 + This driver supports the ethernet mac inside the ralink wisocs
120 +config NET_RALINK_MDIO
121 + def_bool NET_RALINK
122 + depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
125 +config NET_RALINK_MDIO_RT2880
126 + def_bool NET_RALINK
127 + depends on (SOC_RT288X || SOC_RT3883)
128 + select NET_RALINK_MDIO
130 +config NET_RALINK_ESW_RT3052
131 + def_bool NET_RALINK
132 + depends on SOC_RT305X
136 +config NET_RALINK_GSW_MT7620
137 + def_bool NET_RALINK
138 + depends on SOC_MT7620
139 + select NET_RALINK_MDIO
144 +++ b/drivers/net/ethernet/ralink/Makefile
147 +# Makefile for the Ralink SoCs built-in ethernet macs
150 +ralink-eth-y += ralink_soc_eth.o
152 +ralink-eth-$(CONFIG_NET_RALINK_MDIO) += mdio.o
153 +ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880) += mdio_rt2880.o
155 +ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052) += esw_rt3052.o
156 +ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620) += gsw_mt7620a.o mt7530.o
158 +ralink-eth-$(CONFIG_SOC_RT288X) += soc_rt2880.o
159 +ralink-eth-$(CONFIG_SOC_RT305X) += soc_rt305x.o
160 +ralink-eth-$(CONFIG_SOC_RT3883) += soc_rt3883.o
161 +ralink-eth-$(CONFIG_SOC_MT7620) += soc_mt7620.o
163 +obj-$(CONFIG_NET_RALINK) += ralink-eth.o
165 +++ b/drivers/net/ethernet/ralink/esw_rt3052.c
168 + * This program is free software; you can redistribute it and/or modify
169 + * it under the terms of the GNU General Public License as published by
170 + * the Free Software Foundation; version 2 of the License
172 + * This program is distributed in the hope that it will be useful,
173 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
174 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
175 + * GNU General Public License for more details.
177 + * You should have received a copy of the GNU General Public License
178 + * along with this program; if not, write to the Free Software
179 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
181 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
184 +#include <linux/module.h>
185 +#include <linux/kernel.h>
186 +#include <linux/types.h>
187 +#include <linux/dma-mapping.h>
188 +#include <linux/init.h>
189 +#include <linux/skbuff.h>
190 +#include <linux/etherdevice.h>
191 +#include <linux/ethtool.h>
192 +#include <linux/platform_device.h>
193 +#include <linux/of_device.h>
194 +#include <linux/clk.h>
195 +#include <linux/of_net.h>
196 +#include <linux/of_mdio.h>
198 +#include <asm/mach-ralink/ralink_regs.h>
200 +#include "ralink_soc_eth.h"
202 +#include <linux/ioport.h>
203 +#include <linux/switch.h>
204 +#include <linux/mii.h>
206 +#include <ralink_regs.h>
207 +#include <asm/mach-ralink/rt305x.h>
208 +#include <asm/mach-ralink/rt305x_esw_platform.h>
211 + * HW limitations for this switch:
212 + * - No large frame support (PKT_MAX_LEN at most 1536)
213 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
214 + * though this might be possible using the undocumented PPE.
217 +#define RT305X_ESW_REG_ISR 0x00
218 +#define RT305X_ESW_REG_IMR 0x04
219 +#define RT305X_ESW_REG_FCT0 0x08
220 +#define RT305X_ESW_REG_PFC1 0x14
221 +#define RT305X_ESW_REG_ATS 0x24
222 +#define RT305X_ESW_REG_ATS0 0x28
223 +#define RT305X_ESW_REG_ATS1 0x2c
224 +#define RT305X_ESW_REG_ATS2 0x30
225 +#define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
226 +#define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
227 +#define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
228 +#define RT305X_ESW_REG_POA 0x80
229 +#define RT305X_ESW_REG_FPA 0x84
230 +#define RT305X_ESW_REG_SOCPC 0x8c
231 +#define RT305X_ESW_REG_POC0 0x90
232 +#define RT305X_ESW_REG_POC1 0x94
233 +#define RT305X_ESW_REG_POC2 0x98
234 +#define RT305X_ESW_REG_SGC 0x9c
235 +#define RT305X_ESW_REG_STRT 0xa0
236 +#define RT305X_ESW_REG_PCR0 0xc0
237 +#define RT305X_ESW_REG_PCR1 0xc4
238 +#define RT305X_ESW_REG_FPA2 0xc8
239 +#define RT305X_ESW_REG_FCT2 0xcc
240 +#define RT305X_ESW_REG_SGC2 0xe4
241 +#define RT305X_ESW_REG_P0LED 0xa4
242 +#define RT305X_ESW_REG_P1LED 0xa8
243 +#define RT305X_ESW_REG_P2LED 0xac
244 +#define RT305X_ESW_REG_P3LED 0xb0
245 +#define RT305X_ESW_REG_P4LED 0xb4
246 +#define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
247 +#define RT305X_ESW_REG_P1PC 0xec
248 +#define RT305X_ESW_REG_P2PC 0xf0
249 +#define RT305X_ESW_REG_P3PC 0xf4
250 +#define RT305X_ESW_REG_P4PC 0xf8
251 +#define RT305X_ESW_REG_P5PC 0xfc
253 +#define RT305X_ESW_LED_LINK 0
254 +#define RT305X_ESW_LED_100M 1
255 +#define RT305X_ESW_LED_DUPLEX 2
256 +#define RT305X_ESW_LED_ACTIVITY 3
257 +#define RT305X_ESW_LED_COLLISION 4
258 +#define RT305X_ESW_LED_LINKACT 5
259 +#define RT305X_ESW_LED_DUPLCOLL 6
260 +#define RT305X_ESW_LED_10MACT 7
261 +#define RT305X_ESW_LED_100MACT 8
262 +/* Additional led states not in datasheet: */
263 +#define RT305X_ESW_LED_BLINK 10
264 +#define RT305X_ESW_LED_ON 12
266 +#define RT305X_ESW_LINK_S 25
267 +#define RT305X_ESW_DUPLEX_S 9
268 +#define RT305X_ESW_SPD_S 0
270 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
271 +#define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
272 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
274 +#define RT305X_ESW_PCR1_WT_DONE BIT(0)
276 +#define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
277 +#define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
279 +#define RT305X_ESW_PVIDC_PVID_M 0xfff
280 +#define RT305X_ESW_PVIDC_PVID_S 12
282 +#define RT305X_ESW_VLANI_VID_M 0xfff
283 +#define RT305X_ESW_VLANI_VID_S 12
285 +#define RT305X_ESW_VMSC_MSC_M 0xff
286 +#define RT305X_ESW_VMSC_MSC_S 8
288 +#define RT305X_ESW_SOCPC_DISUN2CPU_S 0
289 +#define RT305X_ESW_SOCPC_DISMC2CPU_S 8
290 +#define RT305X_ESW_SOCPC_DISBC2CPU_S 16
291 +#define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
293 +#define RT305X_ESW_POC0_EN_BP_S 0
294 +#define RT305X_ESW_POC0_EN_FC_S 8
295 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
296 +#define RT305X_ESW_POC0_DIS_PORT_M 0x7f
297 +#define RT305X_ESW_POC0_DIS_PORT_S 23
299 +#define RT305X_ESW_POC2_UNTAG_EN_M 0xff
300 +#define RT305X_ESW_POC2_UNTAG_EN_S 0
301 +#define RT305X_ESW_POC2_ENAGING_S 8
302 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
304 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
305 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
306 +#define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
307 +#define RT305X_ESW_SGC2_LAN_PMAP_S 24
309 +#define RT305X_ESW_PFC1_EN_VLAN_M 0xff
310 +#define RT305X_ESW_PFC1_EN_VLAN_S 16
311 +#define RT305X_ESW_PFC1_EN_TOS_S 24
313 +#define RT305X_ESW_VLAN_NONE 0xfff
315 +#define RT305X_ESW_GSC_BC_STROM_MASK 0x3
316 +#define RT305X_ESW_GSC_BC_STROM_SHIFT 4
318 +#define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
319 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
321 +#define RT305X_ESW_POA_LINK_MASK 0x1f
322 +#define RT305X_ESW_POA_LINK_SHIFT 25
324 +#define RT305X_ESW_PORT_ST_CHG BIT(26)
325 +#define RT305X_ESW_PORT0 0
326 +#define RT305X_ESW_PORT1 1
327 +#define RT305X_ESW_PORT2 2
328 +#define RT305X_ESW_PORT3 3
329 +#define RT305X_ESW_PORT4 4
330 +#define RT305X_ESW_PORT5 5
331 +#define RT305X_ESW_PORT6 6
333 +#define RT305X_ESW_PORTS_NONE 0
335 +#define RT305X_ESW_PMAP_LLLLLL 0x3f
336 +#define RT305X_ESW_PMAP_LLLLWL 0x2f
337 +#define RT305X_ESW_PMAP_WLLLLL 0x3e
339 +#define RT305X_ESW_PORTS_INTERNAL \
340 + (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
341 + BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
342 + BIT(RT305X_ESW_PORT4))
344 +#define RT305X_ESW_PORTS_NOCPU \
345 + (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
347 +#define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
349 +#define RT305X_ESW_PORTS_ALL \
350 + (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
352 +#define RT305X_ESW_NUM_VLANS 16
353 +#define RT305X_ESW_NUM_VIDS 4096
354 +#define RT305X_ESW_NUM_PORTS 7
355 +#define RT305X_ESW_NUM_LANWAN 6
356 +#define RT305X_ESW_NUM_LEDS 5
358 +#define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
359 +#define RT5350_EWS_REG_LED_POLARITY 0x168
360 +#define RT5350_RESET_EPHY BIT(24)
361 +#define SYSC_REG_RESET_CTRL 0x34
364 + /* Global attributes. */
365 + RT305X_ESW_ATTR_ENABLE_VLAN,
366 + RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
367 + RT305X_ESW_ATTR_BC_STATUS,
368 + RT305X_ESW_ATTR_LED_FREQ,
369 + /* Port attributes. */
370 + RT305X_ESW_ATTR_PORT_DISABLE,
371 + RT305X_ESW_ATTR_PORT_DOUBLETAG,
372 + RT305X_ESW_ATTR_PORT_UNTAG,
373 + RT305X_ESW_ATTR_PORT_LED,
374 + RT305X_ESW_ATTR_PORT_LAN,
375 + RT305X_ESW_ATTR_PORT_RECV_BAD,
376 + RT305X_ESW_ATTR_PORT_RECV_GOOD,
377 + RT5350_ESW_ATTR_PORT_TR_BAD,
378 + RT5350_ESW_ATTR_PORT_TR_GOOD,
395 + struct device *dev;
396 + void __iomem *base;
398 + const struct rt305x_esw_platform_data *pdata;
399 + /* Protects against concurrent register rmw operations. */
400 + spinlock_t reg_rw_lock;
402 + unsigned char port_map;
403 + unsigned int reg_initval_fct2;
404 + unsigned int reg_initval_fpa2;
405 + unsigned int reg_led_polarity;
408 + struct switch_dev swdev;
409 + bool global_vlan_enable;
410 + bool alt_vlan_disable;
411 + int bc_storm_protect;
413 + struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
414 + struct esw_port ports[RT305X_ESW_NUM_PORTS];
418 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
420 + __raw_writel(val, esw->base + reg);
423 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
425 + return __raw_readl(esw->base + reg);
428 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
433 + t = __raw_readl(esw->base + reg) & ~mask;
434 + __raw_writel(t | val, esw->base + reg);
437 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
440 + unsigned long flags;
442 + spin_lock_irqsave(&esw->reg_rw_lock, flags);
443 + esw_rmw_raw(esw, reg, mask, val);
444 + spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
447 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
450 + unsigned long t_start = jiffies;
454 + if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
455 + RT305X_ESW_PCR1_WT_DONE))
457 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
463 + write_data &= 0xffff;
465 + (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
466 + (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
467 + (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
468 + RT305X_ESW_REG_PCR0);
472 + if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
473 + RT305X_ESW_PCR1_WT_DONE)
476 + if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
483 + printk(KERN_ERR "ramips_eth: MDIO timeout\n");
487 +static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
492 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
493 + val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
494 + val = (val >> s) & RT305X_ESW_VLANI_VID_M;
499 +static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
503 + s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
505 + RT305X_ESW_REG_VLANI(vlan / 2),
506 + RT305X_ESW_VLANI_VID_M << s,
507 + (vid & RT305X_ESW_VLANI_VID_M) << s);
510 +static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
514 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
515 + val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
516 + return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
519 +static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
523 + s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
525 + RT305X_ESW_REG_PVIDC(port / 2),
526 + RT305X_ESW_PVIDC_PVID_M << s,
527 + (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
530 +static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
534 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
535 + val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
536 + val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
541 +static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
545 + s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
547 + RT305X_ESW_REG_VMSC(vlan / 4),
548 + RT305X_ESW_VMSC_MSC_M << s,
549 + (msc & RT305X_ESW_VMSC_MSC_M) << s);
552 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
555 + reg = esw_r32(esw, RT305X_ESW_REG_POC0);
556 + return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
557 + RT305X_ESW_POC0_DIS_PORT_M;
560 +static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
563 + unsigned enable_mask;
567 + old_mask = esw_get_port_disable(esw);
568 + changed = old_mask ^ disable_mask;
569 + enable_mask = old_mask & disable_mask;
571 + /* enable before writing to MII */
572 + esw_rmw(esw, RT305X_ESW_REG_POC0,
573 + (RT305X_ESW_POC0_DIS_PORT_M <<
574 + RT305X_ESW_POC0_DIS_PORT_S),
575 + enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
577 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
578 + if (!(changed & (1 << i)))
580 + if (disable_mask & (1 << i)) {
582 + rt305x_mii_write(esw, i, MII_BMCR,
586 + rt305x_mii_write(esw, i, MII_BMCR,
594 + /* disable after writing to MII */
595 + esw_rmw(esw, RT305X_ESW_REG_POC0,
596 + (RT305X_ESW_POC0_DIS_PORT_M <<
597 + RT305X_ESW_POC0_DIS_PORT_S),
598 + disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
601 +static void esw_set_gsc(struct rt305x_esw *esw)
603 + esw_rmw(esw, RT305X_ESW_REG_SGC,
604 + RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
605 + esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
606 + esw_rmw(esw, RT305X_ESW_REG_SGC,
607 + RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
608 + esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
611 +static int esw_apply_config(struct switch_dev *dev);
613 +static void esw_hw_init(struct rt305x_esw *esw)
616 + u8 port_disable = 0;
617 + u8 port_map = RT305X_ESW_PMAP_LLLLLL;
619 + /* vodoo from original driver */
620 + esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
621 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
622 + /* Port priority 1 for all ports, vlan enabled. */
623 + esw_w32(esw, 0x00005555 |
624 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
625 + RT305X_ESW_REG_PFC1);
627 + /* Enable Back Pressure, and Flow Control */
629 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
630 + (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
631 + RT305X_ESW_REG_POC0);
633 + /* Enable Aging, and VLAN TAG removal */
635 + ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
636 + (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
637 + RT305X_ESW_REG_POC2);
639 + if (esw->reg_initval_fct2)
640 + esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
642 + esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
645 + * 300s aging timer, max packet len 1536, broadcast storm prevention
646 + * disabled, disable collision abort, mac xor48 hash, 10 packet back
647 + * pressure jam, GMII disable was_transmit, back pressure disabled,
648 + * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
651 + esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
653 + /* Setup SoC Port control register */
655 + (RT305X_ESW_SOCPC_CRC_PADDING |
656 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
657 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
658 + (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
659 + RT305X_ESW_REG_SOCPC);
661 + if (esw->reg_initval_fpa2)
662 + esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
664 + esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
665 + esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
667 + /* Force Link/Activity on ports */
668 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
669 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
670 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
671 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
672 + esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
674 + /* Copy disabled port configuration from bootloader setup */
675 + port_disable = esw_get_port_disable(esw);
676 + for (i = 0; i < 6; i++)
677 + esw->ports[i].disable = (port_disable & (1 << i)) != 0;
679 + if (soc_is_rt3352()) {
681 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
682 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
683 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
685 + rt305x_mii_write(esw, 0, 31, 0x8000);
686 + for (i = 0; i < 5; i++) {
687 + if (esw->ports[i].disable) {
688 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
690 + rt305x_mii_write(esw, i, MII_BMCR,
695 + /* TX10 waveform coefficient LSB=0 disable PHY */
696 + rt305x_mii_write(esw, i, 26, 0x1601);
697 + /* TX100/TX10 AD/DA current bias */
698 + rt305x_mii_write(esw, i, 29, 0x7016);
699 + /* TX100 slew rate control */
700 + rt305x_mii_write(esw, i, 30, 0x0038);
703 + /* select global register */
704 + rt305x_mii_write(esw, 0, 31, 0x0);
705 + /* enlarge agcsel threshold 3 and threshold 2 */
706 + rt305x_mii_write(esw, 0, 1, 0x4a40);
707 + /* enlarge agcsel threshold 5 and threshold 4 */
708 + rt305x_mii_write(esw, 0, 2, 0x6254);
709 + /* enlarge agcsel threshold */
710 + rt305x_mii_write(esw, 0, 3, 0xa17f);
711 + rt305x_mii_write(esw, 0,12, 0x7eaa);
712 + /* longer TP_IDL tail length */
713 + rt305x_mii_write(esw, 0, 14, 0x65);
714 + /* increased squelch pulse count threshold. */
715 + rt305x_mii_write(esw, 0, 16, 0x0684);
716 + /* set TX10 signal amplitude threshold to minimum */
717 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
718 + /* set squelch amplitude to higher threshold */
719 + rt305x_mii_write(esw, 0, 18, 0x40ba);
720 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
721 + rt305x_mii_write(esw, 0, 22, 0x253f);
722 + /* set PLL/Receive bias current are calibrated */
723 + rt305x_mii_write(esw, 0, 27, 0x2fda);
724 + /* change PLL/Receive bias current to internal(RT3350) */
725 + rt305x_mii_write(esw, 0, 28, 0xc410);
726 + /* change PLL bias current to internal(RT3052_MP3) */
727 + rt305x_mii_write(esw, 0, 29, 0x598b);
728 + /* select local register */
729 + rt305x_mii_write(esw, 0, 31, 0x8000);
730 + } else if (soc_is_rt5350()) {
732 + u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
733 + rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
734 + rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
736 + /* set the led polarity */
737 + esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
739 + /* local registers */
740 + rt305x_mii_write(esw, 0, 31, 0x8000);
741 + for (i = 0; i < 5; i++) {
742 + if (esw->ports[i].disable) {
743 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
745 + rt305x_mii_write(esw, i, MII_BMCR,
750 + /* TX10 waveform coefficient LSB=0 disable PHY */
751 + rt305x_mii_write(esw, i, 26, 0x1601);
752 + /* TX100/TX10 AD/DA current bias */
753 + rt305x_mii_write(esw, i, 29, 0x7015);
754 + /* TX100 slew rate control */
755 + rt305x_mii_write(esw, i, 30, 0x0038);
758 + /* global registers */
759 + rt305x_mii_write(esw, 0, 31, 0x0);
760 + /* enlarge agcsel threshold 3 and threshold 2 */
761 + rt305x_mii_write(esw, 0, 1, 0x4a40);
762 + /* enlarge agcsel threshold 5 and threshold 4 */
763 + rt305x_mii_write(esw, 0, 2, 0x6254);
764 + /* enlarge agcsel threshold 6 */
765 + rt305x_mii_write(esw, 0, 3, 0xa17f);
766 + rt305x_mii_write(esw, 0, 12, 0x7eaa);
767 + /* longer TP_IDL tail length */
768 + rt305x_mii_write(esw, 0, 14, 0x65);
769 + /* increased squelch pulse count threshold. */
770 + rt305x_mii_write(esw, 0, 16, 0x0684);
771 + /* set TX10 signal amplitude threshold to minimum */
772 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
773 + /* set squelch amplitude to higher threshold */
774 + rt305x_mii_write(esw, 0, 18, 0x40ba);
775 + /* tune TP_IDL tail and head waveform, enable power down slew rate control */
776 + rt305x_mii_write(esw, 0, 22, 0x253f);
777 + /* set PLL/Receive bias current are calibrated */
778 + rt305x_mii_write(esw, 0, 27, 0x2fda);
779 + /* change PLL/Receive bias current to internal(RT3350) */
780 + rt305x_mii_write(esw, 0, 28, 0xc410);
781 + /* change PLL bias current to internal(RT3052_MP3) */
782 + rt305x_mii_write(esw, 0, 29, 0x598b);
783 + /* select local register */
784 + rt305x_mii_write(esw, 0, 31, 0x8000);
786 + rt305x_mii_write(esw, 0, 31, 0x8000);
787 + for (i = 0; i < 5; i++) {
788 + if (esw->ports[i].disable) {
789 + rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
791 + rt305x_mii_write(esw, i, MII_BMCR,
796 + /* TX10 waveform coefficient */
797 + rt305x_mii_write(esw, i, 26, 0x1601);
798 + /* TX100/TX10 AD/DA current bias */
799 + rt305x_mii_write(esw, i, 29, 0x7058);
800 + /* TX100 slew rate control */
801 + rt305x_mii_write(esw, i, 30, 0x0018);
805 + /* select global register */
806 + rt305x_mii_write(esw, 0, 31, 0x0);
807 + /* tune TP_IDL tail and head waveform */
808 + rt305x_mii_write(esw, 0, 22, 0x052f);
809 + /* set TX10 signal amplitude threshold to minimum */
810 + rt305x_mii_write(esw, 0, 17, 0x0fe0);
811 + /* set squelch amplitude to higher threshold */
812 + rt305x_mii_write(esw, 0, 18, 0x40ba);
813 + /* longer TP_IDL tail length */
814 + rt305x_mii_write(esw, 0, 14, 0x65);
815 + /* select local register */
816 + rt305x_mii_write(esw, 0, 31, 0x8000);
820 + port_map = esw->port_map;
822 + port_map = RT305X_ESW_PMAP_LLLLLL;
825 + * Unused HW feature, but still nice to be consistent here...
826 + * This is also exported to userspace ('lan' attribute) so it's
827 + * conveniently usable to decide which ports go into the wan vlan by
830 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
831 + RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
832 + port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
834 + /* make the switch leds blink */
835 + for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
836 + esw->ports[i].led = 0x05;
838 + /* Apply the empty config. */
839 + esw_apply_config(&esw->swdev);
841 + /* Only unmask the port change interrupt */
842 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
845 +static irqreturn_t esw_interrupt(int irq, void *_esw)
847 + struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
850 + status = esw_r32(esw, RT305X_ESW_REG_ISR);
851 + if (status & RT305X_ESW_PORT_ST_CHG) {
852 + u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
853 + link >>= RT305X_ESW_POA_LINK_SHIFT;
854 + link &= RT305X_ESW_POA_LINK_MASK;
855 + dev_info(esw->dev, "link changed 0x%02X\n", link);
857 + esw_w32(esw, status, RT305X_ESW_REG_ISR);
859 + return IRQ_HANDLED;
862 +static int esw_apply_config(struct switch_dev *dev)
864 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
871 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
873 + if (esw->global_vlan_enable) {
874 + vid = esw->vlans[i].vid;
875 + vmsc = esw->vlans[i].ports;
877 + vid = RT305X_ESW_VLAN_NONE;
878 + vmsc = RT305X_ESW_PORTS_NONE;
880 + esw_set_vlan_id(esw, i, vid);
881 + esw_set_vmsc(esw, i, vmsc);
884 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
886 + disable |= esw->ports[i].disable << i;
887 + if (esw->global_vlan_enable) {
888 + doubletag |= esw->ports[i].doubletag << i;
890 + untag |= esw->ports[i].untag << i;
891 + pvid = esw->ports[i].pvid;
893 + int x = esw->alt_vlan_disable ? 0 : 1;
894 + doubletag |= x << i;
899 + esw_set_pvid(esw, i, pvid);
900 + if (i < RT305X_ESW_NUM_LEDS)
901 + esw_w32(esw, esw->ports[i].led,
902 + RT305X_ESW_REG_P0LED + 4*i);
906 + esw_set_port_disable(esw, disable);
907 + esw_rmw(esw, RT305X_ESW_REG_SGC2,
908 + (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
909 + RT305X_ESW_SGC2_DOUBLE_TAG_S),
910 + doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
911 + esw_rmw(esw, RT305X_ESW_REG_PFC1,
912 + RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
913 + en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
914 + esw_rmw(esw, RT305X_ESW_REG_POC2,
915 + RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
916 + untag << RT305X_ESW_POC2_UNTAG_EN_S);
918 + if (!esw->global_vlan_enable) {
920 + * Still need to put all ports into vlan 0 or they'll be
922 + * NOTE: vlan 0 is special, no vlan tag is prepended
924 + esw_set_vlan_id(esw, 0, 0);
925 + esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
931 +static int esw_reset_switch(struct switch_dev *dev)
933 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
935 + esw->global_vlan_enable = 0;
936 + memset(esw->ports, 0, sizeof(esw->ports));
937 + memset(esw->vlans, 0, sizeof(esw->vlans));
943 +static int esw_get_vlan_enable(struct switch_dev *dev,
944 + const struct switch_attr *attr,
945 + struct switch_val *val)
947 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
949 + val->value.i = esw->global_vlan_enable;
954 +static int esw_set_vlan_enable(struct switch_dev *dev,
955 + const struct switch_attr *attr,
956 + struct switch_val *val)
958 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
960 + esw->global_vlan_enable = val->value.i != 0;
965 +static int esw_get_alt_vlan_disable(struct switch_dev *dev,
966 + const struct switch_attr *attr,
967 + struct switch_val *val)
969 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
971 + val->value.i = esw->alt_vlan_disable;
976 +static int esw_set_alt_vlan_disable(struct switch_dev *dev,
977 + const struct switch_attr *attr,
978 + struct switch_val *val)
980 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
982 + esw->alt_vlan_disable = val->value.i != 0;
988 +rt305x_esw_set_bc_status(struct switch_dev *dev,
989 + const struct switch_attr *attr,
990 + struct switch_val *val)
992 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
994 + esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
1000 +rt305x_esw_get_bc_status(struct switch_dev *dev,
1001 + const struct switch_attr *attr,
1002 + struct switch_val *val)
1004 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1006 + val->value.i = esw->bc_storm_protect;
1012 +rt305x_esw_set_led_freq(struct switch_dev *dev,
1013 + const struct switch_attr *attr,
1014 + struct switch_val *val)
1016 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1018 + esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
1024 +rt305x_esw_get_led_freq(struct switch_dev *dev,
1025 + const struct switch_attr *attr,
1026 + struct switch_val *val)
1028 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1030 + val->value.i = esw->led_frequency;
1035 +static int esw_get_port_link(struct switch_dev *dev,
1037 + struct switch_port_link *link)
1039 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1042 + if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
1045 + poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
1047 + link->link = (poa >> RT305X_ESW_LINK_S) & 1;
1048 + link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
1049 + if (port < RT305X_ESW_NUM_LEDS) {
1050 + speed = (poa >> RT305X_ESW_SPD_S) & 1;
1052 + if (port == RT305X_ESW_NUM_PORTS - 1)
1054 + speed = (poa >> RT305X_ESW_SPD_S) & 3;
1058 + link->speed = SWITCH_PORT_SPEED_10;
1061 + link->speed = SWITCH_PORT_SPEED_100;
1064 + case 3: /* forced gige speed can be 2 or 3 */
1065 + link->speed = SWITCH_PORT_SPEED_1000;
1068 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1075 +static int esw_get_port_bool(struct switch_dev *dev,
1076 + const struct switch_attr *attr,
1077 + struct switch_val *val)
1079 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1080 + int idx = val->port_vlan;
1081 + u32 x, reg, shift;
1083 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1086 + switch (attr->id) {
1087 + case RT305X_ESW_ATTR_PORT_DISABLE:
1088 + reg = RT305X_ESW_REG_POC0;
1089 + shift = RT305X_ESW_POC0_DIS_PORT_S;
1091 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1092 + reg = RT305X_ESW_REG_SGC2;
1093 + shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1095 + case RT305X_ESW_ATTR_PORT_UNTAG:
1096 + reg = RT305X_ESW_REG_POC2;
1097 + shift = RT305X_ESW_POC2_UNTAG_EN_S;
1099 + case RT305X_ESW_ATTR_PORT_LAN:
1100 + reg = RT305X_ESW_REG_SGC2;
1101 + shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1102 + if (idx >= RT305X_ESW_NUM_LANWAN)
1109 + x = esw_r32(esw, reg);
1110 + val->value.i = (x >> (idx + shift)) & 1;
1115 +static int esw_set_port_bool(struct switch_dev *dev,
1116 + const struct switch_attr *attr,
1117 + struct switch_val *val)
1119 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1120 + int idx = val->port_vlan;
1122 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1123 + val->value.i < 0 || val->value.i > 1)
1126 + switch (attr->id) {
1127 + case RT305X_ESW_ATTR_PORT_DISABLE:
1128 + esw->ports[idx].disable = val->value.i;
1130 + case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1131 + esw->ports[idx].doubletag = val->value.i;
1133 + case RT305X_ESW_ATTR_PORT_UNTAG:
1134 + esw->ports[idx].untag = val->value.i;
1143 +static int esw_get_port_recv_badgood(struct switch_dev *dev,
1144 + const struct switch_attr *attr,
1145 + struct switch_val *val)
1147 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1148 + int idx = val->port_vlan;
1149 + int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1152 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1154 + reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1155 + val->value.i = (reg >> shift) & 0xffff;
1161 +esw_get_port_tr_badgood(struct switch_dev *dev,
1162 + const struct switch_attr *attr,
1163 + struct switch_val *val)
1165 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1167 + int idx = val->port_vlan;
1168 + int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1171 + if (!soc_is_rt5350())
1174 + if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1177 + reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1178 + val->value.i = (reg >> shift) & 0xffff;
1183 +static int esw_get_port_led(struct switch_dev *dev,
1184 + const struct switch_attr *attr,
1185 + struct switch_val *val)
1187 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1188 + int idx = val->port_vlan;
1190 + if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1191 + idx >= RT305X_ESW_NUM_LEDS)
1194 + val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1199 +static int esw_set_port_led(struct switch_dev *dev,
1200 + const struct switch_attr *attr,
1201 + struct switch_val *val)
1203 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1204 + int idx = val->port_vlan;
1206 + if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1209 + esw->ports[idx].led = val->value.i;
1214 +static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1216 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1218 + if (port >= RT305X_ESW_NUM_PORTS)
1221 + *val = esw_get_pvid(esw, port);
1226 +static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1228 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1230 + if (port >= RT305X_ESW_NUM_PORTS)
1233 + esw->ports[port].pvid = val;
1238 +static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1240 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1242 + int vlan_idx = -1;
1247 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1251 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1252 + if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1253 + esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1259 + if (vlan_idx == -1)
1262 + vmsc = esw_get_vmsc(esw, vlan_idx);
1263 + poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1265 + for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1266 + struct switch_port *p;
1267 + int port_mask = 1 << i;
1269 + if (!(vmsc & port_mask))
1272 + p = &val->value.ports[val->len++];
1274 + if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1277 + p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1283 +static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1285 + struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1287 + int vlan_idx = -1;
1290 + if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1291 + val->len > RT305X_ESW_NUM_PORTS)
1294 + /* one of the already defined vlans? */
1295 + for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1296 + if (esw->vlans[i].vid == val->port_vlan &&
1297 + esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1303 + /* select a free slot */
1304 + for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1305 + if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1309 + /* bail if all slots are in use */
1310 + if (vlan_idx == -1)
1313 + ports = RT305X_ESW_PORTS_NONE;
1314 + for (i = 0; i < val->len; i++) {
1315 + struct switch_port *p = &val->value.ports[i];
1316 + int port_mask = 1 << p->id;
1317 + bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1319 + if (p->id >= RT305X_ESW_NUM_PORTS)
1322 + ports |= port_mask;
1323 + esw->ports[p->id].untag = untagged;
1325 + esw->vlans[vlan_idx].ports = ports;
1326 + if (ports == RT305X_ESW_PORTS_NONE)
1327 + esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1329 + esw->vlans[vlan_idx].vid = val->port_vlan;
1334 +static const struct switch_attr esw_global[] = {
1336 + .type = SWITCH_TYPE_INT,
1337 + .name = "enable_vlan",
1338 + .description = "VLAN mode (1:enabled)",
1340 + .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1341 + .get = esw_get_vlan_enable,
1342 + .set = esw_set_vlan_enable,
1345 + .type = SWITCH_TYPE_INT,
1346 + .name = "alternate_vlan_disable",
1347 + .description = "Use en_vlan instead of doubletag to disable"
1350 + .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1351 + .get = esw_get_alt_vlan_disable,
1352 + .set = esw_set_alt_vlan_disable,
1355 + .type = SWITCH_TYPE_INT,
1356 + .name = "bc_storm_protect",
1357 + .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1359 + .id = RT305X_ESW_ATTR_BC_STATUS,
1360 + .get = rt305x_esw_get_bc_status,
1361 + .set = rt305x_esw_set_bc_status,
1364 + .type = SWITCH_TYPE_INT,
1365 + .name = "led_frequency",
1366 + .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1368 + .id = RT305X_ESW_ATTR_LED_FREQ,
1369 + .get = rt305x_esw_get_led_freq,
1370 + .set = rt305x_esw_set_led_freq,
1374 +static const struct switch_attr esw_port[] = {
1376 + .type = SWITCH_TYPE_INT,
1377 + .name = "disable",
1378 + .description = "Port state (1:disabled)",
1380 + .id = RT305X_ESW_ATTR_PORT_DISABLE,
1381 + .get = esw_get_port_bool,
1382 + .set = esw_set_port_bool,
1385 + .type = SWITCH_TYPE_INT,
1386 + .name = "doubletag",
1387 + .description = "Double tagging for incoming vlan packets "
1390 + .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1391 + .get = esw_get_port_bool,
1392 + .set = esw_set_port_bool,
1395 + .type = SWITCH_TYPE_INT,
1397 + .description = "Untag (1:strip outgoing vlan tag)",
1399 + .id = RT305X_ESW_ATTR_PORT_UNTAG,
1400 + .get = esw_get_port_bool,
1401 + .set = esw_set_port_bool,
1404 + .type = SWITCH_TYPE_INT,
1406 + .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1407 + " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1408 + " 8:100mact, 10:blink, 11:off, 12:on)",
1410 + .id = RT305X_ESW_ATTR_PORT_LED,
1411 + .get = esw_get_port_led,
1412 + .set = esw_set_port_led,
1415 + .type = SWITCH_TYPE_INT,
1417 + .description = "HW port group (0:wan, 1:lan)",
1419 + .id = RT305X_ESW_ATTR_PORT_LAN,
1420 + .get = esw_get_port_bool,
1423 + .type = SWITCH_TYPE_INT,
1424 + .name = "recv_bad",
1425 + .description = "Receive bad packet counter",
1426 + .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1427 + .get = esw_get_port_recv_badgood,
1430 + .type = SWITCH_TYPE_INT,
1431 + .name = "recv_good",
1432 + .description = "Receive good packet counter",
1433 + .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1434 + .get = esw_get_port_recv_badgood,
1437 + .type = SWITCH_TYPE_INT,
1440 + .description = "Transmit bad packet counter. rt5350 only",
1441 + .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1442 + .get = esw_get_port_tr_badgood,
1445 + .type = SWITCH_TYPE_INT,
1446 + .name = "tr_good",
1448 + .description = "Transmit good packet counter. rt5350 only",
1449 + .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1450 + .get = esw_get_port_tr_badgood,
1454 +static const struct switch_attr esw_vlan[] = {
1457 +static const struct switch_dev_ops esw_ops = {
1459 + .attr = esw_global,
1460 + .n_attr = ARRAY_SIZE(esw_global),
1464 + .n_attr = ARRAY_SIZE(esw_port),
1468 + .n_attr = ARRAY_SIZE(esw_vlan),
1470 + .get_vlan_ports = esw_get_vlan_ports,
1471 + .set_vlan_ports = esw_set_vlan_ports,
1472 + .get_port_pvid = esw_get_port_pvid,
1473 + .set_port_pvid = esw_set_port_pvid,
1474 + .get_port_link = esw_get_port_link,
1475 + .apply_config = esw_apply_config,
1476 + .reset_switch = esw_reset_switch,
1479 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1480 + /* All ports are LAN ports. */
1481 + .vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
1482 + .reg_initval_fct2 = 0x00d6500c,
1484 + * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1485 + * turbo mii off, rgmi 3.3v off
1487 + * port6: enabled, gige, full-duplex, rx/tx-flow-control
1489 + .reg_initval_fpa2 = 0x3f502b28,
1492 +static const struct of_device_id ralink_esw_match[] = {
1493 + { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1496 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1498 +static int esw_probe(struct platform_device *pdev)
1500 + struct device_node *np = pdev->dev.of_node;
1501 + const struct rt305x_esw_platform_data *pdata;
1502 + const __be32 *port_map, *reg_init;
1503 + struct rt305x_esw *esw;
1504 + struct switch_dev *swdev;
1505 + struct resource *res, *irq;
1508 + pdata = pdev->dev.platform_data;
1510 + const struct of_device_id *match;
1511 + match = of_match_device(ralink_esw_match, &pdev->dev);
1513 + pdata = (struct rt305x_esw_platform_data *) match->data;
1518 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1520 + dev_err(&pdev->dev, "no memory resource found\n");
1524 + irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1526 + dev_err(&pdev->dev, "no irq resource found\n");
1530 + esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1532 + dev_err(&pdev->dev, "no memory for private data\n");
1536 + esw->dev = &pdev->dev;
1537 + esw->irq = irq->start;
1538 + esw->base = ioremap(res->start, resource_size(res));
1540 + dev_err(&pdev->dev, "ioremap failed\n");
1545 + port_map = of_get_property(np, "ralink,portmap", NULL);
1547 + esw->port_map = be32_to_cpu(*port_map);
1549 + reg_init = of_get_property(np, "ralink,fct2", NULL);
1551 + esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1553 + reg_init = of_get_property(np, "ralink,fpa2", NULL);
1555 + esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1557 + reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1559 + esw->reg_led_polarity = be32_to_cpu(*reg_init);
1561 + swdev = &esw->swdev;
1562 + swdev->of_node = pdev->dev.of_node;
1563 + swdev->name = "rt305x-esw";
1564 + swdev->alias = "rt305x";
1565 + swdev->cpu_port = RT305X_ESW_PORT6;
1566 + swdev->ports = RT305X_ESW_NUM_PORTS;
1567 + swdev->vlans = RT305X_ESW_NUM_VIDS;
1568 + swdev->ops = &esw_ops;
1570 + err = register_switch(swdev, NULL);
1572 + dev_err(&pdev->dev, "register_switch failed\n");
1576 + platform_set_drvdata(pdev, esw);
1578 + esw->pdata = pdata;
1579 + spin_lock_init(&esw->reg_rw_lock);
1583 + esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1584 + esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1585 + request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1590 + iounmap(esw->base);
1596 +static int esw_remove(struct platform_device *pdev)
1598 + struct rt305x_esw *esw;
1600 + esw = platform_get_drvdata(pdev);
1602 + unregister_switch(&esw->swdev);
1603 + platform_set_drvdata(pdev, NULL);
1604 + iounmap(esw->base);
1611 +static struct platform_driver esw_driver = {
1612 + .probe = esw_probe,
1613 + .remove = esw_remove,
1615 + .name = "rt305x-esw",
1616 + .owner = THIS_MODULE,
1617 + .of_match_table = ralink_esw_match,
1621 +int __init rtesw_init(void)
1623 + return platform_driver_register(&esw_driver);
1626 +void rtesw_exit(void)
1628 + platform_driver_unregister(&esw_driver);
1631 +++ b/drivers/net/ethernet/ralink/esw_rt3052.h
1634 + * This program is free software; you can redistribute it and/or modify
1635 + * it under the terms of the GNU General Public License as published by
1636 + * the Free Software Foundation; version 2 of the License
1638 + * This program is distributed in the hope that it will be useful,
1639 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1640 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1641 + * GNU General Public License for more details.
1643 + * You should have received a copy of the GNU General Public License
1644 + * along with this program; if not, write to the Free Software
1645 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1647 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1650 +#ifndef _RALINK_ESW_RT3052_H__
1651 +#define _RALINK_ESW_RT3052_H__
1653 +#ifdef CONFIG_NET_RALINK_ESW_RT3052
1655 +int __init rtesw_init(void);
1656 +void rtesw_exit(void);
1660 +static inline int __init rtesw_init(void) { return 0; }
1661 +static inline void rtesw_exit(void) { }
1666 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.c
1669 + * This program is free software; you can redistribute it and/or modify
1670 + * it under the terms of the GNU General Public License as published by
1671 + * the Free Software Foundation; version 2 of the License
1673 + * This program is distributed in the hope that it will be useful,
1674 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1675 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1676 + * GNU General Public License for more details.
1678 + * You should have received a copy of the GNU General Public License
1679 + * along with this program; if not, write to the Free Software
1680 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1682 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1685 +#include <linux/module.h>
1686 +#include <linux/kernel.h>
1687 +#include <linux/types.h>
1688 +#include <linux/dma-mapping.h>
1689 +#include <linux/init.h>
1690 +#include <linux/skbuff.h>
1691 +#include <linux/etherdevice.h>
1692 +#include <linux/ethtool.h>
1693 +#include <linux/platform_device.h>
1694 +#include <linux/of_device.h>
1695 +#include <linux/clk.h>
1696 +#include <linux/of_net.h>
1697 +#include <linux/of_mdio.h>
1698 +#include <linux/of_irq.h>
1699 +#include <linux/of_address.h>
1700 +#include <linux/switch.h>
1702 +#include <asm/mach-ralink/ralink_regs.h>
1704 +#include "ralink_soc_eth.h"
1706 +#include <linux/ioport.h>
1707 +#include <linux/switch.h>
1708 +#include <linux/mii.h>
1710 +#include <ralink_regs.h>
1711 +#include <asm/mach-ralink/mt7620.h>
1713 +#include "ralink_soc_eth.h"
1714 +#include "gsw_mt7620a.h"
1715 +#include "mt7530.h"
1718 +#define GSW_REG_PHY_TIMEOUT (5 * HZ)
1720 +#define MT7620A_GSW_REG_PIAC 0x7004
1722 +#define GSW_NUM_VLANS 16
1723 +#define GSW_NUM_VIDS 4096
1724 +#define GSW_NUM_PORTS 7
1725 +#define GSW_PORT6 6
1727 +#define GSW_MDIO_ACCESS BIT(31)
1728 +#define GSW_MDIO_READ BIT(19)
1729 +#define GSW_MDIO_WRITE BIT(18)
1730 +#define GSW_MDIO_START BIT(16)
1731 +#define GSW_MDIO_ADDR_SHIFT 20
1732 +#define GSW_MDIO_REG_SHIFT 25
1734 +#define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
1735 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
1736 +#define GSW_REG_SMACCR0 0x3fE4
1737 +#define GSW_REG_SMACCR1 0x3fE8
1738 +#define GSW_REG_CKGCR 0x3ff0
1740 +#define GSW_REG_IMR 0x7008
1741 +#define GSW_REG_ISR 0x700c
1743 +#define SYSC_REG_CFG1 0x14
1745 +#define PORT_IRQ_ST_CHG 0x7f
1747 +#define SYSCFG1 0x14
1749 +#define ESW_PHY_POLLING 0x7000
1751 +#define PMCR_IPG BIT(18)
1752 +#define PMCR_MAC_MODE BIT(16)
1753 +#define PMCR_FORCE BIT(15)
1754 +#define PMCR_TX_EN BIT(14)
1755 +#define PMCR_RX_EN BIT(13)
1756 +#define PMCR_BACKOFF BIT(9)
1757 +#define PMCR_BACKPRES BIT(8)
1758 +#define PMCR_RX_FC BIT(5)
1759 +#define PMCR_TX_FC BIT(4)
1760 +#define PMCR_SPEED(_x) (_x << 2)
1761 +#define PMCR_DUPLEX BIT(1)
1762 +#define PMCR_LINK BIT(0)
1764 +#define PHY_AN_EN BIT(31)
1765 +#define PHY_PRE_EN BIT(30)
1766 +#define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
1769 + /* Global attributes. */
1770 + GSW_ATTR_ENABLE_VLAN,
1771 + /* Port attributes. */
1772 + GSW_ATTR_PORT_UNTAG,
1780 +struct mt7620_gsw {
1781 + struct device *dev;
1782 + void __iomem *base;
1785 + long unsigned int autopoll;
1788 +static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
1790 + iowrite32(val, gsw->base + reg);
1793 +static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
1795 + return ioread32(gsw->base + reg);
1798 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
1800 + unsigned long t_start = jiffies;
1803 + if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
1805 + if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
1810 + printk(KERN_ERR "mdio: MDIO timeout\n");
1814 +static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
1817 + if (mt7620_mii_busy_wait(gsw))
1820 + write_data &= 0xffff;
1822 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
1823 + (phy_register << GSW_MDIO_REG_SHIFT) |
1824 + (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
1825 + MT7620A_GSW_REG_PIAC);
1827 + if (mt7620_mii_busy_wait(gsw))
1833 +static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
1837 + if (mt7620_mii_busy_wait(gsw))
1840 + gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
1841 + (phy_reg << GSW_MDIO_REG_SHIFT) |
1842 + (phy_addr << GSW_MDIO_ADDR_SHIFT),
1843 + MT7620A_GSW_REG_PIAC);
1845 + if (mt7620_mii_busy_wait(gsw))
1848 + d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
1853 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
1855 + struct fe_priv *priv = bus->priv;
1856 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1858 + return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
1861 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
1863 + struct fe_priv *priv = bus->priv;
1864 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1866 + return _mt7620_mii_read(gsw, phy_addr, phy_reg);
1869 +static unsigned char *fe_speed_str(int speed)
1886 +int mt7620a_has_carrier(struct fe_priv *priv)
1888 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1891 + for (i = 0; i < GSW_PORT6; i++)
1892 + if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
1897 +static void mt7620a_handle_carrier(struct fe_priv *priv)
1902 + if (mt7620a_has_carrier(priv))
1903 + netif_carrier_on(priv->netdev);
1905 + netif_carrier_off(priv->netdev);
1908 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
1910 + if (priv->link[port])
1911 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1912 + port, fe_speed_str(priv->phy->speed[port]),
1913 + (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
1915 + netdev_info(priv->netdev, "port %d link down\n", port);
1916 + mt7620a_handle_carrier(priv);
1919 +static irqreturn_t gsw_interrupt(int irq, void *_priv)
1921 + struct fe_priv *priv = (struct fe_priv *) _priv;
1922 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1924 + int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
1926 + status = gsw_r32(gsw, GSW_REG_ISR);
1927 + if (status & PORT_IRQ_ST_CHG)
1928 + for (i = 0; i <= max; i++) {
1929 + u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
1930 + int link = status & 0x1;
1932 + if (link != priv->link[i]) {
1934 + netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1935 + i, fe_speed_str((status >> 2) & 3),
1936 + (status & 0x2) ? "Full" : "Half");
1938 + netdev_info(priv->netdev, "port %d link down\n", i);
1941 + priv->link[i] = link;
1943 + mt7620a_handle_carrier(priv);
1945 + gsw_w32(gsw, status, GSW_REG_ISR);
1947 + return IRQ_HANDLED;
1950 +static int mt7620_is_bga(void)
1952 + u32 bga = rt_sysc_r32(0x0c);
1954 + return (bga >> 16) & 1;
1957 +static void gsw_auto_poll(struct mt7620_gsw *gsw)
1960 + int lsb = -1, msb = 0;
1962 + for_each_set_bit(phy, &gsw->autopoll, 32) {
1968 + gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
1971 +void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
1973 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1974 + const __be32 *_id = of_get_property(np, "reg", NULL);
1975 + int phy_mode, size, id;
1977 + u32 val, mask = 0;
1978 + int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
1980 + if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
1982 + pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
1984 + pr_err("%s: invalid port id\n", np->name);
1988 + id = be32_to_cpu(*_id);
1993 + priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
1994 + if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
1995 + pr_err("%s: invalid fixed link property\n", np->name);
1996 + priv->phy->phy_fixed[id] = NULL;
2000 + phy_mode = of_get_phy_mode(np);
2001 + switch (phy_mode) {
2002 + case PHY_INTERFACE_MODE_RGMII:
2005 + case PHY_INTERFACE_MODE_MII:
2008 + case PHY_INTERFACE_MODE_RMII:
2012 + dev_err(priv->device, "port %d - invalid phy mode\n", id);
2016 + priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
2017 + if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
2020 + val = rt_sysc_r32(SYSCFG1);
2021 + val &= ~(3 << shift);
2022 + val |= mask << shift;
2023 + rt_sysc_w32(val, SYSCFG1);
2025 + if (priv->phy->phy_fixed[id]) {
2026 + const __be32 *link = priv->phy->phy_fixed[id];
2030 + priv->phy->speed[id] = be32_to_cpup(link++);
2031 + tx_fc = be32_to_cpup(link++);
2032 + rx_fc = be32_to_cpup(link++);
2033 + priv->phy->duplex[id] = be32_to_cpup(link++);
2034 + priv->link[id] = 1;
2036 + switch (priv->phy->speed[id]) {
2047 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
2048 + priv->phy->phy_fixed[id] = 0;
2051 + val = PMCR_SPEED(val);
2052 + val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2053 + PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
2055 + val |= PMCR_TX_FC;
2057 + val |= PMCR_RX_FC;
2058 + if (priv->phy->duplex[id])
2059 + val |= PMCR_DUPLEX;
2060 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2061 + dev_info(priv->device, "using fixed link parameters\n");
2065 + if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
2066 + u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2067 + PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
2069 + gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2070 + fe_connect_phy_node(priv, priv->phy->phy_node[id]);
2071 + gsw->autopoll |= BIT(id);
2072 + gsw_auto_poll(gsw);
2077 +static void gsw_hw_init(struct mt7620_gsw *gsw)
2079 + u32 is_BGA = mt7620_is_bga();
2081 + rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
2082 + gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
2084 + /*correct PHY setting L3.0 BGA*/
2085 + _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
2087 + _mt7620_mii_write(gsw, 1, 17, 0x7444);
2089 + _mt7620_mii_write(gsw, 1, 19, 0x0114);
2091 + _mt7620_mii_write(gsw, 1, 19, 0x0117);
2093 + _mt7620_mii_write(gsw, 1, 22, 0x10cf);
2094 + _mt7620_mii_write(gsw, 1, 25, 0x6212);
2095 + _mt7620_mii_write(gsw, 1, 26, 0x0777);
2096 + _mt7620_mii_write(gsw, 1, 29, 0x4000);
2097 + _mt7620_mii_write(gsw, 1, 28, 0xc077);
2098 + _mt7620_mii_write(gsw, 1, 24, 0x0000);
2100 + _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
2101 + _mt7620_mii_write(gsw, 1, 17, 0x4838);
2103 + _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
2105 + _mt7620_mii_write(gsw, 1, 21, 0x0515);
2106 + _mt7620_mii_write(gsw, 1, 22, 0x0053);
2107 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2108 + _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
2109 + _mt7620_mii_write(gsw, 1, 25, 0x0fad);
2110 + _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
2112 + _mt7620_mii_write(gsw, 1, 21, 0x0517);
2113 + _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
2114 + _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2115 + _mt7620_mii_write(gsw, 1, 24, 0x0aab);
2116 + _mt7620_mii_write(gsw, 1, 25, 0x00ae);
2117 + _mt7620_mii_write(gsw, 1, 26, 0x0fff);
2119 + _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
2120 + _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
2122 + _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
2123 + _mt7620_mii_write(gsw, 0, 30, 0xa000);
2124 + _mt7620_mii_write(gsw, 1, 30, 0xa000);
2125 + _mt7620_mii_write(gsw, 2, 30, 0xa000);
2126 + _mt7620_mii_write(gsw, 3, 30, 0xa000);
2128 + _mt7620_mii_write(gsw, 0, 4, 0x05e1);
2129 + _mt7620_mii_write(gsw, 1, 4, 0x05e1);
2130 + _mt7620_mii_write(gsw, 2, 4, 0x05e1);
2131 + _mt7620_mii_write(gsw, 3, 4, 0x05e1);
2132 + _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
2133 + _mt7620_mii_write(gsw, 0, 16, 0x1111);
2134 + _mt7620_mii_write(gsw, 1, 16, 0x1010);
2135 + _mt7620_mii_write(gsw, 2, 16, 0x1515);
2136 + _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
2138 + /* CPU Port6 Force Link 1G, FC ON */
2139 + gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
2140 + /* Set Port6 CPU Port */
2141 + gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
2143 + /* setup port 4 */
2144 + if (gsw->port4 == PORT4_EPHY) {
2145 + u32 val = rt_sysc_r32(SYSCFG1);
2147 + rt_sysc_w32(val, SYSCFG1);
2148 + _mt7620_mii_write(gsw, 4, 30, 0xa000);
2149 + _mt7620_mii_write(gsw, 4, 4, 0x05e1);
2150 + _mt7620_mii_write(gsw, 4, 16, 0x1313);
2151 + pr_info("gsw: setting port4 to ephy mode\n");
2155 +void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
2157 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2158 + unsigned long flags;
2160 + spin_lock_irqsave(&priv->page_lock, flags);
2161 + gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
2162 + gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2164 + spin_unlock_irqrestore(&priv->page_lock, flags);
2167 +static struct of_device_id gsw_match[] = {
2168 + { .compatible = "ralink,mt7620a-gsw" },
2172 +int mt7620_gsw_config(struct fe_priv *priv)
2174 + struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2176 + /* is the mt7530 internal or external */
2177 + if ((_mt7620_mii_read(gsw, 0x1f, 2) == 1) && (_mt7620_mii_read(gsw, 0x1f, 3) == 0xbeef))
2178 + mt7530_probe(priv->device, NULL, priv->mii_bus);
2180 + mt7530_probe(priv->device, gsw->base, NULL);
2185 +int mt7620_gsw_probe(struct fe_priv *priv)
2187 + struct mt7620_gsw *gsw;
2188 + struct device_node *np;
2189 + const char *port4 = NULL;
2191 + np = of_find_matching_node(NULL, gsw_match);
2193 + dev_err(priv->device, "no gsw node found\n");
2196 + np = of_node_get(np);
2198 + gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
2200 + dev_err(priv->device, "no gsw memory for private data\n");
2204 + gsw->irq = irq_of_parse_and_map(np, 0);
2206 + dev_err(priv->device, "no gsw irq resource found\n");
2210 + gsw->base = of_iomap(np, 0);
2212 + dev_err(priv->device, "gsw ioremap failed\n");
2216 + gsw->dev = priv->device;
2217 + priv->soc->swpriv = gsw;
2219 + of_property_read_string(np, "ralink,port4", &port4);
2220 + if (port4 && !strcmp(port4, "ephy"))
2221 + gsw->port4 = PORT4_EPHY;
2222 + else if (port4 && !strcmp(port4, "gmac"))
2223 + gsw->port4 = PORT4_EXT;
2229 + gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
2230 + request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
2235 +++ b/drivers/net/ethernet/ralink/gsw_mt7620a.h
2238 + * This program is free software; you can redistribute it and/or modify
2239 + * it under the terms of the GNU General Public License as published by
2240 + * the Free Software Foundation; version 2 of the License
2242 + * This program is distributed in the hope that it will be useful,
2243 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2244 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2245 + * GNU General Public License for more details.
2247 + * You should have received a copy of the GNU General Public License
2248 + * along with this program; if not, write to the Free Software
2249 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2251 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2254 +#ifndef _RALINK_GSW_MT7620_H__
2255 +#define _RALINK_GSW_MT7620_H__
2257 +extern int mt7620_gsw_config(struct fe_priv *priv);
2258 +extern int mt7620_gsw_probe(struct fe_priv *priv);
2259 +extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
2260 +extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2261 +extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2262 +extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
2263 +extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
2264 +extern int mt7620a_has_carrier(struct fe_priv *priv);
2268 +++ b/drivers/net/ethernet/ralink/mdio.c
2271 + * This program is free software; you can redistribute it and/or modify
2272 + * it under the terms of the GNU General Public License as published by
2273 + * the Free Software Foundation; version 2 of the License
2275 + * This program is distributed in the hope that it will be useful,
2276 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2277 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2278 + * GNU General Public License for more details.
2280 + * You should have received a copy of the GNU General Public License
2281 + * along with this program; if not, write to the Free Software
2282 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2284 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2287 +#include <linux/module.h>
2288 +#include <linux/kernel.h>
2289 +#include <linux/types.h>
2290 +#include <linux/dma-mapping.h>
2291 +#include <linux/init.h>
2292 +#include <linux/skbuff.h>
2293 +#include <linux/etherdevice.h>
2294 +#include <linux/ethtool.h>
2295 +#include <linux/platform_device.h>
2296 +#include <linux/phy.h>
2297 +#include <linux/of_device.h>
2298 +#include <linux/clk.h>
2299 +#include <linux/of_net.h>
2300 +#include <linux/of_mdio.h>
2302 +#include "ralink_soc_eth.h"
2305 +static int fe_mdio_reset(struct mii_bus *bus)
2311 +static void fe_phy_link_adjust(struct net_device *dev)
2313 + struct fe_priv *priv = netdev_priv(dev);
2314 + unsigned long flags;
2317 + spin_lock_irqsave(&priv->phy->lock, flags);
2318 + for (i = 0; i < 8; i++) {
2319 + if (priv->phy->phy_node[i]) {
2320 + struct phy_device *phydev = priv->phy->phy[i];
2321 + int status_change = 0;
2324 + if (priv->phy->duplex[i] != phydev->duplex ||
2325 + priv->phy->speed[i] != phydev->speed)
2326 + status_change = 1;
2328 + if (phydev->link != priv->link[i])
2329 + status_change = 1;
2331 + switch (phydev->speed) {
2335 + priv->link[i] = phydev->link;
2336 + priv->phy->duplex[i] = phydev->duplex;
2337 + priv->phy->speed[i] = phydev->speed;
2339 + if (status_change && priv->soc->mdio_adjust_link)
2340 + priv->soc->mdio_adjust_link(priv, i);
2347 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
2349 + const __be32 *_port = NULL;
2350 + struct phy_device *phydev;
2351 + int phy_mode, port;
2353 + _port = of_get_property(phy_node, "reg", NULL);
2355 + if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
2356 + pr_err("%s: invalid port id\n", phy_node->name);
2359 + port = be32_to_cpu(*_port);
2360 + phy_mode = of_get_phy_mode(phy_node);
2361 + if (phy_mode < 0) {
2362 + dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
2363 + priv->phy->phy_node[port] = NULL;
2367 + phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
2369 + if (IS_ERR(phydev)) {
2370 + dev_err(priv->device, "could not connect to PHY\n");
2371 + priv->phy->phy_node[port] = NULL;
2372 + return PTR_ERR(phydev);
2375 + phydev->supported &= PHY_GBIT_FEATURES;
2376 + phydev->advertising = phydev->supported;
2377 + phydev->no_auto_carrier_off = 1;
2379 + dev_info(priv->device,
2380 + "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
2381 + port, dev_name(&phydev->dev), phydev->phy_id,
2382 + phydev->drv->name);
2384 + priv->phy->phy[port] = phydev;
2385 + priv->link[port] = 0;
2390 +static int fe_phy_connect(struct fe_priv *priv)
2395 +static void fe_phy_disconnect(struct fe_priv *priv)
2397 + unsigned long flags;
2400 + for (i = 0; i < 8; i++)
2401 + if (priv->phy->phy_fixed[i]) {
2402 + spin_lock_irqsave(&priv->phy->lock, flags);
2403 + priv->link[i] = 0;
2404 + if (priv->soc->mdio_adjust_link)
2405 + priv->soc->mdio_adjust_link(priv, i);
2406 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2407 + } else if (priv->phy->phy[i]) {
2408 + phy_disconnect(priv->phy->phy[i]);
2412 +static void fe_phy_start(struct fe_priv *priv)
2414 + unsigned long flags;
2417 + for (i = 0; i < 8; i++) {
2418 + if (priv->phy->phy_fixed[i]) {
2419 + spin_lock_irqsave(&priv->phy->lock, flags);
2420 + priv->link[i] = 1;
2421 + if (priv->soc->mdio_adjust_link)
2422 + priv->soc->mdio_adjust_link(priv, i);
2423 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2424 + } else if (priv->phy->phy[i]) {
2425 + phy_start(priv->phy->phy[i]);
2430 +static void fe_phy_stop(struct fe_priv *priv)
2432 + unsigned long flags;
2435 + for (i = 0; i < 8; i++)
2436 + if (priv->phy->phy_fixed[i]) {
2437 + spin_lock_irqsave(&priv->phy->lock, flags);
2438 + priv->link[i] = 0;
2439 + if (priv->soc->mdio_adjust_link)
2440 + priv->soc->mdio_adjust_link(priv, i);
2441 + spin_unlock_irqrestore(&priv->phy->lock, flags);
2442 + } else if (priv->phy->phy[i]) {
2443 + phy_stop(priv->phy->phy[i]);
2447 +static struct fe_phy phy_ralink = {
2448 + .connect = fe_phy_connect,
2449 + .disconnect = fe_phy_disconnect,
2450 + .start = fe_phy_start,
2451 + .stop = fe_phy_stop,
2454 +int fe_mdio_init(struct fe_priv *priv)
2456 + struct device_node *mii_np;
2459 + if (!priv->soc->mdio_read || !priv->soc->mdio_write)
2462 + spin_lock_init(&phy_ralink.lock);
2463 + priv->phy = &phy_ralink;
2465 + mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
2467 + dev_err(priv->device, "no %s child node found", "mdio-bus");
2471 + if (!of_device_is_available(mii_np)) {
2473 + goto err_put_node;
2476 + priv->mii_bus = mdiobus_alloc();
2477 + if (priv->mii_bus == NULL) {
2479 + goto err_put_node;
2482 + priv->mii_bus->name = "mdio";
2483 + priv->mii_bus->read = priv->soc->mdio_read;
2484 + priv->mii_bus->write = priv->soc->mdio_write;
2485 + priv->mii_bus->reset = fe_mdio_reset;
2486 + priv->mii_bus->irq = priv->mii_irq;
2487 + priv->mii_bus->priv = priv;
2488 + priv->mii_bus->parent = priv->device;
2490 + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
2491 + err = of_mdiobus_register(priv->mii_bus, mii_np);
2493 + goto err_free_bus;
2498 + kfree(priv->mii_bus);
2500 + of_node_put(mii_np);
2501 + priv->mii_bus = NULL;
2505 +void fe_mdio_cleanup(struct fe_priv *priv)
2507 + if (!priv->mii_bus)
2510 + mdiobus_unregister(priv->mii_bus);
2511 + of_node_put(priv->mii_bus->dev.of_node);
2512 + kfree(priv->mii_bus);
2515 +++ b/drivers/net/ethernet/ralink/mdio.h
2518 + * This program is free software; you can redistribute it and/or modify
2519 + * it under the terms of the GNU General Public License as published by
2520 + * the Free Software Foundation; version 2 of the License
2522 + * This program is distributed in the hope that it will be useful,
2523 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2524 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2525 + * GNU General Public License for more details.
2527 + * You should have received a copy of the GNU General Public License
2528 + * along with this program; if not, write to the Free Software
2529 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2531 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2534 +#ifndef _RALINK_MDIO_H__
2535 +#define _RALINK_MDIO_H__
2537 +#ifdef CONFIG_NET_RALINK_MDIO
2538 +extern int fe_mdio_init(struct fe_priv *priv);
2539 +extern void fe_mdio_cleanup(struct fe_priv *priv);
2540 +extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
2542 +static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
2543 +static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
2547 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.c
2550 + * This program is free software; you can redistribute it and/or modify
2551 + * it under the terms of the GNU General Public License as published by
2552 + * the Free Software Foundation; version 2 of the License
2554 + * This program is distributed in the hope that it will be useful,
2555 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2556 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2557 + * GNU General Public License for more details.
2559 + * You should have received a copy of the GNU General Public License
2560 + * along with this program; if not, write to the Free Software
2561 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2563 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2566 +#include <linux/module.h>
2567 +#include <linux/kernel.h>
2568 +#include <linux/types.h>
2569 +#include <linux/dma-mapping.h>
2570 +#include <linux/init.h>
2571 +#include <linux/skbuff.h>
2572 +#include <linux/etherdevice.h>
2573 +#include <linux/ethtool.h>
2574 +#include <linux/platform_device.h>
2575 +#include <linux/phy.h>
2576 +#include <linux/of_device.h>
2577 +#include <linux/clk.h>
2578 +#include <linux/of_net.h>
2579 +#include <linux/of_mdio.h>
2581 +#include "ralink_soc_eth.h"
2582 +#include "mdio_rt2880.h"
2585 +#define FE_MDIO_RETRY 1000
2587 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
2589 + switch (priv->phy->speed[0]) {
2601 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
2605 + if (!priv->link[0]) {
2606 + netif_carrier_off(priv->netdev);
2607 + netdev_info(priv->netdev, "link down\n");
2611 + mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
2612 + FE_MDIO_CFG_RX_CLK_SKEW_200 |
2613 + FE_MDIO_CFG_GP1_FRC_EN;
2615 + if (priv->phy->duplex[0] == DUPLEX_FULL)
2616 + mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
2618 + if (priv->phy->tx_fc[0])
2619 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
2621 + if (priv->phy->rx_fc[0])
2622 + mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
2624 + switch (priv->phy->speed[0]) {
2626 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
2629 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
2632 + mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
2638 + fe_w32(mdio_cfg, FE_MDIO_CFG);
2640 + netif_carrier_on(priv->netdev);
2641 + netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
2642 + rt2880_speed_str(priv),
2643 + (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
2646 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
2650 + retries = FE_MDIO_RETRY;
2654 + t = fe_r32(FE_MDIO_ACCESS);
2655 + if ((t & (0x1 << 31)) == 0)
2658 + if (retries-- == 0)
2664 + dev_err(priv->device, "MDIO operation timed out\n");
2665 + return -ETIMEDOUT;
2668 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
2670 + struct fe_priv *priv = bus->priv;
2674 + err = rt2880_mdio_wait_ready(priv);
2678 + t = (phy_addr << 24) | (phy_reg << 16);
2679 + fe_w32(t, FE_MDIO_ACCESS);
2681 + fe_w32(t, FE_MDIO_ACCESS);
2683 + err = rt2880_mdio_wait_ready(priv);
2687 + pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2688 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2690 + return fe_r32(FE_MDIO_ACCESS) & 0xffff;
2693 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
2695 + struct fe_priv *priv = bus->priv;
2699 + pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2700 + phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2702 + err = rt2880_mdio_wait_ready(priv);
2706 + t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
2707 + fe_w32(t, FE_MDIO_ACCESS);
2709 + fe_w32(t, FE_MDIO_ACCESS);
2711 + return rt2880_mdio_wait_ready(priv);
2714 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
2716 + const __be32 *id = of_get_property(np, "reg", NULL);
2717 + const __be32 *link;
2721 + if (!id || (be32_to_cpu(*id) != 0)) {
2722 + pr_err("%s: invalid port id\n", np->name);
2726 + priv->phy->phy_fixed[0] = of_get_property(np, "ralink,fixed-link", &size);
2727 + if (priv->phy->phy_fixed[0] && (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
2728 + pr_err("%s: invalid fixed link property\n", np->name);
2729 + priv->phy->phy_fixed[0] = NULL;
2733 + phy_mode = of_get_phy_mode(np);
2734 + switch (phy_mode) {
2735 + case PHY_INTERFACE_MODE_RGMII:
2737 + case PHY_INTERFACE_MODE_MII:
2739 + case PHY_INTERFACE_MODE_RMII:
2742 + if (!priv->phy->phy_fixed[0])
2743 + dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[0]);
2747 + priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
2748 + if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
2751 + if (priv->phy->phy_fixed[0]) {
2752 + link = priv->phy->phy_fixed[0];
2753 + priv->phy->speed[0] = be32_to_cpup(link++);
2754 + priv->phy->duplex[0] = be32_to_cpup(link++);
2755 + priv->phy->tx_fc[0] = be32_to_cpup(link++);
2756 + priv->phy->rx_fc[0] = be32_to_cpup(link++);
2758 + priv->link[0] = 1;
2759 + switch (priv->phy->speed[0]) {
2767 + dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[0]);
2768 + priv->phy->phy_fixed[0] = 0;
2771 + dev_info(priv->device, "using fixed link parameters\n");
2772 + rt2880_mdio_link_adjust(priv, 0);
2775 + if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0]) {
2776 + fe_connect_phy_node(priv, priv->phy->phy_node[0]);
2782 +++ b/drivers/net/ethernet/ralink/mdio_rt2880.h
2785 + * This program is free software; you can redistribute it and/or modify
2786 + * it under the terms of the GNU General Public License as published by
2787 + * the Free Software Foundation; version 2 of the License
2789 + * This program is distributed in the hope that it will be useful,
2790 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2791 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2792 + * GNU General Public License for more details.
2794 + * You should have received a copy of the GNU General Public License
2795 + * along with this program; if not, write to the Free Software
2796 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2798 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2801 +#ifndef _RALINK_MDIO_RT2880_H__
2802 +#define _RALINK_MDIO_RT2880_H__
2804 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
2805 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2806 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2807 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
2811 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.c
2814 + * This program is free software; you can redistribute it and/or modify
2815 + * it under the terms of the GNU General Public License as published by
2816 + * the Free Software Foundation; version 2 of the License
2818 + * This program is distributed in the hope that it will be useful,
2819 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2820 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2821 + * GNU General Public License for more details.
2823 + * You should have received a copy of the GNU General Public License
2824 + * along with this program; if not, write to the Free Software
2825 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2827 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2830 +#include <linux/module.h>
2831 +#include <linux/kernel.h>
2832 +#include <linux/types.h>
2833 +#include <linux/dma-mapping.h>
2834 +#include <linux/init.h>
2835 +#include <linux/skbuff.h>
2836 +#include <linux/etherdevice.h>
2837 +#include <linux/ethtool.h>
2838 +#include <linux/platform_device.h>
2839 +#include <linux/of_device.h>
2840 +#include <linux/clk.h>
2841 +#include <linux/of_net.h>
2842 +#include <linux/of_mdio.h>
2843 +#include <linux/if_vlan.h>
2844 +#include <linux/reset.h>
2846 +#include <asm/mach-ralink/ralink_regs.h>
2848 +#include "ralink_soc_eth.h"
2849 +#include "esw_rt3052.h"
2852 +#define TX_TIMEOUT (20 * HZ / 100)
2853 +#define MAX_RX_LENGTH 1536
2855 +static const u32 fe_reg_table_default[FE_REG_COUNT] = {
2856 + [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
2857 + [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
2858 + [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
2859 + [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
2860 + [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
2861 + [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
2862 + [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
2863 + [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
2864 + [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
2865 + [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
2866 + [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
2869 +static const u32 *fe_reg_table = fe_reg_table_default;
2871 +static void __iomem *fe_base = 0;
2873 +void fe_w32(u32 val, unsigned reg)
2875 + __raw_writel(val, fe_base + reg);
2878 +u32 fe_r32(unsigned reg)
2880 + return __raw_readl(fe_base + reg);
2883 +static inline void fe_reg_w32(u32 val, enum fe_reg reg)
2885 + fe_w32(val, fe_reg_table[reg]);
2888 +static inline u32 fe_reg_r32(enum fe_reg reg)
2890 + return fe_r32(fe_reg_table[reg]);
2893 +static inline void fe_int_disable(u32 mask)
2895 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
2896 + FE_REG_FE_INT_ENABLE);
2898 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
2901 +static inline void fe_int_enable(u32 mask)
2903 + fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
2904 + FE_REG_FE_INT_ENABLE);
2906 + fe_reg_r32(FE_REG_FE_INT_ENABLE);
2909 +static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
2911 + unsigned long flags;
2913 + spin_lock_irqsave(&priv->page_lock, flags);
2914 + fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
2915 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2916 + FE_GDMA1_MAC_ADRL);
2917 + spin_unlock_irqrestore(&priv->page_lock, flags);
2920 +static int fe_set_mac_address(struct net_device *dev, void *p)
2922 + int ret = eth_mac_addr(dev, p);
2925 + struct fe_priv *priv = netdev_priv(dev);
2927 + if (priv->soc->set_mac)
2928 + priv->soc->set_mac(priv, dev->dev_addr);
2930 + fe_hw_set_macaddr(priv, p);
2936 +static struct sk_buff* fe_alloc_skb(struct fe_priv *priv)
2938 + struct sk_buff *skb;
2940 + skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
2944 + skb_reserve(skb, NET_IP_ALIGN);
2949 +static int fe_alloc_rx(struct fe_priv *priv)
2951 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
2954 + priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
2955 + &priv->rx_phys, GFP_ATOMIC);
2956 + if (!priv->rx_dma)
2959 + memset(priv->rx_dma, 0, size);
2961 + for (i = 0; i < NUM_DMA_DESC; i++) {
2962 + priv->rx_skb[i] = fe_alloc_skb(priv);
2963 + if (!priv->rx_skb[i])
2967 + for (i = 0; i < NUM_DMA_DESC; i++) {
2968 + dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev,
2969 + priv->rx_skb[i]->data,
2972 + priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
2974 + if (priv->soc->rx_dma)
2975 + priv->soc->rx_dma(priv, i, MAX_RX_LENGTH);
2977 + priv->rx_dma[i].rxd2 = RX_DMA_LSO;
2981 + fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
2982 + fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
2983 + fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
2984 + fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
2989 +static int fe_alloc_tx(struct fe_priv *priv)
2991 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
2994 + priv->tx_free_idx = 0;
2996 + priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
2997 + &priv->tx_phys, GFP_ATOMIC);
2998 + if (!priv->tx_dma)
3001 + memset(priv->tx_dma, 0, size);
3003 + for (i = 0; i < NUM_DMA_DESC; i++) {
3004 + if (priv->soc->tx_dma) {
3005 + priv->soc->tx_dma(priv, i, 0);
3009 + priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
3010 + priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
3013 + fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
3014 + fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
3015 + fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
3016 + fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
3021 +static void fe_free_dma(struct fe_priv *priv)
3025 + for (i = 0; i < NUM_DMA_DESC; i++) {
3026 + if (priv->rx_skb[i]) {
3027 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1,
3028 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3029 + dev_kfree_skb_any(priv->rx_skb[i]);
3030 + priv->rx_skb[i] = NULL;
3033 + if (priv->tx_skb[i]) {
3034 + dev_kfree_skb_any(priv->tx_skb[i]);
3035 + priv->tx_skb[i] = NULL;
3039 + if (priv->rx_dma) {
3040 + int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
3041 + dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma,
3045 + if (priv->tx_dma) {
3046 + int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
3047 + dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma,
3051 + netdev_reset_queue(priv->netdev);
3054 +static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
3056 + struct fe_priv *priv = netdev_priv(dev);
3057 + dma_addr_t mapped_addr;
3061 + if (priv->soc->min_pkt_len) {
3062 + if (skb->len < priv->soc->min_pkt_len) {
3063 + if (skb_padto(skb, priv->soc->min_pkt_len)) {
3065 + "fe_eth: skb_padto failed\n");
3069 + skb_put(skb, priv->soc->min_pkt_len - skb->len);
3073 + dev->trans_start = jiffies;
3074 + mapped_addr = dma_map_single(&priv->netdev->dev, skb->data,
3075 + skb->len, DMA_TO_DEVICE);
3077 + spin_lock(&priv->page_lock);
3079 + tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
3080 + tx_next = (tx + 1) % NUM_DMA_DESC;
3082 + if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
3083 + !(priv->tx_dma[tx].txd2 & TX_DMA_DONE) ||
3084 + !(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE))
3086 + spin_unlock(&priv->page_lock);
3087 + dev->stats.tx_dropped++;
3090 + return NETDEV_TX_OK;
3093 + priv->tx_skb[tx] = skb;
3094 + priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr;
3096 + if (priv->soc->tx_dma)
3097 + priv->soc->tx_dma(priv, tx, skb->len);
3099 + priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
3101 + if (skb->ip_summed == CHECKSUM_PARTIAL)
3102 + priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM;
3104 + priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM;
3106 + priv->tx_dma[tx].txd4 &= ~0x80;
3108 + dev->stats.tx_packets++;
3109 + dev->stats.tx_bytes += skb->len;
3111 + fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0);
3112 + netdev_sent_queue(dev, skb->len);
3114 + spin_unlock(&priv->page_lock);
3116 + return NETDEV_TX_OK;
3119 +static int fe_poll_rx(struct napi_struct *napi, int budget)
3121 + struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
3122 + int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
3126 + while ((rx < budget) && !complete) {
3127 + idx = (idx + 1) % NUM_DMA_DESC;
3129 + if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) {
3130 + struct sk_buff *new_skb = fe_alloc_skb(priv);
3133 + int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2);
3134 + dma_addr_t dma_addr;
3136 + dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1,
3137 + MAX_RX_LENGTH, DMA_FROM_DEVICE);
3139 + skb_put(priv->rx_skb[idx], pktlen);
3140 + priv->rx_skb[idx]->dev = priv->netdev;
3141 + priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev);
3142 + if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit)
3143 + priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY;
3145 + priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE;
3146 + priv->netdev->stats.rx_packets++;
3147 + priv->netdev->stats.rx_bytes += pktlen;
3148 + netif_receive_skb(priv->rx_skb[idx]);
3150 + priv->rx_skb[idx] = new_skb;
3152 + dma_addr = dma_map_single(&priv->netdev->dev,
3156 + priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr;
3159 + priv->netdev->stats.rx_dropped++;
3162 + if (priv->soc->rx_dma)
3163 + priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH);
3165 + priv->rx_dma[idx].rxd2 = RX_DMA_LSO;
3166 + fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
3175 + napi_complete(&priv->rx_napi);
3176 + fe_int_enable(priv->soc->rx_dly_int);
3182 +static void fe_tx_housekeeping(unsigned long ptr)
3184 + struct net_device *dev = (struct net_device*)ptr;
3185 + struct fe_priv *priv = netdev_priv(dev);
3186 + unsigned int bytes_compl = 0;
3187 + unsigned int pkts_compl = 0;
3189 + spin_lock(&priv->page_lock);
3191 + struct fe_tx_dma *txd;
3193 + txd = &priv->tx_dma[priv->tx_free_idx];
3195 + if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx]))
3198 + bytes_compl += priv->tx_skb[priv->tx_free_idx]->len;
3201 + dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]);
3202 + priv->tx_skb[priv->tx_free_idx] = NULL;
3203 + priv->tx_free_idx++;
3204 + if (priv->tx_free_idx >= NUM_DMA_DESC)
3205 + priv->tx_free_idx = 0;
3208 + netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl);
3209 + spin_unlock(&priv->page_lock);
3211 + fe_int_enable(priv->soc->tx_dly_int);
3214 +static void fe_tx_timeout(struct net_device *dev)
3216 + struct fe_priv *priv = netdev_priv(dev);
3218 + tasklet_schedule(&priv->tx_tasklet);
3219 + priv->netdev->stats.tx_errors++;
3220 + netdev_err(dev, "transmit timed out, waking up the queue\n");
3221 + netif_wake_queue(dev);
3224 +static irqreturn_t fe_handle_irq(int irq, void *dev)
3226 + struct fe_priv *priv = netdev_priv(dev);
3227 + unsigned int status;
3228 + unsigned int mask;
3230 + status = fe_reg_r32(FE_REG_FE_INT_STATUS);
3231 + mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
3233 + if (!(status & mask))
3236 + if (status & priv->soc->rx_dly_int) {
3237 + fe_int_disable(priv->soc->rx_dly_int);
3238 + napi_schedule(&priv->rx_napi);
3241 + if (status & priv->soc->tx_dly_int) {
3242 + fe_int_disable(priv->soc->tx_dly_int);
3243 + tasklet_schedule(&priv->tx_tasklet);
3246 + fe_reg_w32(status, FE_REG_FE_INT_STATUS);
3248 + return IRQ_HANDLED;
3251 +static int fe_hw_init(struct net_device *dev)
3253 + struct fe_priv *priv = netdev_priv(dev);
3256 + err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
3257 + dev_name(priv->device), dev);
3261 + err = fe_alloc_rx(priv);
3263 + err = fe_alloc_tx(priv);
3267 + if (priv->soc->set_mac)
3268 + priv->soc->set_mac(priv, dev->dev_addr);
3270 + fe_hw_set_macaddr(priv, dev->dev_addr);
3272 + fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
3274 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3276 + tasklet_init(&priv->tx_tasklet, fe_tx_housekeeping, (unsigned long)dev);
3278 + if (priv->soc->fwd_config) {
3279 + priv->soc->fwd_config(priv);
3281 + unsigned long sysclk = priv->sysclk;
3284 + netdev_err(dev, "unable to get clock\n");
3288 + sysclk /= FE_US_CYC_CNT_DIVISOR;
3289 + sysclk <<= FE_US_CYC_CNT_SHIFT;
3291 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
3292 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
3295 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG);
3296 + fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
3297 + FE_GDMA1_FWD_CFG);
3298 + fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN),
3300 + fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
3303 + fe_w32(1, FE_FE_RST_GL);
3304 + fe_w32(0, FE_FE_RST_GL);
3309 +static int fe_open(struct net_device *dev)
3311 + struct fe_priv *priv = netdev_priv(dev);
3312 + unsigned long flags;
3315 + spin_lock_irqsave(&priv->page_lock, flags);
3316 + napi_enable(&priv->rx_napi);
3318 + val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
3319 + val |= priv->soc->pdma_glo_cfg;
3320 + fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
3322 + spin_unlock_irqrestore(&priv->page_lock, flags);
3325 + priv->phy->start(priv);
3327 + if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
3328 + netif_carrier_on(dev);
3330 + netif_start_queue(dev);
3331 + fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3336 +static int fe_stop(struct net_device *dev)
3338 + struct fe_priv *priv = netdev_priv(dev);
3339 + unsigned long flags;
3341 + fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
3343 + netif_stop_queue(dev);
3346 + priv->phy->stop(priv);
3348 + spin_lock_irqsave(&priv->page_lock, flags);
3349 + napi_disable(&priv->rx_napi);
3351 + fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
3352 + ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
3353 + FE_REG_PDMA_GLO_CFG);
3354 + spin_unlock_irqrestore(&priv->page_lock, flags);
3359 +static int __init fe_init(struct net_device *dev)
3361 + struct fe_priv *priv = netdev_priv(dev);
3362 + struct device_node *port;
3365 + BUG_ON(!priv->soc->reset_fe);
3366 + priv->soc->reset_fe();
3368 + if (priv->soc->switch_init)
3369 + priv->soc->switch_init(priv);
3371 + net_srandom(jiffies);
3372 + memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
3373 + of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
3375 + err = fe_mdio_init(priv);
3380 + err = priv->phy->connect(priv);
3382 + goto err_mdio_cleanup;
3385 + if (priv->soc->port_init)
3386 + for_each_child_of_node(priv->device->of_node, port)
3387 + if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
3388 + priv->soc->port_init(priv, port);
3390 + err = fe_hw_init(dev);
3392 + goto err_phy_disconnect;
3394 + if (priv->soc->switch_config)
3395 + priv->soc->switch_config(priv);
3399 +err_phy_disconnect:
3401 + priv->phy->disconnect(priv);
3403 + fe_mdio_cleanup(priv);
3408 +static void fe_uninit(struct net_device *dev)
3410 + struct fe_priv *priv = netdev_priv(dev);
3412 + tasklet_kill(&priv->tx_tasklet);
3415 + priv->phy->disconnect(priv);
3416 + fe_mdio_cleanup(priv);
3418 + fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
3419 + free_irq(dev->irq, dev);
3421 + fe_free_dma(priv);
3424 +static const struct net_device_ops fe_netdev_ops = {
3425 + .ndo_init = fe_init,
3426 + .ndo_uninit = fe_uninit,
3427 + .ndo_open = fe_open,
3428 + .ndo_stop = fe_stop,
3429 + .ndo_start_xmit = fe_start_xmit,
3430 + .ndo_tx_timeout = fe_tx_timeout,
3431 + .ndo_set_mac_address = fe_set_mac_address,
3432 + .ndo_change_mtu = eth_change_mtu,
3433 + .ndo_validate_addr = eth_validate_addr,
3436 +static int fe_probe(struct platform_device *pdev)
3438 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3439 + const struct of_device_id *match;
3440 + struct fe_soc_data *soc = NULL;
3441 + struct net_device *netdev;
3442 + struct fe_priv *priv;
3443 + struct clk *sysclk;
3446 + device_reset(&pdev->dev);
3448 + match = of_match_device(of_fe_match, &pdev->dev);
3449 + soc = (struct fe_soc_data *) match->data;
3450 + if (soc->reg_table)
3451 + fe_reg_table = soc->reg_table;
3453 + fe_base = devm_request_and_ioremap(&pdev->dev, res);
3457 + netdev = alloc_etherdev(sizeof(struct fe_priv));
3459 + dev_err(&pdev->dev, "alloc_etherdev failed\n");
3463 + strcpy(netdev->name, "eth%d");
3464 + netdev->netdev_ops = &fe_netdev_ops;
3465 + netdev->base_addr = (unsigned long) fe_base;
3466 + netdev->watchdog_timeo = TX_TIMEOUT;
3467 + netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
3469 + netdev->irq = platform_get_irq(pdev, 0);
3470 + if (netdev->irq < 0) {
3471 + dev_err(&pdev->dev, "no IRQ resource found\n");
3476 + priv = netdev_priv(netdev);
3477 + memset(priv, 0, sizeof(struct fe_priv));
3478 + spin_lock_init(&priv->page_lock);
3480 + sysclk = devm_clk_get(&pdev->dev, NULL);
3481 + if (!IS_ERR(sysclk))
3482 + priv->sysclk = clk_get_rate(sysclk);
3484 + priv->netdev = netdev;
3485 + priv->device = &pdev->dev;
3488 + err = register_netdev(netdev);
3490 + dev_err(&pdev->dev, "error bringing up device\n");
3494 + netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32);
3496 + platform_set_drvdata(pdev, netdev);
3498 + netdev_info(netdev, "done loading\n");
3503 +static int fe_remove(struct platform_device *pdev)
3505 + struct net_device *dev = platform_get_drvdata(pdev);
3506 + struct fe_priv *priv = netdev_priv(dev);
3508 + netif_stop_queue(dev);
3509 + netif_napi_del(&priv->rx_napi);
3511 + unregister_netdev(dev);
3517 +static struct platform_driver fe_driver = {
3518 + .probe = fe_probe,
3519 + .remove = fe_remove,
3521 + .name = "ralink_soc_eth",
3522 + .owner = THIS_MODULE,
3523 + .of_match_table = of_fe_match,
3527 +static int __init init_rtfe(void)
3531 + ret = rtesw_init();
3535 + ret = platform_driver_register(&fe_driver);
3542 +static void __exit exit_rtfe(void)
3544 + platform_driver_unregister(&fe_driver);
3548 +module_init(init_rtfe);
3549 +module_exit(exit_rtfe);
3551 +MODULE_LICENSE("GPL");
3552 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
3553 +MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
3555 +++ b/drivers/net/ethernet/ralink/ralink_soc_eth.h
3558 + * This program is free software; you can redistribute it and/or modify
3559 + * it under the terms of the GNU General Public License as published by
3560 + * the Free Software Foundation; version 2 of the License
3562 + * This program is distributed in the hope that it will be useful,
3563 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3564 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3565 + * GNU General Public License for more details.
3567 + * You should have received a copy of the GNU General Public License
3568 + * along with this program; if not, write to the Free Software
3569 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3571 + * based on Ralink SDK3.3
3572 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3578 +#include <linux/mii.h>
3579 +#include <linux/interrupt.h>
3580 +#include <linux/netdevice.h>
3581 +#include <linux/dma-mapping.h>
3582 +#include <linux/phy.h>
3586 + FE_REG_PDMA_GLO_CFG = 0,
3587 + FE_REG_PDMA_RST_CFG,
3588 + FE_REG_DLY_INT_CFG,
3589 + FE_REG_TX_BASE_PTR0,
3590 + FE_REG_TX_MAX_CNT0,
3591 + FE_REG_TX_CTX_IDX0,
3592 + FE_REG_RX_BASE_PTR0,
3593 + FE_REG_RX_MAX_CNT0,
3594 + FE_REG_RX_CALC_IDX0,
3595 + FE_REG_FE_INT_ENABLE,
3596 + FE_REG_FE_INT_STATUS,
3597 + FE_REG_FE_DMA_VID_BASE,
3601 +#define NUM_DMA_DESC 0x100
3603 +#define FE_DELAY_EN_INT 0x80
3604 +#define FE_DELAY_MAX_INT 0x04
3605 +#define FE_DELAY_MAX_TOUT 0x04
3606 +#define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
3607 +#define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
3608 +#define FE_PSE_FQFC_CFG_INIT 0x80504000
3610 +/* interrupt bits */
3611 +#define FE_CNT_PPE_AF BIT(31)
3612 +#define FE_CNT_GDM_AF BIT(29)
3613 +#define FE_PSE_P2_FC BIT(26)
3614 +#define FE_PSE_BUF_DROP BIT(24)
3615 +#define FE_GDM_OTHER_DROP BIT(23)
3616 +#define FE_PSE_P1_FC BIT(22)
3617 +#define FE_PSE_P0_FC BIT(21)
3618 +#define FE_PSE_FQ_EMPTY BIT(20)
3619 +#define FE_GE1_STA_CHG BIT(18)
3620 +#define FE_TX_COHERENT BIT(17)
3621 +#define FE_RX_COHERENT BIT(16)
3622 +#define FE_TX_DONE_INT3 BIT(11)
3623 +#define FE_TX_DONE_INT2 BIT(10)
3624 +#define FE_TX_DONE_INT1 BIT(9)
3625 +#define FE_TX_DONE_INT0 BIT(8)
3626 +#define FE_RX_DONE_INT0 BIT(2)
3627 +#define FE_TX_DLY_INT BIT(1)
3628 +#define FE_RX_DLY_INT BIT(0)
3630 +#define RT5350_RX_DLY_INT BIT(30)
3631 +#define RT5350_TX_DLY_INT BIT(28)
3634 +#define FE_FE_OFFSET 0x0000
3635 +#define FE_GDMA_OFFSET 0x0020
3636 +#define FE_PSE_OFFSET 0x0040
3637 +#define FE_GDMA2_OFFSET 0x0060
3638 +#define FE_CDMA_OFFSET 0x0080
3639 +#define FE_DMA_VID0 0x00a8
3640 +#define FE_PDMA_OFFSET 0x0100
3641 +#define FE_PPE_OFFSET 0x0200
3642 +#define FE_CMTABLE_OFFSET 0x0400
3643 +#define FE_POLICYTABLE_OFFSET 0x1000
3645 +#define RT5350_PDMA_OFFSET 0x0800
3646 +#define RT5350_SDM_OFFSET 0x0c00
3648 +#define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
3649 +#define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
3650 +#define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
3651 +#define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
3652 +#define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
3653 +#define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
3654 +#define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
3655 +#define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
3657 +#define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
3658 +#define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
3659 +#define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
3660 +#define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
3661 +#define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
3663 +#define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
3664 +#define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
3665 +#define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
3666 +#define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
3667 +#define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
3669 +#define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
3670 +#define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
3671 +#define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
3672 +#define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
3674 +#define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
3675 +#define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
3677 +#define MT7620A_GDMA_OFFSET 0x0600
3678 +#define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
3679 +#define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
3680 +#define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
3681 +#define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
3682 +#define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
3684 +#define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
3685 +#define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
3686 +#define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
3687 +#define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
3688 +#define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
3689 +#define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
3690 +#define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
3691 +#define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
3692 +#define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
3693 +#define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
3694 +#define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
3695 +#define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
3696 +#define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
3697 +#define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
3698 +#define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
3699 +#define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
3700 +#define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
3701 +#define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
3702 +#define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
3703 +#define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
3704 +#define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
3705 +#define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
3706 +#define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
3707 +#define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
3708 +#define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
3709 +#define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
3710 +#define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
3711 +#define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
3712 +#define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
3713 +#define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
3715 +#define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
3716 +#define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
3717 +#define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
3718 +#define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
3719 +#define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
3720 +#define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
3721 +#define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
3722 +#define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
3723 +#define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
3724 +#define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
3725 +#define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
3726 +#define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
3727 +#define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
3728 +#define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
3729 +#define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
3730 +#define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
3731 +#define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
3732 +#define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
3733 +#define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
3734 +#define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
3735 +#define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
3736 +#define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
3737 +#define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
3738 +#define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
3739 +#define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
3740 +#define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
3741 +#define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
3742 +#define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
3744 +#define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00) //Switch DMA configuration
3745 +#define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04) //Switch DMA Rx Ring
3746 +#define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08) //Switch DMA Tx Ring
3747 +#define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C) //Switch MAC address LSB
3748 +#define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10) //Switch MAC Address MSB
3749 +#define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
3750 +#define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
3751 +#define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
3752 +#define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
3753 +#define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
3755 +#define RT5350_SDM_ICS_EN BIT(16)
3756 +#define RT5350_SDM_TCS_EN BIT(17)
3757 +#define RT5350_SDM_UCS_EN BIT(18)
3760 +/* MDIO_CFG register bits */
3761 +#define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
3762 +#define FE_MDIO_CFG_GP1_BP_EN BIT(16)
3763 +#define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
3764 +#define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
3765 +#define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
3766 +#define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
3767 +#define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
3768 +#define FE_MDIO_CFG_GP1_FC_TX BIT(11)
3769 +#define FE_MDIO_CFG_GP1_FC_RX BIT(10)
3770 +#define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
3771 +#define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
3772 +#define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
3773 +#define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
3774 +#define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
3775 +#define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
3776 +#define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
3777 +#define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
3778 +#define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
3779 +#define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
3780 +#define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
3781 +#define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
3782 +#define FE_MDIO_CFG_TX_CLK_SKEW_0 0
3783 +#define FE_MDIO_CFG_TX_CLK_SKEW_200 1
3784 +#define FE_MDIO_CFG_TX_CLK_SKEW_400 2
3785 +#define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
3787 +/* uni-cast port */
3788 +#define FE_GDM1_ICS_EN BIT(22)
3789 +#define FE_GDM1_TCS_EN BIT(21)
3790 +#define FE_GDM1_UCS_EN BIT(20)
3791 +#define FE_GDM1_JMB_EN BIT(19)
3792 +#define FE_GDM1_STRPCRC BIT(16)
3793 +#define FE_GDM1_UFRC_P_CPU (0 << 12)
3794 +#define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
3795 +#define FE_GDM1_UFRC_P_PPE (6 << 12)
3798 +#define FE_ICS_GEN_EN BIT(2)
3799 +#define FE_UCS_GEN_EN BIT(1)
3800 +#define FE_TCS_GEN_EN BIT(0)
3803 +#define FE_PST_DRX_IDX0 BIT(16)
3804 +#define FE_PST_DTX_IDX3 BIT(3)
3805 +#define FE_PST_DTX_IDX2 BIT(2)
3806 +#define FE_PST_DTX_IDX1 BIT(1)
3807 +#define FE_PST_DTX_IDX0 BIT(0)
3809 +#define FE_TX_WB_DDONE BIT(6)
3810 +#define FE_RX_DMA_BUSY BIT(3)
3811 +#define FE_TX_DMA_BUSY BIT(1)
3812 +#define FE_RX_DMA_EN BIT(2)
3813 +#define FE_TX_DMA_EN BIT(0)
3815 +#define FE_PDMA_SIZE_4DWORDS (0 << 4)
3816 +#define FE_PDMA_SIZE_8DWORDS (1 << 4)
3817 +#define FE_PDMA_SIZE_16DWORDS (2 << 4)
3819 +#define FE_US_CYC_CNT_MASK 0xff
3820 +#define FE_US_CYC_CNT_SHIFT 0x8
3821 +#define FE_US_CYC_CNT_DIVISOR 1000000
3823 +#define RX_DMA_PLEN0(_x) (((_x) >> 16) & 0x3fff)
3824 +#define RX_DMA_LSO BIT(30)
3825 +#define RX_DMA_DONE BIT(31)
3826 +#define RX_DMA_L4VALID BIT(30)
3829 + unsigned int rxd1;
3830 + unsigned int rxd2;
3831 + unsigned int rxd3;
3832 + unsigned int rxd4;
3833 +} __packed __aligned(4);
3835 +#define TX_DMA_PLEN0_MASK ((0x3fff) << 16)
3836 +#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
3837 +#define TX_DMA_LSO BIT(30)
3838 +#define TX_DMA_DONE BIT(31)
3839 +#define TX_DMA_QN(_x) ((_x) << 16)
3840 +#define TX_DMA_PN(_x) ((_x) << 24)
3841 +#define TX_DMA_QN_MASK TX_DMA_QN(0x7)
3842 +#define TX_DMA_PN_MASK TX_DMA_PN(0x7)
3843 +#define TX_DMA_CHKSUM (0x7 << 29)
3846 + unsigned int txd1;
3847 + unsigned int txd2;
3848 + unsigned int txd3;
3849 + unsigned int txd4;
3850 +} __packed __aligned(4);
3855 + struct phy_device *phy[8];
3856 + struct device_node *phy_node[8];
3857 + const __be32 *phy_fixed[8];
3864 + int (*connect)(struct fe_priv *priv);
3865 + void (*disconnect)(struct fe_priv *priv);
3866 + void (*start)(struct fe_priv *priv);
3867 + void (*stop)(struct fe_priv *priv);
3872 + unsigned char mac[6];
3873 + const u32 *reg_table;
3875 + void (*reset_fe)(void);
3876 + void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
3877 + void (*fwd_config)(struct fe_priv *priv);
3878 + void (*tx_dma)(struct fe_priv *priv, int idx, int len);
3879 + void (*rx_dma)(struct fe_priv *priv, int idx, int len);
3880 + int (*switch_init)(struct fe_priv *priv);
3881 + int (*switch_config)(struct fe_priv *priv);
3882 + void (*port_init)(struct fe_priv *priv, struct device_node *port);
3883 + int (*has_carrier)(struct fe_priv *priv);
3884 + int (*mdio_init)(struct fe_priv *priv);
3885 + void (*mdio_cleanup)(struct fe_priv *priv);
3886 + int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
3887 + int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
3888 + void (*mdio_adjust_link)(struct fe_priv *priv, int port);
3901 + spinlock_t page_lock;
3903 + struct fe_soc_data *soc;
3904 + struct net_device *netdev;
3905 + struct device *device;
3906 + unsigned long sysclk;
3908 + struct fe_rx_dma *rx_dma;
3909 + struct napi_struct rx_napi;
3910 + struct sk_buff *rx_skb[NUM_DMA_DESC];
3911 + dma_addr_t rx_phys;
3913 + struct fe_tx_dma *tx_dma;
3914 + struct tasklet_struct tx_tasklet;
3915 + struct sk_buff *tx_skb[NUM_DMA_DESC];
3916 + dma_addr_t tx_phys;
3917 + unsigned int tx_free_idx;
3919 + struct fe_phy *phy;
3920 + struct mii_bus *mii_bus;
3921 + int mii_irq[PHY_MAX_ADDR];
3926 +extern const struct of_device_id of_fe_match[];
3928 +void fe_w32(u32 val, unsigned reg);
3929 +u32 fe_r32(unsigned reg);
3931 +#endif /* FE_ETH_H */
3933 +++ b/drivers/net/ethernet/ralink/soc_mt7620.c
3936 + * This program is free software; you can redistribute it and/or modify
3937 + * it under the terms of the GNU General Public License as published by
3938 + * the Free Software Foundation; version 2 of the License
3940 + * This program is distributed in the hope that it will be useful,
3941 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3942 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3943 + * GNU General Public License for more details.
3945 + * You should have received a copy of the GNU General Public License
3946 + * along with this program; if not, write to the Free Software
3947 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3949 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3952 +#include <linux/module.h>
3953 +#include <linux/platform_device.h>
3955 +#include <asm/mach-ralink/ralink_regs.h>
3957 +#include "ralink_soc_eth.h"
3958 +#include "gsw_mt7620a.h"
3960 +#define MT7620A_CDMA_CSG_CFG 0x400
3961 +#define MT7620_DMA_VID (MT7620A_CDMA_CSG_CFG | 0x30)
3962 +#define MT7620A_DMA_2B_OFFSET BIT(31)
3963 +#define MT7620A_RESET_FE BIT(21)
3964 +#define MT7620A_RESET_ESW BIT(23)
3965 +#define MT7620_L4_VALID BIT(23)
3967 +#define SYSC_REG_RESET_CTRL 0x34
3968 +#define MAX_RX_LENGTH 1536
3970 +#define CDMA_ICS_EN BIT(2)
3971 +#define CDMA_UCS_EN BIT(1)
3972 +#define CDMA_TCS_EN BIT(0)
3974 +#define GDMA_ICS_EN BIT(22)
3975 +#define GDMA_TCS_EN BIT(21)
3976 +#define GDMA_UCS_EN BIT(20)
3978 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
3979 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
3980 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
3981 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
3982 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
3983 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
3984 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
3985 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
3986 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
3987 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
3988 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
3989 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
3990 + [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
3993 +static void mt7620_fe_reset(void)
3995 + rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
3996 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
3999 +static void mt7620_fwd_config(struct fe_priv *priv)
4001 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
4002 + fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG);
4003 + fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG);
4006 +static void mt7620_tx_dma(struct fe_priv *priv, int idx, int len)
4009 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(len);
4011 + priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_DONE;
4014 +static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
4016 + priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
4019 +static struct fe_soc_data mt7620_data = {
4020 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4021 + .reset_fe = mt7620_fe_reset,
4022 + .set_mac = mt7620_set_mac,
4023 + .fwd_config = mt7620_fwd_config,
4024 + .tx_dma = mt7620_tx_dma,
4025 + .rx_dma = mt7620_rx_dma,
4026 + .switch_init = mt7620_gsw_probe,
4027 + .switch_config = mt7620_gsw_config,
4028 + .port_init = mt7620_port_init,
4030 + .reg_table = rt5350_reg_table,
4031 + .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
4032 + .rx_dly_int = RT5350_RX_DLY_INT,
4033 + .tx_dly_int = RT5350_TX_DLY_INT,
4034 + .checksum_bit = MT7620_L4_VALID,
4035 + .has_carrier = mt7620a_has_carrier,
4036 + .mdio_read = mt7620_mdio_read,
4037 + .mdio_write = mt7620_mdio_write,
4038 + .mdio_adjust_link = mt7620_mdio_link_adjust,
4041 +const struct of_device_id of_fe_match[] = {
4042 + { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
4046 +MODULE_DEVICE_TABLE(of, of_fe_match);
4048 +++ b/drivers/net/ethernet/ralink/soc_rt2880.c
4051 + * This program is free software; you can redistribute it and/or modify
4052 + * it under the terms of the GNU General Public License as published by
4053 + * the Free Software Foundation; version 2 of the License
4055 + * This program is distributed in the hope that it will be useful,
4056 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4057 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4058 + * GNU General Public License for more details.
4060 + * You should have received a copy of the GNU General Public License
4061 + * along with this program; if not, write to the Free Software
4062 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4064 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4067 +#include <linux/module.h>
4069 +#include <asm/mach-ralink/ralink_regs.h>
4071 +#include "ralink_soc_eth.h"
4072 +#include "mdio_rt2880.h"
4074 +#define SYSC_REG_RESET_CTRL 0x034
4075 +#define RT2880_RESET_FE BIT(18)
4077 +void rt2880_fe_reset(void)
4079 + rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
4082 +struct fe_soc_data rt2880_data = {
4083 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4084 + .reset_fe = rt2880_fe_reset,
4085 + .min_pkt_len = 64,
4086 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4087 + .checksum_bit = RX_DMA_L4VALID,
4088 + .rx_dly_int = FE_RX_DLY_INT,
4089 + .tx_dly_int = FE_TX_DLY_INT,
4090 + .mdio_read = rt2880_mdio_read,
4091 + .mdio_write = rt2880_mdio_write,
4092 + .mdio_adjust_link = rt2880_mdio_link_adjust,
4095 +const struct of_device_id of_fe_match[] = {
4096 + { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
4100 +MODULE_DEVICE_TABLE(of, of_fe_match);
4102 +++ b/drivers/net/ethernet/ralink/soc_rt305x.c
4105 + * This program is free software; you can redistribute it and/or modify
4106 + * it under the terms of the GNU General Public License as published by
4107 + * the Free Software Foundation; version 2 of the License
4109 + * This program is distributed in the hope that it will be useful,
4110 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4111 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4112 + * GNU General Public License for more details.
4114 + * You should have received a copy of the GNU General Public License
4115 + * along with this program; if not, write to the Free Software
4116 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4118 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4121 +#include <linux/module.h>
4123 +#include <asm/mach-ralink/ralink_regs.h>
4125 +#include "ralink_soc_eth.h"
4127 +#define RT305X_RESET_FE BIT(21)
4128 +#define RT305X_RESET_ESW BIT(23)
4129 +#define SYSC_REG_RESET_CTRL 0x034
4131 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
4132 + [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
4133 + [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
4134 + [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
4135 + [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
4136 + [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
4137 + [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
4138 + [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
4139 + [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
4140 + [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
4141 + [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
4142 + [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
4143 + [FE_REG_FE_DMA_VID_BASE] = 0,
4146 +static void rt305x_fe_reset(void)
4148 + rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
4149 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4152 +static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
4154 + unsigned long flags;
4156 + spin_lock_irqsave(&priv->page_lock, flags);
4157 + fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
4158 + fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
4159 + RT5350_SDM_MAC_ADRL);
4160 + spin_unlock_irqrestore(&priv->page_lock, flags);
4163 +static void rt5350_fwd_config(struct fe_priv *priv)
4165 + unsigned long sysclk = priv->sysclk;
4168 + sysclk /= FE_US_CYC_CNT_DIVISOR;
4169 + sysclk <<= FE_US_CYC_CNT_SHIFT;
4171 + fe_w32((fe_r32(FE_FE_GLO_CFG) &
4172 + ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
4176 + fe_w32(fe_r32(RT5350_SDM_CFG) & ~0xffff, RT5350_SDM_CFG);
4177 + fe_w32(fe_r32(RT5350_SDM_CFG) | RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN,
4181 +static void rt5350_fe_reset(void)
4183 + rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
4184 + rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
4187 +static struct fe_soc_data rt3050_data = {
4188 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4189 + .reset_fe = rt305x_fe_reset,
4190 + .min_pkt_len = 64,
4191 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4192 + .checksum_bit = RX_DMA_L4VALID,
4193 + .rx_dly_int = FE_RX_DLY_INT,
4194 + .tx_dly_int = FE_TX_DLY_INT,
4197 +static struct fe_soc_data rt5350_data = {
4198 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4199 + .reg_table = rt5350_reg_table,
4200 + .reset_fe = rt5350_fe_reset,
4201 + .set_mac = rt5350_set_mac,
4202 + .fwd_config = rt5350_fwd_config,
4203 + .min_pkt_len = 64,
4204 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4205 + .checksum_bit = RX_DMA_L4VALID,
4206 + .rx_dly_int = RT5350_RX_DLY_INT,
4207 + .tx_dly_int = RT5350_TX_DLY_INT,
4210 +const struct of_device_id of_fe_match[] = {
4211 + { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
4212 + { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
4216 +MODULE_DEVICE_TABLE(of, of_fe_match);
4218 +++ b/drivers/net/ethernet/ralink/soc_rt3883.c
4221 + * This program is free software; you can redistribute it and/or modify
4222 + * it under the terms of the GNU General Public License as published by
4223 + * the Free Software Foundation; version 2 of the License
4225 + * This program is distributed in the hope that it will be useful,
4226 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4227 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4228 + * GNU General Public License for more details.
4230 + * You should have received a copy of the GNU General Public License
4231 + * along with this program; if not, write to the Free Software
4232 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4234 + * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4237 +#include <linux/module.h>
4239 +#include <asm/mach-ralink/ralink_regs.h>
4241 +#include "ralink_soc_eth.h"
4242 +#include "mdio_rt2880.h"
4244 +#define RT3883_SYSC_REG_RSTCTRL 0x34
4245 +#define RT3883_RSTCTRL_FE BIT(21)
4247 +static void rt3883_fe_reset(void)
4251 + t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
4252 + t |= RT3883_RSTCTRL_FE;
4253 + rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
4255 + t &= ~RT3883_RSTCTRL_FE;
4256 + rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
4259 +static struct fe_soc_data rt3883_data = {
4260 + .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
4261 + .reset_fe = rt3883_fe_reset,
4262 + .min_pkt_len = 64,
4263 + .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
4264 + .rx_dly_int = FE_RX_DLY_INT,
4265 + .tx_dly_int = FE_TX_DLY_INT,
4266 + .checksum_bit = RX_DMA_L4VALID,
4267 + .mdio_read = rt2880_mdio_read,
4268 + .mdio_write = rt2880_mdio_write,
4269 + .mdio_adjust_link = rt2880_mdio_link_adjust,
4270 + .port_init = rt2880_port_init,
4273 +const struct of_device_id of_fe_match[] = {
4274 + { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
4278 +MODULE_DEVICE_TABLE(of, of_fe_match);
4281 +++ b/drivers/net/ethernet/ralink/mt7530.c
4284 + * This program is free software; you can redistribute it and/or
4285 + * modify it under the terms of the GNU General Public License
4286 + * as published by the Free Software Foundation; either version 2
4287 + * of the License, or (at your option) any later version.
4289 + * This program is distributed in the hope that it will be useful,
4290 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4291 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4292 + * GNU General Public License for more details.
4294 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
4297 +#include <linux/if.h>
4298 +#include <linux/module.h>
4299 +#include <linux/init.h>
4300 +#include <linux/list.h>
4301 +#include <linux/if_ether.h>
4302 +#include <linux/skbuff.h>
4303 +#include <linux/netdevice.h>
4304 +#include <linux/netlink.h>
4305 +#include <linux/bitops.h>
4306 +#include <net/genetlink.h>
4307 +#include <linux/switch.h>
4308 +#include <linux/delay.h>
4309 +#include <linux/phy.h>
4310 +#include <linux/netdevice.h>
4311 +#include <linux/etherdevice.h>
4312 +#include <linux/lockdep.h>
4313 +#include <linux/workqueue.h>
4314 +#include <linux/of_device.h>
4316 +#include "mt7530.h"
4318 +#define MT7530_CPU_PORT 6
4319 +#define MT7530_NUM_PORTS 7
4320 +#define MT7530_NUM_VLANS 16
4321 +#define MT7530_NUM_VIDS 16
4323 +#define REG_ESW_VLAN_VTCR 0x90
4324 +#define REG_ESW_VLAN_VAWD1 0x94
4325 +#define REG_ESW_VLAN_VAWD2 0x98
4328 + /* Global attributes. */
4329 + MT7530_ATTR_ENABLE_VLAN,
4332 +struct mt7530_port {
4336 +struct mt7530_vlan {
4340 +struct mt7530_priv {
4341 + void __iomem *base;
4342 + struct mii_bus *bus;
4343 + struct switch_dev swdev;
4345 + bool global_vlan_enable;
4346 + struct mt7530_vlan vlans[MT7530_NUM_VLANS];
4347 + struct mt7530_port ports[MT7530_NUM_PORTS];
4350 +struct mt7530_mapping {
4354 +} mt7530_defaults[] = {
4357 + .pvids = { 1, 1, 1, 1, 2, 1 },
4358 + .vlans = { 0, 0x4f, 0x50 },
4361 + .pvids = { 2, 1, 1, 1, 1, 1 },
4362 + .vlans = { 0, 0x5e, 0x41 },
4366 +struct mt7530_mapping*
4367 +mt7530_find_mapping(struct device_node *np)
4372 + if (of_property_read_string(np, "ralink,port-map", &map))
4375 + for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
4376 + if (!strcmp(map, mt7530_defaults[i].name))
4377 + return &mt7530_defaults[i];
4383 +mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
4387 + mt7530->global_vlan_enable = 1;
4389 + for (i = 0; i < 6; i++)
4390 + mt7530->ports[i].pvid = map->pvids[i];
4391 + for (i = 0; i < 8; i++)
4392 + mt7530->vlans[i].ports = map->vlans[i];
4396 +mt7530_reset_switch(struct switch_dev *dev)
4398 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4400 + memset(priv->ports, 0, sizeof(priv->ports));
4401 + memset(priv->vlans, 0, sizeof(priv->vlans));
4407 +mt7530_get_vlan_enable(struct switch_dev *dev,
4408 + const struct switch_attr *attr,
4409 + struct switch_val *val)
4411 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4413 + val->value.i = priv->global_vlan_enable;
4419 +mt7530_set_vlan_enable(struct switch_dev *dev,
4420 + const struct switch_attr *attr,
4421 + struct switch_val *val)
4423 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4425 + priv->global_vlan_enable = val->value.i != 0;
4431 +mt7530_r32(struct mt7530_priv *priv, u32 reg)
4436 + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
4437 + low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
4438 + high = mdiobus_read(priv->bus, 0x1f, 0x10);
4440 + return (high << 16) | (low & 0xffff);
4443 + return ioread32(priv->base + reg);
4447 +mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
4450 + mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
4451 + mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
4452 + mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
4456 + iowrite32(val, priv->base + reg);
4460 +mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
4464 + mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
4466 + for (i = 0; i < 20; i++) {
4467 + u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
4469 + if ((val & BIT(31)) == 0)
4475 + printk("mt7530: vtcr timeout\n");
4479 +mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
4481 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4483 + if (port >= MT7530_NUM_PORTS)
4486 + *val = mt7530_r32(priv, 0x2014 + (0x100 * port));
4493 +mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
4495 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4497 + if (port >= MT7530_NUM_PORTS)
4500 + priv->ports[port].pvid = pvid;
4506 +mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
4508 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4514 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VIDS)
4517 + mt7530_vtcr(priv, 0, val->port_vlan);
4518 + member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
4522 + for (i = 0; i < MT7530_NUM_PORTS; i++) {
4523 + struct switch_port *p;
4524 + if (!(member & BIT(i)))
4527 + p = &val->value.ports[val->len++];
4536 +mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
4538 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4542 + if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VIDS ||
4543 + val->len > MT7530_NUM_PORTS)
4546 + for (i = 0; i < val->len; i++) {
4547 + struct switch_port *p = &val->value.ports[i];
4549 + if (p->id >= MT7530_NUM_PORTS)
4552 + ports |= BIT(p->id);
4554 + priv->vlans[val->port_vlan].ports = ports;
4560 +mt7530_apply_config(struct switch_dev *dev)
4562 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4565 + if (!priv->global_vlan_enable) {
4566 + mt7530_w32(priv, 0x2004, 0xff000);
4567 + mt7530_w32(priv, 0x2104, 0xff000);
4568 + mt7530_w32(priv, 0x2204, 0xff000);
4569 + mt7530_w32(priv, 0x2304, 0xff000);
4570 + mt7530_w32(priv, 0x2404, 0xff000);
4571 + mt7530_w32(priv, 0x2504, 0xff000);
4572 + mt7530_w32(priv, 0x2604, 0xff000);
4573 + mt7530_w32(priv, 0x2010, 0x810000c);
4574 + mt7530_w32(priv, 0x2110, 0x810000c);
4575 + mt7530_w32(priv, 0x2210, 0x810000c);
4576 + mt7530_w32(priv, 0x2310, 0x810000c);
4577 + mt7530_w32(priv, 0x2410, 0x810000c);
4578 + mt7530_w32(priv, 0x2510, 0x810000c);
4579 + mt7530_w32(priv, 0x2610, 0x810000c);
4583 + // LAN/WAN ports as security mode
4584 + mt7530_w32(priv, 0x2004, 0xff0003);
4585 + mt7530_w32(priv, 0x2104, 0xff0003);
4586 + mt7530_w32(priv, 0x2204, 0xff0003);
4587 + mt7530_w32(priv, 0x2304, 0xff0003);
4588 + mt7530_w32(priv, 0x2404, 0xff0003);
4589 + mt7530_w32(priv, 0x2504, 0xff0003);
4590 + // LAN/WAN ports as transparent port
4591 + mt7530_w32(priv, 0x2010, 0x810000c0);
4592 + mt7530_w32(priv, 0x2110, 0x810000c0);
4593 + mt7530_w32(priv, 0x2210, 0x810000c0);
4594 + mt7530_w32(priv, 0x2310, 0x810000c0);
4595 + mt7530_w32(priv, 0x2410, 0x810000c0);
4596 + mt7530_w32(priv, 0x2510, 0x810000c0);
4598 + // set CPU/P7 port as user port
4599 + mt7530_w32(priv, 0x2610, 0x81000000);
4600 + mt7530_w32(priv, 0x2710, 0x81000000);
4602 + mt7530_w32(priv, 0x2604, 0x20ff0003);
4603 + mt7530_w32(priv, 0x2704, 0x20ff0003);
4604 + mt7530_w32(priv, 0x2610, 0x81000000);
4606 + for (i = 0; i < MT7530_NUM_VLANS; i++) {
4607 + u8 ports = priv->vlans[i].ports;
4608 + u32 val = mt7530_r32(priv, 0x100 + 4 * (i / 2));
4617 + mt7530_w32(priv, 0x100 + 4 * (i / 2), val);
4620 + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, BIT(30) | (ports << 16) | BIT(0));
4622 + mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
4624 + mt7530_vtcr(priv, 1, i);
4627 + for (i = 0; i < MT7530_NUM_PORTS; i++)
4628 + mt7530_w32(priv, 0x2014 + (0x100 * i), 0x10000 | priv->ports[i].pvid);
4634 +mt7530_get_port_link(struct switch_dev *dev, int port,
4635 + struct switch_port_link *link)
4637 + struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
4640 + if (port < 0 || port >= MT7530_NUM_PORTS)
4643 + pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
4645 + link->link = pmsr & 1;
4646 + link->duplex = (pmsr >> 1) & 1;
4647 + speed = (pmsr >> 2) & 3;
4651 + link->speed = SWITCH_PORT_SPEED_10;
4654 + link->speed = SWITCH_PORT_SPEED_100;
4657 + case 3: /* forced gige speed can be 2 or 3 */
4658 + link->speed = SWITCH_PORT_SPEED_1000;
4661 + link->speed = SWITCH_PORT_SPEED_UNKNOWN;
4668 +static const struct switch_attr mt7530_global[] = {
4670 + .type = SWITCH_TYPE_INT,
4671 + .name = "enable_vlan",
4672 + .description = "VLAN mode (1:enabled)",
4674 + .id = MT7530_ATTR_ENABLE_VLAN,
4675 + .get = mt7530_get_vlan_enable,
4676 + .set = mt7530_set_vlan_enable,
4680 +static const struct switch_attr mt7530_port[] = {
4683 +static const struct switch_attr mt7530_vlan[] = {
4686 +static const struct switch_dev_ops mt7530_ops = {
4688 + .attr = mt7530_global,
4689 + .n_attr = ARRAY_SIZE(mt7530_global),
4692 + .attr = mt7530_port,
4693 + .n_attr = ARRAY_SIZE(mt7530_port),
4696 + .attr = mt7530_vlan,
4697 + .n_attr = ARRAY_SIZE(mt7530_vlan),
4699 + .get_vlan_ports = mt7530_get_vlan_ports,
4700 + .set_vlan_ports = mt7530_set_vlan_ports,
4701 + .get_port_pvid = mt7530_get_port_pvid,
4702 + .set_port_pvid = mt7530_set_port_pvid,
4703 + .get_port_link = mt7530_get_port_link,
4704 + .apply_config = mt7530_apply_config,
4705 + .reset_switch = mt7530_reset_switch,
4709 +mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus)
4711 + struct switch_dev *swdev;
4712 + struct mt7530_priv *mt7530;
4713 + struct mt7530_mapping *map;
4716 + if (bus && bus->phy_map[0x1f]->phy_id != 0x1beef)
4719 + mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
4723 + mt7530->base = base;
4724 + mt7530->bus = bus;
4725 + mt7530->global_vlan_enable = 1;
4727 + swdev = &mt7530->swdev;
4728 + swdev->name = "mt7530";
4729 + swdev->alias = "mt7530";
4730 + swdev->cpu_port = MT7530_CPU_PORT;
4731 + swdev->ports = MT7530_NUM_PORTS;
4732 + swdev->vlans = MT7530_NUM_VLANS;
4733 + swdev->ops = &mt7530_ops;
4735 + ret = register_switch(swdev, NULL);
4737 + dev_err(dev, "failed to register mt7530\n");
4741 + dev_info(dev, "loaded mt7530 driver\n");
4743 + map = mt7530_find_mapping(dev->of_node);
4745 + mt7530_apply_mapping(mt7530, map);
4746 + mt7530_apply_config(swdev);
4751 +++ b/drivers/net/ethernet/ralink/mt7530.h
4754 + * This program is free software; you can redistribute it and/or
4755 + * modify it under the terms of the GNU General Public License
4756 + * as published by the Free Software Foundation; either version 2
4757 + * of the License, or (at your option) any later version.
4759 + * This program is distributed in the hope that it will be useful,
4760 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4761 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4762 + * GNU General Public License for more details.
4764 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
4767 +#ifndef _MT7530_H__
4768 +#define _MT7530_H__
4770 +int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus);