target/linux/ramips/patches-3.10/0212-GPIO-ralink-add-mt7621-gpio-controller.patch

   1 From 2a9b5a9fc1a0707b95dbe61dd1c30b9337cb457d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 16 Mar 2014 05:26:34 +0000
   4 Subject: [PATCH 212/215] GPIO: ralink: add mt7621 gpio controller
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  arch/mips/Kconfig          |    5 +-
   9  drivers/gpio/Kconfig       |    6 ++
  10  drivers/gpio/Makefile      |    1 +
  11  drivers/gpio/gpio-mt7621.c |  183 ++++++++++++++++++++++++++++++++++++++++++++
  12  4 files changed, 194 insertions(+), 1 deletion(-)
  13  create mode 100644 drivers/gpio/gpio-mt7621.c
  14
  15 --- a/arch/mips/Kconfig
  16 +++ b/arch/mips/Kconfig
  17 @@ -448,7 +448,10 @@ config RALINK
  18         select ARCH_REQUIRE_GPIOLIB
  19         select PINCTRL
  20         select PINCTRL_RT2880
  21 -
  22 +       select ARCH_HAS_RESET_CONTROLLER
  23 +       select RESET_CONTROLLER
  24 +       select ARCH_REQUIRE_GPIOLIB
  25 +
  26  config SGI_IP22
  27         bool "SGI IP22 (Indy/Indigo2)"
  28         select FW_ARC
  29 --- a/drivers/gpio/Kconfig
  30 +++ b/drivers/gpio/Kconfig
  31 @@ -710,6 +710,12 @@ config GPIO_MSIC
  32           Enable support for GPIO on intel MSIC controllers found in
  33           intel MID devices
  34
  35 +config GPIO_MT7621
  36 +       bool "Mediatek GPIO Support"
  37 +       depends on SOC_MT7621
  38 +       help
  39 +         Say yes here to support the Mediatek SoC GPIO device
  40 +
  41  comment "USB GPIO expanders:"
  42
  43  config GPIO_VIPERBOARD
  44 --- a/drivers/gpio/Makefile
  45 +++ b/drivers/gpio/Makefile
  46 @@ -88,3 +88,4 @@ obj-$(CONFIG_GPIO_WM831X)     += gpio-wm831x
  47  obj-$(CONFIG_GPIO_WM8350)      += gpio-wm8350.o
  48  obj-$(CONFIG_GPIO_WM8994)      += gpio-wm8994.o
  49  obj-$(CONFIG_GPIO_XILINX)      += gpio-xilinx.o
  50 +obj-$(CONFIG_GPIO_MT7621)      += gpio-mt7621.o
  51 --- /dev/null
  52 +++ b/drivers/gpio/gpio-mt7621.c
  53 @@ -0,0 +1,183 @@
  54 +/*
  55 + * This program is free software; you can redistribute it and/or modify it
  56 + * under the terms of the GNU General Public License version 2 as published
  57 + * by the Free Software Foundation.
  58 + *
  59 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
  60 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
  61 + */
  62 +
  63 +#include <linux/io.h>
  64 +#include <linux/err.h>
  65 +#include <linux/gpio.h>
  66 +#include <linux/module.h>
  67 +#include <linux/of_irq.h>
  68 +#include <linux/spinlock.h>
  69 +#include <linux/irqdomain.h>
  70 +#include <linux/interrupt.h>
  71 +#include <linux/platform_device.h>
  72 +
  73 +#define MTK_BANK_WIDTH         32
  74 +
  75 +enum mediatek_gpio_reg {
  76 +       GPIO_REG_CTRL = 0,
  77 +       GPIO_REG_POL,
  78 +       GPIO_REG_DATA,
  79 +       GPIO_REG_DSET,
  80 +       GPIO_REG_DCLR,
  81 +};
  82 +
  83 +static void __iomem *mtk_gc_membase;
  84 +
  85 +struct mtk_gc {
  86 +       struct gpio_chip chip;
  87 +       spinlock_t lock;
  88 +       int bank;
  89 +};
  90 +
  91 +int
  92 +gpio_to_irq(unsigned gpio)
  93 +{
  94 +       return -1;
  95 +}
  96 +
  97 +static inline struct mtk_gc
  98 +*to_mediatek_gpio(struct gpio_chip *chip)
  99 +{
 100 +       struct mtk_gc *mgc;
 101 +
 102 +       mgc = container_of(chip, struct mtk_gc, chip);
 103 +
 104 +       return mgc;
 105 +}
 106 +
 107 +static inline void
 108 +mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
 109 +{
 110 +       iowrite32(val, mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
 111 +}
 112 +
 113 +static inline u32
 114 +mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
 115 +{
 116 +       return ioread32(mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
 117 +}
 118 +
 119 +static void
 120 +mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 121 +{
 122 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 123 +
 124 +       mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
 125 +}
 126 +
 127 +static int
 128 +mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
 129 +{
 130 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 131 +
 132 +       return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
 133 +}
 134 +
 135 +static int
 136 +mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 137 +{
 138 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 139 +       unsigned long flags;
 140 +       u32 t;
 141 +
 142 +       spin_lock_irqsave(&rg->lock, flags);
 143 +       t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
 144 +       t &= ~BIT(offset);
 145 +       mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
 146 +       spin_unlock_irqrestore(&rg->lock, flags);
 147 +
 148 +       return 0;
 149 +}
 150 +
 151 +static int
 152 +mediatek_gpio_direction_output(struct gpio_chip *chip,
 153 +                                       unsigned offset, int value)
 154 +{
 155 +       struct mtk_gc *rg = to_mediatek_gpio(chip);
 156 +       unsigned long flags;
 157 +       u32 t;
 158 +
 159 +       spin_lock_irqsave(&rg->lock, flags);
 160 +       t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
 161 +       t |= BIT(offset);
 162 +       mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
 163 +       mediatek_gpio_set(chip, offset, value);
 164 +       spin_unlock_irqrestore(&rg->lock, flags);
 165 +
 166 +       return 0;
 167 +}
 168 +
 169 +static int
 170 +mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
 171 +{
 172 +       const __be32 *id = of_get_property(bank, "reg", NULL);
 173 +       struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
 174 +                               sizeof(struct mtk_gc), GFP_KERNEL);
 175 +       if (!rg || !id)
 176 +               return -ENOMEM;
 177 +
 178 +       spin_lock_init(&rg->lock);
 179 +
 180 +       rg->chip.dev = &pdev->dev;
 181 +       rg->chip.label = dev_name(&pdev->dev);
 182 +       rg->chip.of_node = bank;
 183 +       rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
 184 +       rg->chip.ngpio = MTK_BANK_WIDTH;
 185 +       rg->chip.direction_input = mediatek_gpio_direction_input;
 186 +       rg->chip.direction_output = mediatek_gpio_direction_output;
 187 +       rg->chip.get = mediatek_gpio_get;
 188 +       rg->chip.set = mediatek_gpio_set;
 189 +
 190 +       /* set polarity to low for all gpios */
 191 +       mtk_gpio_w32(rg, GPIO_REG_POL, 0);
 192 +
 193 +       dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
 194 +
 195 +       return gpiochip_add(&rg->chip);
 196 +}
 197 +
 198 +static int
 199 +mediatek_gpio_probe(struct platform_device *pdev)
 200 +{
 201 +       struct device_node *bank, *np = pdev->dev.of_node;
 202 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 203 +
 204 +       mtk_gc_membase = devm_request_and_ioremap(&pdev->dev, res);
 205 +       if (IS_ERR(mtk_gc_membase))
 206 +               return PTR_ERR(mtk_gc_membase);
 207 +
 208 +       for_each_child_of_node(np, bank)
 209 +               if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
 210 +                       mediatek_gpio_bank_probe(pdev, bank);
 211 +
 212 +       return 0;
 213 +}
 214 +
 215 +static const struct of_device_id mediatek_gpio_match[] = {
 216 +       { .compatible = "mtk,mt7621-gpio" },
 217 +       {},
 218 +};
 219 +MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
 220 +
 221 +static struct platform_driver mediatek_gpio_driver = {
 222 +       .probe = mediatek_gpio_probe,
 223 +       .driver = {
 224 +               .name = "mt7621_gpio",
 225 +               .owner = THIS_MODULE,
 226 +               .of_match_table = mediatek_gpio_match,
 227 +       },
 228 +};
 229 +
 230 +static int __init
 231 +mediatek_gpio_init(void)
 232 +{
 233 +       return platform_driver_register(&mediatek_gpio_driver);
 234 +}
 235 +
 236 +subsys_initcall(mediatek_gpio_init);