1 From a5fc495c8dc199ffa997d43331693a5b7ee07270 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 17 Nov 2013 17:41:46 +0100
4 Subject: [PATCH] ralink: add mt7620 nand driver
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/mtd/maps/Kconfig | 4 +
9 drivers/mtd/maps/Makefile | 2 +
10 drivers/mtd/maps/ralink_nand.c | 2136 ++++++++++++++++++++++++++++++++++++++++
11 drivers/mtd/maps/ralink_nand.h | 232 +++++
12 drivers/mtd/nand/Makefile | 2 +-
13 5 files changed, 2375 insertions(+), 1 deletion(-)
14 create mode 100644 drivers/mtd/maps/ralink_nand.c
15 create mode 100644 drivers/mtd/maps/ralink_nand.h
17 Index: linux-3.10.18/drivers/mtd/maps/Kconfig
18 ===================================================================
19 --- linux-3.10.18.orig/drivers/mtd/maps/Kconfig 2013-11-17 17:50:02.049020043 +0100
20 +++ linux-3.10.18/drivers/mtd/maps/Kconfig 2013-11-17 17:51:50.545024547 +0100
23 If compiled as a module, it will be called latch-addr-flash.
25 +config MTD_NAND_MT7620
26 + tristate "Support for NAND on Mediatek MT7620"
27 + depends on RALINK && SOC_MT7620
30 Index: linux-3.10.18/drivers/mtd/maps/Makefile
31 ===================================================================
32 --- linux-3.10.18.orig/drivers/mtd/maps/Makefile 2013-11-17 17:50:02.049020043 +0100
33 +++ linux-3.10.18/drivers/mtd/maps/Makefile 2013-11-17 17:51:50.545024547 +0100
35 obj-$(CONFIG_MTD_GPIO_ADDR) += gpio-addr-flash.o
36 obj-$(CONFIG_MTD_LATCH_ADDR) += latch-addr-flash.o
37 obj-$(CONFIG_MTD_LANTIQ) += lantiq-flash.o
38 +obj-$(CONFIG_MTD_NAND_MT7620) += ralink_nand.o
40 Index: linux-3.10.18/drivers/mtd/maps/ralink_nand.c
41 ===================================================================
42 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
43 +++ linux-3.10.18/drivers/mtd/maps/ralink_nand.c 2013-11-17 17:51:50.549024547 +0100
46 +#include <linux/device.h>
48 +#include <linux/slab.h>
49 +#include <linux/mtd/mtd.h>
50 +#include <linux/delay.h>
51 +#include <linux/module.h>
52 +#include <linux/interrupt.h>
53 +#include <linux/dma-mapping.h>
54 +#include <linux/mtd/partitions.h>
56 +#include <linux/delay.h>
57 +#include <linux/sched.h>
58 +#include <linux/of.h>
59 +#include <linux/platform_device.h>
61 +#include "ralink_nand.h"
62 +#ifdef RANDOM_GEN_BAD_BLOCK
63 +#include <linux/random.h>
66 +#define LARGE_MTD_BOOT_PART_SIZE (CFG_BLOCKSIZE<<2)
67 +#define LARGE_MTD_CONFIG_PART_SIZE (CFG_BLOCKSIZE<<2)
68 +#define LARGE_MTD_FACTORY_PART_SIZE (CFG_BLOCKSIZE<<1)
71 +#define BLOCK_ALIGNED(a) ((a) & (CFG_BLOCKSIZE - 1))
73 +#define READ_STATUS_RETRY 1000
75 +struct mtd_info *ranfc_mtd = NULL;
79 +static int ranfc_bbt = 1;
80 +#if defined (WORKAROUND_RX_BUF_OV)
81 +static int ranfc_verify = 1;
83 +static u32 nand_addrlen;
86 +module_param(ranfc_debug, int, 0644);
87 +module_param(ranfc_bbt, int, 0644);
88 +module_param(ranfc_verify, int, 0644);
92 +#define ra_dbg(args...) do { if (ranfc_debug) printk(args); } while(0)
94 +#define ra_dbg(args...)
97 +#define CLEAR_INT_STATUS() ra_outl(NFC_INT_ST, ra_inl(NFC_INT_ST))
98 +#define NFC_TRANS_DONE() (ra_inl(NFC_INT_ST) & INT_ST_ND_DONE)
100 +int is_nand_page_2048 = 0;
101 +const unsigned int nand_size_map[2][3] = {{25, 30, 30}, {20, 27, 30}};
103 +static int nfc_wait_ready(int snooze_ms);
105 +static const char * const mtk_probe_types[] = { "cmdlinepart", "ofpart", NULL };
110 +static int nfc_chip_reset(void)
114 + //ra_dbg("%s:\n", __func__);
116 + // reset nand flash
117 + ra_outl(NFC_CMD1, 0x0);
118 + ra_outl(NFC_CMD2, 0xff);
119 + ra_outl(NFC_ADDR, 0x0);
120 + ra_outl(NFC_CONF, 0x0411);
122 + status = nfc_wait_ready(5); //erase wait 5us
123 + if (status & NAND_STATUS_FAIL) {
124 + printk("%s: fail \n", __func__);
127 + return (int)(status & NAND_STATUS_FAIL);
134 + * clear NFC and flash chip.
136 +static int nfc_all_reset(void)
140 + ra_dbg("%s: \n", __func__);
142 + // reset controller
143 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x02); //clear data buffer
144 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) & ~0x02); //clear data buffer
146 + CLEAR_INT_STATUS();
148 + retry = READ_STATUS_RETRY;
149 + while ((ra_inl(NFC_INT_ST) & 0x02) != 0x02 && retry--);
151 + printk("nfc_all_reset: clean buffer fail \n");
155 + retry = READ_STATUS_RETRY;
156 + while ((ra_inl(NFC_STATUS) & 0x1) != 0x0 && retry--) { //fixme, controller is busy ?
165 +/** NOTICE: only called by nfc_wait_ready().
166 + * @return -1, nfc can not get transction done
169 +static int _nfc_read_status(char *status)
171 + unsigned long cmd1, conf;
172 + int int_st, nfc_st;
176 + conf = 0x000101 | (1 << 20);
178 + //fixme, should we check nfc status?
179 + CLEAR_INT_STATUS();
181 + ra_outl(NFC_CMD1, cmd1);
182 + ra_outl(NFC_CONF, conf);
185 + * 1. since we have no wired ready signal, directly
186 + * calling this function is not gurantee to read right status under ready state.
187 + * 2. the other side, we can not determine how long to become ready, this timeout retry is nonsense.
188 + * 3. SUGGESTION: call nfc_read_status() from nfc_wait_ready(),
189 + * that is aware about caller (in sementics) and has snooze plused nfc ND_DONE.
191 + retry = READ_STATUS_RETRY;
193 + nfc_st = ra_inl(NFC_STATUS);
194 + int_st = ra_inl(NFC_INT_ST);
197 + } while (!(int_st & INT_ST_RX_BUF_RDY) && retry--);
199 + if (!(int_st & INT_ST_RX_BUF_RDY)) {
200 + printk("nfc_read_status: NFC fail, int_st(%x), retry:%x. nfc:%x, reset nfc and flash. \n",
201 + int_st, retry, nfc_st);
203 + *status = NAND_STATUS_FAIL;
207 + *status = (char)(le32_to_cpu(ra_inl(NFC_DATA)) & 0x0ff);
212 + * @return !0, chip protect.
213 + * @return 0, chip not protected.
215 +static int nfc_check_wp(void)
217 + /* Check the WP bit */
218 +#if !defined CONFIG_NOT_SUPPORT_WP
219 + return !!(ra_inl(NFC_CTRL) & 0x01);
224 + ret = _nfc_read_status(&result);
225 + //FIXME, if ret < 0
227 + return !(result & NAND_STATUS_WP);
231 +#if !defined CONFIG_NOT_SUPPORT_RB
233 + * @return !0, chip ready.
234 + * @return 0, chip busy.
236 +static int nfc_device_ready(void)
238 + /* Check the ready */
239 + return !!(ra_inl(NFC_STATUS) & 0x04);
245 + * generic function to get data from flash.
246 + * @return data length reading from flash.
248 +static int _ra_nand_pull_data(char *buf, int len, int use_gdma)
250 +#ifdef RW_DATA_BY_BYTE
253 + __u32 *p = (__u32 *)buf;
256 + unsigned int ret_data;
259 + // receive data by use_gdma
261 + //if (_ra_nand_dma_pull((unsigned long)p, len)) {
263 + printk("%s: fail \n", __func__);
264 + len = -1; //return error
270 + //fixme: retry count size?
271 + retry = READ_STATUS_RETRY;
274 + int_st = ra_inl(NFC_INT_ST);
275 + if (int_st & INT_ST_RX_BUF_RDY) {
277 + ret_data = ra_inl(NFC_DATA);
278 + ra_outl(NFC_INT_ST, INT_ST_RX_BUF_RDY);
279 +#ifdef RW_DATA_BY_BYTE
280 + ret_size = sizeof(unsigned int);
281 + ret_size = min(ret_size, len);
283 + while (ret_size-- > 0) {
284 + //nfc is little endian
285 + *p++ = ret_data & 0x0ff;
289 + ret_size = min(len, 4);
294 + __u8 *q = (__u8 *)p;
295 + while (ret_size-- > 0) {
296 + *q++ = ret_data & 0x0ff;
302 + retry = READ_STATUS_RETRY;
304 + else if (int_st & INT_ST_ND_DONE) {
314 +#ifdef RW_DATA_BY_BYTE
315 + return (int)(p - buf);
317 + return ((int)p - (int)buf);
322 + * generic function to put data into flash.
323 + * @return data length writing into flash.
325 +static int _ra_nand_push_data(char *buf, int len, int use_gdma)
327 +#ifdef RW_DATA_BY_BYTE
330 + __u32 *p = (__u32 *)buf;
333 + unsigned int tx_data = 0;
334 + int tx_size, iter = 0;
336 + // receive data by use_gdma
338 + //if (_ra_nand_dma_push((unsigned long)p, len))
341 + printk("%s: fail \n", __func__);
346 + retry = READ_STATUS_RETRY;
348 + int_st = ra_inl(NFC_INT_ST);
349 + if (int_st & INT_ST_TX_BUF_RDY) {
350 +#ifdef RW_DATA_BY_BYTE
351 + tx_size = min(len, (int)sizeof(unsigned long));
352 + for (iter = 0; iter < tx_size; iter++) {
353 + tx_data |= (*p++ << (8*iter));
356 + tx_size = min(len, 4);
360 + __u8 *q = (__u8 *)p;
361 + for (iter = 0; iter < tx_size; iter++)
362 + tx_data |= (*q++ << (8*iter));
366 + ra_outl(NFC_INT_ST, INT_ST_TX_BUF_RDY);
367 + ra_outl(NFC_DATA, tx_data);
369 + retry = READ_STATUS_RETRY;
371 + else if (int_st & INT_ST_ND_DONE) {
377 + ra_dbg("%s p:%p buf:%p \n", __func__, p, buf);
384 +#ifdef RW_DATA_BY_BYTE
385 + return (int)(p - buf);
387 + return ((int)p - (int)buf);
392 +static int nfc_select_chip(struct ra_nand_chip *ra, int chipnr)
394 +#if (CONFIG_NUMCHIPS == 1)
395 + if (!(chipnr < CONFIG_NUMCHIPS))
403 +/** @return -1: chip_select fail
404 + * 0 : both CE and WP==0 are OK
405 + * 1 : CE OK and WP==1
407 +static int nfc_enable_chip(struct ra_nand_chip *ra, unsigned int offs, int read_only)
409 + int chipnr = offs >> ra->chip_shift;
411 + ra_dbg("%s: offs:%x read_only:%x \n", __func__, offs, read_only);
413 + chipnr = nfc_select_chip(ra, chipnr);
415 + printk("%s: chip select error, offs(%x)\n", __func__, offs);
420 + return nfc_check_wp();
425 +/** wait nand chip becomeing ready and return queried status.
426 + * @param snooze: sleep time in ms unit before polling device ready.
427 + * @return status of nand chip
428 + * @return NAN_STATUS_FAIL if something unexpected.
430 +static int nfc_wait_ready(int snooze_ms)
436 + if (snooze_ms == 0)
439 + schedule_timeout(snooze_ms * HZ / 1000);
441 + snooze_ms = retry = snooze_ms *1000000 / 100 ; // ndelay(100)
443 + while (!NFC_TRANS_DONE() && retry--) {
444 + if (!cond_resched())
448 + if (!NFC_TRANS_DONE()) {
449 + printk("nfc_wait_ready: no transaction done \n");
450 + return NAND_STATUS_FAIL;
453 +#if !defined (CONFIG_NOT_SUPPORT_RB)
455 + while(!(status = nfc_device_ready()) && retry--) {
460 + printk("nfc_wait_ready: no device ready. \n");
461 + return NAND_STATUS_FAIL;
464 + _nfc_read_status(&status);
469 + _nfc_read_status(&status);
470 + if (status & NAND_STATUS_READY)
475 + printk("nfc_wait_ready 2: no device ready, status(%x). \n", status);
482 + * return 0: erase OK
483 + * return -EIO: fail
485 +int nfc_erase_block(struct ra_nand_chip *ra, int row_addr)
487 + unsigned long cmd1, cmd2, bus_addr, conf;
492 + bus_addr = row_addr;
493 + conf = 0x00511 | ((CFG_ROW_ADDR_CYCLE)<<16);
496 + ra_dbg("%s: cmd1: %lx, cmd2:%lx bus_addr: %lx, conf: %lx \n",
497 + __func__, cmd1, cmd2, bus_addr, conf);
499 + //fixme, should we check nfc status?
500 + CLEAR_INT_STATUS();
502 + ra_outl(NFC_CMD1, cmd1);
503 + ra_outl(NFC_CMD2, cmd2);
504 + ra_outl(NFC_ADDR, bus_addr);
505 + ra_outl(NFC_CONF, conf);
507 + status = nfc_wait_ready(3); //erase wait 3ms
508 + if (status & NAND_STATUS_FAIL) {
509 + printk("%s: fail \n", __func__);
517 +static inline int _nfc_read_raw_data(int cmd1, int cmd2, int bus_addr, int bus_addr2, int conf, char *buf, int len, int flags)
521 + CLEAR_INT_STATUS();
522 + ra_outl(NFC_CMD1, cmd1);
523 + ra_outl(NFC_CMD2, cmd2);
524 + ra_outl(NFC_ADDR, bus_addr);
525 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
526 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
527 + ra_outl(NFC_ADDR2, bus_addr2);
529 + ra_outl(NFC_CONF, conf);
531 + ret = _ra_nand_pull_data(buf, len, 0);
533 + ra_dbg("%s: ret:%x (%x) \n", __func__, ret, len);
534 + return NAND_STATUS_FAIL;
537 + //FIXME, this section is not necessary
538 + ret = nfc_wait_ready(0); //wait ready
539 + /* to prevent the DATA FIFO 's old data from next operation */
540 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x02); //clear data buffer
541 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) & ~0x02); //clear data buffer
543 + if (ret & NAND_STATUS_FAIL) {
544 + printk("%s: fail \n", __func__);
545 + return NAND_STATUS_FAIL;
551 +static inline int _nfc_write_raw_data(int cmd1, int cmd3, int bus_addr, int bus_addr2, int conf, char *buf, int len, int flags)
555 + CLEAR_INT_STATUS();
556 + ra_outl(NFC_CMD1, cmd1);
557 + ra_outl(NFC_CMD3, cmd3);
558 + ra_outl(NFC_ADDR, bus_addr);
559 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
560 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
561 + ra_outl(NFC_ADDR2, bus_addr2);
563 + ra_outl(NFC_CONF, conf);
565 + ret = _ra_nand_push_data(buf, len, 0);
567 + ra_dbg("%s: ret:%x (%x) \n", __func__, ret, len);
568 + return NAND_STATUS_FAIL;
571 + ret = nfc_wait_ready(1); //write wait 1ms
572 + /* to prevent the DATA FIFO 's old data from next operation */
573 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x02); //clear data buffer
574 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) & ~0x02); //clear data buffer
576 + if (ret & NAND_STATUS_FAIL) {
577 + printk("%s: fail \n", __func__);
578 + return NAND_STATUS_FAIL;
588 +int nfc_read_oob(struct ra_nand_chip *ra, int page, unsigned int offs, char *buf, int len, int flags)
590 + unsigned int cmd1 = 0, cmd2 = 0, conf = 0;
591 + unsigned int bus_addr = 0, bus_addr2 = 0;
592 + unsigned int ecc_en;
596 + int pages_perblock = 1<<(ra->erase_shift - ra->page_shift);
597 + // constrain of nfc read function
599 +#if defined (WORKAROUND_RX_BUF_OV)
600 + BUG_ON (len > 60); //problem of rx-buffer overrun
602 + BUG_ON (offs >> ra->oob_shift); //page boundry
603 + BUG_ON ((unsigned int)(((offs + len) >> ra->oob_shift) + page) >
604 + ((page + pages_perblock) & ~(pages_perblock-1))); //block boundry
606 + use_gdma = flags & FLAG_USE_GDMA;
607 + ecc_en = flags & FLAG_ECC_EN;
608 + bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)) | (offs & ((1<<CFG_COLUMN_ADDR_CYCLE*8) - 1));
610 + if (is_nand_page_2048) {
611 + bus_addr += CFG_PAGESIZE;
612 + bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
615 + conf = 0x000511| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
619 + conf = 0x000141| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
626 + ra_dbg("%s: cmd1:%x, bus_addr:%x, conf:%x, len:%x, flag:%x\n",
627 + __func__, cmd1, bus_addr, conf, len, flags);
629 + status = _nfc_read_raw_data(cmd1, cmd2, bus_addr, bus_addr2, conf, buf, len, flags);
630 + if (status & NAND_STATUS_FAIL) {
631 + printk("%s: fail\n", __func__);
642 +int nfc_write_oob(struct ra_nand_chip *ra, int page, unsigned int offs, char *buf, int len, int flags)
644 + unsigned int cmd1 = 0, cmd3=0, conf = 0;
645 + unsigned int bus_addr = 0, bus_addr2 = 0;
649 + int pages_perblock = 1<<(ra->erase_shift - ra->page_shift);
650 + // constrain of nfc read function
652 + BUG_ON (offs >> ra->oob_shift); //page boundry
653 + BUG_ON ((unsigned int)(((offs + len) >> ra->oob_shift) + page) >
654 + ((page + pages_perblock) & ~(pages_perblock-1))); //block boundry
656 + use_gdma = flags & FLAG_USE_GDMA;
657 + bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)) | (offs & ((1<<CFG_COLUMN_ADDR_CYCLE*8) - 1));
659 + if (is_nand_page_2048) {
662 + bus_addr += CFG_PAGESIZE;
663 + bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
664 + conf = 0x001123 | ((CFG_ADDR_CYCLE)<<16) | ((len) << 20);
669 + conf = 0x001223 | ((CFG_ADDR_CYCLE)<<16) | ((len) << 20);
675 + ra_dbg("%s: cmd1: %x, cmd3: %x bus_addr: %x, conf: %x, len:%x\n",
676 + __func__, cmd1, cmd3, bus_addr, conf, len);
678 + status = _nfc_write_raw_data(cmd1, cmd3, bus_addr, bus_addr2, conf, buf, len, flags);
679 + if (status & NAND_STATUS_FAIL) {
680 + printk("%s: fail \n", __func__);
688 +int nfc_read_page(struct ra_nand_chip *ra, char *buf, int page, int flags);
689 +int nfc_write_page(struct ra_nand_chip *ra, char *buf, int page, int flags);
692 +#if !defined (WORKAROUND_RX_BUF_OV)
693 +static int one_bit_correction(char *ecc, char *expected, int *bytes, int *bits);
694 +int nfc_ecc_verify(struct ra_nand_chip *ra, char *buf, int page, int mode)
700 + //ra_dbg("%s, page:%x mode:%d\n", __func__, page, mode);
702 + if (mode == FL_WRITING) {
703 + int len = CFG_PAGESIZE + CFG_PAGE_OOBSIZE;
704 + int conf = 0x000141| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
705 + conf |= (1<<3); //(ecc_en)
706 + //conf |= (1<<2); // (use_gdma)
708 + p = ra->readback_buffers;
709 + ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_ECC_EN);
713 + //FIXME, double comfirm
714 + printk("%s: read back fail, try again \n",__func__);
715 + ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_ECC_EN);
717 + printk("\t%s: read back fail agian \n",__func__);
721 + else if (mode == FL_READING) {
729 + if (!is_nand_page_2048) {
730 + ecc = ra_inl(NFC_ECC);
731 + if (ecc == 0) //clean page.
734 + for (i=0; i<CONFIG_ECC_BYTES; i++) {
735 + int eccpos = CONFIG_ECC_OFFSET + i;
736 + if (*(p + eccpos) != (char)0xff)
738 + if (i == CONFIG_ECC_BYTES - 1) {
739 + printk("skip ecc 0xff at page %x\n", page);
743 + for (i=0; i<CONFIG_ECC_BYTES; i++) {
744 + int eccpos = CONFIG_ECC_OFFSET + i;
745 + if (*(p + eccpos) != *(e + i)) {
746 + printk("%s mode:%s, invalid ecc, page: %x read:%x %x %x, ecc:%x \n",
747 + __func__, (mode == FL_READING)?"read":"write", page,
748 + *(p+ CONFIG_ECC_OFFSET), *(p+ CONFIG_ECC_OFFSET+1), *(p+ CONFIG_ECC_OFFSET +2), ecc);
753 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
754 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
756 + int ecc2, ecc3, ecc4, qsz;
757 + char *e2, *e3, *e4;
758 + int correction_flag = 0;
759 + ecc = ra_inl(NFC_ECC_P1);
760 + ecc2 = ra_inl(NFC_ECC_P2);
761 + ecc3 = ra_inl(NFC_ECC_P3);
762 + ecc4 = ra_inl(NFC_ECC_P4);
767 + qsz = CFG_PAGE_OOBSIZE / 4;
768 + if (ecc == 0 && ecc2 == 0 && ecc3 == 0 && ecc4 == 0)
770 + for (i=0; i<CONFIG_ECC_BYTES; i++) {
771 + int eccpos = CONFIG_ECC_OFFSET + i;
772 + if (*(p + eccpos) != (char)0xff)
774 + else if (*(p + eccpos + qsz) != (char)0xff)
776 + else if (*(p + eccpos + qsz*2) != (char)0xff)
778 + else if (*(p + eccpos + qsz*3) != (char)0xff)
780 + if (i == CONFIG_ECC_BYTES - 1) {
781 + printk("skip ecc 0xff at page %x\n", page);
785 + for (i=0; i<CONFIG_ECC_BYTES; i++) {
786 + int eccpos = CONFIG_ECC_OFFSET + i;
787 + if (*(p + eccpos) != *(e + i)) {
788 + printk("%s mode:%s, invalid ecc, page: %x read:%x %x %x, ecc:%x \n",
789 + __func__, (mode == FL_READING)?"read":"write", page,
790 + *(p+ CONFIG_ECC_OFFSET), *(p+ CONFIG_ECC_OFFSET+1), *(p+ CONFIG_ECC_OFFSET +2), ecc);
791 + correction_flag |= 0x1;
793 + if (*(p + eccpos + qsz) != *(e2 + i)) {
794 + printk("%s mode:%s, invalid ecc2, page: %x read:%x %x %x, ecc2:%x \n",
795 + __func__, (mode == FL_READING)?"read":"write", page,
796 + *(p+CONFIG_ECC_OFFSET+qsz), *(p+ CONFIG_ECC_OFFSET+1+qsz), *(p+ CONFIG_ECC_OFFSET+2+qsz), ecc2);
797 + correction_flag |= 0x2;
799 + if (*(p + eccpos + qsz*2) != *(e3 + i)) {
800 + printk("%s mode:%s, invalid ecc3, page: %x read:%x %x %x, ecc3:%x \n",
801 + __func__, (mode == FL_READING)?"read":"write", page,
802 + *(p+CONFIG_ECC_OFFSET+qsz*2), *(p+ CONFIG_ECC_OFFSET+1+qsz*2), *(p+ CONFIG_ECC_OFFSET+2+qsz*2), ecc3);
803 + correction_flag |= 0x4;
805 + if (*(p + eccpos + qsz*3) != *(e4 + i)) {
806 + printk("%s mode:%s, invalid ecc4, page: %x read:%x %x %x, ecc4:%x \n",
807 + __func__, (mode == FL_READING)?"read":"write", page,
808 + *(p+CONFIG_ECC_OFFSET+qsz*3), *(p+ CONFIG_ECC_OFFSET+1+qsz*3), *(p+ CONFIG_ECC_OFFSET+2+qsz*3), ecc4);
809 + correction_flag |= 0x8;
813 + if (correction_flag)
815 + printk("trying to do correction!\n");
816 + if (correction_flag & 0x1)
819 + char *pBuf = p - CFG_PAGESIZE;
821 + if (one_bit_correction(p + CONFIG_ECC_OFFSET, e, &bytes, &bits) == 0)
823 + pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
824 + printk("1. correct byte %d, bit %d!\n", bytes, bits);
828 + printk("failed to correct!\n");
833 + if (correction_flag & 0x2)
836 + char *pBuf = (p - CFG_PAGESIZE) + CFG_PAGESIZE/4;
838 + if (one_bit_correction((p + CONFIG_ECC_OFFSET + qsz), e2, &bytes, &bits) == 0)
840 + pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
841 + printk("2. correct byte %d, bit %d!\n", bytes, bits);
845 + printk("failed to correct!\n");
849 + if (correction_flag & 0x4)
852 + char *pBuf = (p - CFG_PAGESIZE) + CFG_PAGESIZE/2;
854 + if (one_bit_correction((p + CONFIG_ECC_OFFSET + qsz * 2), e3, &bytes, &bits) == 0)
856 + pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
857 + printk("3. correct byte %d, bit %d!\n", bytes, bits);
861 + printk("failed to correct!\n");
865 + if (correction_flag & 0x8)
868 + char *pBuf = (p - CFG_PAGESIZE) + CFG_PAGESIZE*3/4;
870 + if (one_bit_correction((p + CONFIG_ECC_OFFSET + qsz * 3), e4, &bytes, &bits) == 0)
872 + pBuf[bytes] = pBuf[bytes] ^ (1 << bits);
873 + printk("4. correct byte %d, bit %d!\n", bytes, bits);
877 + printk("failed to correct!\n");
893 +void ranfc_dump(void)
896 + for (i=0; i<11; i++) {
899 + printk("%x: %x \n", NFC_BASE + i*4, ra_inl(NFC_BASE + i*4));
904 + * @return 0, ecc OK or corrected.
905 + * @return NAND_STATUS_FAIL, ecc fail.
908 +int nfc_ecc_verify(struct ra_nand_chip *ra, char *buf, int page, int mode)
914 + if (ranfc_verify == 0)
917 + ra_dbg("%s, page:%x mode:%d\n", __func__, page, mode);
919 + if (mode == FL_WRITING) { // read back and memcmp
920 + ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_NONE);
921 + if (ret != 0) //double comfirm
922 + ret = nfc_read_page(ra, ra->readback_buffers, page, FLAG_NONE);
925 + printk("%s: mode:%x read back fail \n", __func__, mode);
928 + return memcmp(buf, ra->readback_buffers, 1<<ra->page_shift);
931 + if (mode == FL_READING) {
933 + if (ra->sandbox_page == 0)
936 + ret = nfc_write_page(ra, buf, ra->sandbox_page, FLAG_USE_GDMA | FLAG_ECC_EN);
938 + printk("%s, fail write sandbox_page \n", __func__);
943 + * The following command is actually not 'write' command to drive NFC to write flash.
944 + * However, it can make NFC to calculate ECC, that will be used to compare with original ones.
947 + unsigned int conf = 0x001223| (CFG_ADDR_CYCLE<<16) | (0x200 << 20) | (1<<3) | (1<<2);
948 + _nfc_write_raw_data(0xff, 0xff, ra->sandbox_page<<ra->page_shift, conf, buf, 0x200, FLAG_USE_GDMA);
951 + ecc = ra_inl(NFC_ECC);
952 + if (ecc == 0) //clean page.
955 + p = buf + (1<<ra->page_shift);
956 + for (i=0; i<CONFIG_ECC_BYTES; i++) {
957 + int eccpos = CONFIG_ECC_OFFSET + i;
958 + if (*(p + eccpos) != *(e + i)) {
959 + printk("%s mode:%s, invalid ecc, page: %x read:%x %x %x, write:%x \n",
960 + __func__, (mode == FL_READING)?"read":"write", page,
961 + *(p+ CONFIG_ECC_OFFSET), *(p+ CONFIG_ECC_OFFSET+1), *(p+ CONFIG_ECC_OFFSET +2), ecc);
963 + for (i=0; i<528; i++)
964 + printk("%-2x \n", *(buf + i));
979 + * @return -EIO, writing size is less than a page
982 +int nfc_read_page(struct ra_nand_chip *ra, char *buf, int page, int flags)
984 + unsigned int cmd1 = 0, cmd2 = 0, conf = 0;
985 + unsigned int bus_addr = 0, bus_addr2 = 0;
986 + unsigned int ecc_en;
991 + use_gdma = flags & FLAG_USE_GDMA;
992 + ecc_en = flags & FLAG_ECC_EN;
994 + page = page & (CFG_CHIPSIZE - 1); // chip boundary
995 + size = CFG_PAGESIZE + CFG_PAGE_OOBSIZE; //add oobsize
1000 +#if defined (WORKAROUND_RX_BUF_OV)
1001 + len = min(60, size);
1005 + bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)) | (offs & ((1<<CFG_COLUMN_ADDR_CYCLE*8)-1));
1006 + if (is_nand_page_2048) {
1007 + bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
1010 + conf = 0x000511| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
1013 + if (offs & ~(CFG_PAGESIZE-1))
1015 + else if (offs & ~((1<<CFG_COLUMN_ADDR_CYCLE*8)-1))
1020 + conf = 0x000141| ((CFG_ADDR_CYCLE)<<16) | (len << 20);
1022 +#if !defined (WORKAROUND_RX_BUF_OV)
1029 + status = _nfc_read_raw_data(cmd1, cmd2, bus_addr, bus_addr2, conf, buf+offs, len, flags);
1030 + if (status & NAND_STATUS_FAIL) {
1031 + printk("%s: fail \n", __func__);
1039 + // verify and correct ecc
1040 + if ((flags & (FLAG_VERIFY | FLAG_ECC_EN)) == (FLAG_VERIFY | FLAG_ECC_EN)) {
1041 + status = nfc_ecc_verify(ra, buf, page, FL_READING);
1042 + if (status != 0) {
1043 + printk("%s: fail, buf:%x, page:%x, flag:%x\n",
1044 + __func__, (unsigned int)buf, page, flags);
1049 + // fix,e not yet support
1050 + ra->buffers_page = -1; //cached
1058 + * @return -EIO, fail to write
1061 +int nfc_write_page(struct ra_nand_chip *ra, char *buf, int page, int flags)
1063 + unsigned int cmd1 = 0, cmd3, conf = 0;
1064 + unsigned int bus_addr = 0, bus_addr2 = 0;
1065 + unsigned int ecc_en;
1069 + uint8_t *oob = buf + (1<<ra->page_shift);
1071 + use_gdma = flags & FLAG_USE_GDMA;
1072 + ecc_en = flags & FLAG_ECC_EN;
1074 + oob[ra->badblockpos] = 0xff; //tag as good block.
1075 + ra->buffers_page = -1; //cached
1077 + page = page & (CFG_CHIPSIZE-1); //chip boundary
1078 + size = CFG_PAGESIZE + CFG_PAGE_OOBSIZE; //add oobsize
1079 + bus_addr = (page << (CFG_COLUMN_ADDR_CYCLE*8)); //write_page always write from offset 0.
1081 + if (is_nand_page_2048) {
1082 + bus_addr2 = page >> (CFG_COLUMN_ADDR_CYCLE*8);
1085 + conf = 0x001123| ((CFG_ADDR_CYCLE)<<16) | (size << 20);
1090 + conf = 0x001223| ((CFG_ADDR_CYCLE)<<16) | (size << 20);
1093 + conf |= (1<<3); //enable ecc
1098 + ra_dbg("nfc_write_page: cmd1: %x, cmd3: %x bus_addr: %x, conf: %x, len:%x\n",
1099 + cmd1, cmd3, bus_addr, conf, size);
1101 + status = _nfc_write_raw_data(cmd1, cmd3, bus_addr, bus_addr2, conf, buf, size, flags);
1102 + if (status & NAND_STATUS_FAIL) {
1103 + printk("%s: fail \n", __func__);
1108 + if (flags & FLAG_VERIFY) { // verify and correct ecc
1109 + status = nfc_ecc_verify(ra, buf, page, FL_WRITING);
1111 +#ifdef RANDOM_GEN_BAD_BLOCK
1112 + if (((random32() & 0x1ff) == 0x0) && (page >= 0x100)) // randomly create bad block
1114 + printk("hmm... create a bad block at page %x\n", (bus_addr >> 16));
1119 + if (status != 0) {
1120 + printk("%s: ecc_verify fail: ret:%x \n", __func__, status);
1121 + oob[ra->badblockpos] = 0x33;
1122 + page -= page % (CFG_BLOCKSIZE/CFG_PAGESIZE);
1123 + printk("create a bad block at page %x\n", page);
1124 + if (!is_nand_page_2048)
1125 + status = nfc_write_oob(ra, page, ra->badblockpos, oob+ra->badblockpos, 1, flags);
1128 + status = _nfc_write_raw_data(cmd1, cmd3, bus_addr, bus_addr2, conf, buf, size, flags);
1129 + nfc_write_oob(ra, page, 0, oob, 16, FLAG_NONE);
1136 + ra->buffers_page = page; //cached
1142 +/*************************************************************
1143 + * nand internal process
1144 + *************************************************************/
1147 + * nand_release_device - [GENERIC] release chip
1148 + * @mtd: MTD device structure
1150 + * Deselect, release chip lock and wake up anyone waiting on the device
1152 +static void nand_release_device(struct ra_nand_chip *ra)
1154 + /* De-select the NAND device */
1155 + nfc_select_chip(ra, -1);
1157 + /* Release the controller and the chip */
1158 + ra->state = FL_READY;
1160 + mutex_unlock(ra->controller);
1164 + * nand_get_device - [GENERIC] Get chip for selected access
1165 + * @chip: the nand chip descriptor
1166 + * @mtd: MTD device structure
1167 + * @new_state: the state which is requested
1169 + * Get the device and lock it for exclusive access
1172 +nand_get_device(struct ra_nand_chip *ra, int new_state)
1176 + ret = mutex_lock_interruptible(ra->controller);
1178 + ra->state = new_state;
1186 +/*************************************************************
1187 + * nand internal process
1188 + *************************************************************/
1190 +int nand_bbt_get(struct ra_nand_chip *ra, int block)
1193 + bits = block * BBTTAG_BITS;
1198 + return (ra->bbt[byte] >> bits) & BBTTAG_BITS_MASK;
1201 +int nand_bbt_set(struct ra_nand_chip *ra, int block, int tag)
1204 + bits = block * BBTTAG_BITS;
1209 + // If previous tag is bad, dont overwrite it
1210 + if (((ra->bbt[byte] >> bits) & BBTTAG_BITS_MASK) == BBT_TAG_BAD)
1212 + return BBT_TAG_BAD;
1215 + ra->bbt[byte] = (ra->bbt[byte] & ~(BBTTAG_BITS_MASK << bits)) | ((tag & BBTTAG_BITS_MASK) << bits);
1221 + * nand_block_checkbad - [GENERIC] Check if a block is marked bad
1222 + * @mtd: MTD device structure
1223 + * @ofs: offset from device start
1225 + * Check, if the block is bad. Either by reading the bad block table or
1226 + * calling of the scan function.
1228 +int nand_block_checkbad(struct ra_nand_chip *ra, loff_t offs)
1233 + char *str[]= {"UNK", "RES", "BAD", "GOOD"};
1235 + if (ranfc_bbt == 0)
1239 + // align with chip
1241 + offs = offs & ((1<<ra->chip_shift) -1);
1243 + page = offs >> ra->page_shift;
1244 + block = offs >> ra->erase_shift;
1247 + tag = nand_bbt_get(ra, block);
1249 + if (tag == BBT_TAG_UNKNOWN) {
1250 + ret = nfc_read_oob(ra, page, ra->badblockpos, (char*)&tag, 1, FLAG_NONE);
1252 + tag = ((le32_to_cpu(tag) & 0x0ff) == 0x0ff) ? BBT_TAG_GOOD : BBT_TAG_BAD;
1254 + tag = BBT_TAG_BAD;
1256 + nand_bbt_set(ra, block, tag);
1259 + if (tag != BBT_TAG_GOOD) {
1260 + printk("%s: offs:%x tag: %s \n", __func__, (unsigned int)offs, str[tag]);
1271 + * nand_block_markbad -
1273 +int nand_block_markbad(struct ra_nand_chip *ra, loff_t offs)
1280 + // align with chip
1281 + ra_dbg("%s offs: %x \n", __func__, (int)offs);
1283 + offs = offs & ((1<<ra->chip_shift) -1);
1285 + page = offs >> ra->page_shift;
1286 + block = offs >> ra->erase_shift;
1288 + tag = nand_bbt_get(ra, block);
1290 + if (tag == BBT_TAG_BAD) {
1291 + printk("%s: mark repeatedly \n", __func__);
1297 + ret = nfc_read_page(ra, ra->buffers, page, FLAG_NONE);
1299 + printk("%s: fail to read bad block tag \n", __func__);
1303 + ecc = &ra->buffers[(1<<ra->page_shift)+ra->badblockpos];
1304 + if (*ecc == (char)0x0ff) {
1307 + ret = nfc_write_page(ra, ra->buffers, page, FLAG_USE_GDMA);
1309 + printk("%s: fail to write bad block tag \n", __func__);
1315 + nand_bbt_set(ra, block, tag);
1321 +#if defined (WORKAROUND_RX_BUF_OV)
1323 + * to find a bad block for ecc verify of read_page
1325 +unsigned int nand_bbt_find_sandbox(struct ra_nand_chip *ra)
1328 + int chipsize = 1 << ra->chip_shift;
1329 + int blocksize = 1 << ra->erase_shift;
1332 + while (offs < chipsize) {
1333 + if (nand_block_checkbad(ra, offs)) //scan and verify the unknown tag
1335 + offs += blocksize;
1338 + if (offs >= chipsize) {
1339 + offs = chipsize - blocksize;
1342 + nand_bbt_set(ra, (unsigned int)offs>>ra->erase_shift, BBT_TAG_RES); // tag bbt only, instead of update badblockpos of flash.
1343 + return (offs >> ra->page_shift);
1350 + * nand_erase_nand - [Internal] erase block(s)
1351 + * @mtd: MTD device structure
1352 + * @instr: erase instruction
1353 + * @allowbbt: allow erasing the bbt area
1355 + * Erase one ore more blocks
1357 +int _nand_erase_nand(struct ra_nand_chip *ra, struct erase_info *instr)
1359 + int page, len, status, ret;
1360 + unsigned int addr, blocksize = 1<<ra->erase_shift;
1362 + ra_dbg("%s: start:%x, len:%x \n", __func__,
1363 + (unsigned int)instr->addr, (unsigned int)instr->len);
1365 +//#define BLOCK_ALIGNED(a) ((a) & (blocksize - 1)) // already defined
1367 + if (BLOCK_ALIGNED(instr->addr) || BLOCK_ALIGNED(instr->len)) {
1368 + ra_dbg("%s: erase block not aligned, addr:%x len:%x\n", __func__, instr->addr, instr->len);
1372 + instr->fail_addr = 0xffffffff;
1375 + addr = instr->addr;
1376 + instr->state = MTD_ERASING;
1380 + page = (int)(addr >> ra->page_shift);
1382 + /* select device and check wp */
1383 + if (nfc_enable_chip(ra, addr, 0)) {
1384 + printk("%s: nand is write protected \n", __func__);
1385 + instr->state = MTD_ERASE_FAILED;
1389 + /* if we have a bad block, we do not erase bad blocks */
1390 + if (nand_block_checkbad(ra, addr)) {
1391 + printk(KERN_WARNING "nand_erase: attempt to erase a "
1392 + "bad block at 0x%08x\n", addr);
1393 + instr->state = MTD_ERASE_FAILED;
1398 + * Invalidate the page cache, if we erase the block which
1399 + * contains the current cached page
1401 + if (BLOCK_ALIGNED(addr) == BLOCK_ALIGNED(ra->buffers_page << ra->page_shift))
1402 + ra->buffers_page = -1;
1404 + status = nfc_erase_block(ra, page);
1405 + /* See if block erase succeeded */
1407 + printk("%s: failed erase, page 0x%08x\n", __func__, page);
1408 + instr->state = MTD_ERASE_FAILED;
1409 + instr->fail_addr = (page << ra->page_shift);
1414 + /* Increment page address and decrement length */
1416 + addr += blocksize;
1419 + instr->state = MTD_ERASE_DONE;
1423 + ret = ((instr->state == MTD_ERASE_DONE) ? 0 : -EIO);
1424 + /* Do call back function */
1426 + mtd_erase_callback(instr);
1429 + nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_BAD);
1432 + /* Return more or less happy */
1437 +nand_write_oob_buf(struct ra_nand_chip *ra, uint8_t *buf, uint8_t *oob, size_t size,
1438 + int mode, int ooboffs)
1440 + size_t oobsize = 1<<ra->oob_shift;
1441 + struct nand_oobfree *free;
1442 + uint32_t woffs = ooboffs;
1445 + ra_dbg("%s: size:%x, mode:%x, offs:%x \n", __func__, size, mode, ooboffs);
1448 + case MTD_OPS_PLACE_OOB:
1450 + if (ooboffs > oobsize)
1453 + size = min(size, oobsize - ooboffs);
1454 + memcpy(buf + ooboffs, oob, size);
1458 + case MTD_OPS_AUTO_OOB:
1459 + if (ooboffs > ra->oob->oobavail)
1463 + for(free = ra->oob->oobfree; free->length && size; free++) {
1464 + int wlen = free->length - woffs;
1467 + /* Write request not from offset 0 ? */
1473 + bytes = min_t(size_t, size, wlen);
1474 + memcpy (buf + free->offset + woffs, oob, bytes);
1491 +static int nand_read_oob_buf(struct ra_nand_chip *ra, uint8_t *oob, size_t size,
1492 + int mode, int ooboffs)
1494 + size_t oobsize = 1<<ra->oob_shift;
1495 + uint8_t *buf = ra->buffers + (1<<ra->page_shift);
1498 + ra_dbg("%s: size:%x, mode:%x, offs:%x \n", __func__, size, mode, ooboffs);
1501 + case MTD_OPS_PLACE_OOB:
1503 + if (ooboffs > oobsize)
1506 + size = min(size, oobsize - ooboffs);
1507 + memcpy(oob, buf + ooboffs, size);
1510 + case MTD_OPS_AUTO_OOB: {
1511 + struct nand_oobfree *free;
1512 + uint32_t woffs = ooboffs;
1514 + if (ooboffs > ra->oob->oobavail)
1517 + size = min(size, ra->oob->oobavail - ooboffs);
1518 + for(free = ra->oob->oobfree; free->length && size; free++) {
1519 + int wlen = free->length - woffs;
1522 + /* Write request not from offset 0 ? */
1528 + bytes = min_t(size_t, size, wlen);
1529 + memcpy (oob, buf + free->offset + woffs, bytes);
1545 + * nand_do_write_ops - [Internal] NAND write with ECC
1546 + * @mtd: MTD device structure
1547 + * @to: offset to write to
1548 + * @ops: oob operations description structure
1550 + * NAND write with ECC
1552 +static int nand_do_write_ops(struct ra_nand_chip *ra, loff_t to,
1553 + struct mtd_oob_ops *ops)
1556 + uint32_t datalen = ops->len;
1557 + uint32_t ooblen = ops->ooblen;
1558 + uint8_t *oob = ops->oobbuf;
1559 + uint8_t *data = ops->datbuf;
1560 + int pagesize = (1<<ra->page_shift);
1561 + int pagemask = (pagesize -1);
1562 + int oobsize = 1<<ra->oob_shift;
1564 + //int i = 0; //for ra_dbg only
1566 + ra_dbg("%s: to:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x oobmode:%x \n",
1567 + __func__, (unsigned int)to, data, oob, datalen, ooblen, ops->ooboffs, ops->mode);
1570 + ops->oobretlen = 0;
1573 + /* Invalidate the page cache, when we write to the cached page */
1574 + ra->buffers_page = -1;
1580 + // oob sequential (burst) write
1581 + if (datalen == 0 && ooblen) {
1582 + int len = ((ooblen + ops->ooboffs) + (ra->oob->oobavail - 1)) / ra->oob->oobavail * oobsize;
1584 + /* select chip, and check if it is write protected */
1585 + if (nfc_enable_chip(ra, addr, 0))
1588 + //FIXME, need sanity check of block boundary
1589 + page = (int)((to & ((1<<ra->chip_shift)-1)) >> ra->page_shift); //chip boundary
1590 + memset(ra->buffers, 0x0ff, pagesize);
1591 + //fixme, should we reserve the original content?
1592 + if (ops->mode == MTD_OPS_AUTO_OOB) {
1593 + nfc_read_oob(ra, page, 0, ra->buffers, len, FLAG_NONE);
1598 + nand_write_oob_buf(ra, ra->buffers, oob, ooblen, ops->mode, ops->ooboffs);
1599 + // write out buffer to chip
1600 + nfc_write_oob(ra, page, 0, ra->buffers, len, FLAG_USE_GDMA);
1603 + ops->oobretlen = ooblen;
1607 + // data sequential (burst) write
1608 + if (datalen && ooblen == 0) {
1609 + // ranfc can not support write_data_burst, since hw-ecc and fifo constraints..
1613 + while(datalen || ooblen) {
1619 + ra_dbg("%s (%d): addr:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x \n",
1620 + __func__, i++, (unsigned int)addr, data, oob, datalen, ooblen, ops->ooboffs);
1622 + page = (int)((addr & ((1<<ra->chip_shift)-1)) >> ra->page_shift); //chip boundary
1624 + /* select chip, and check if it is write protected */
1625 + if (nfc_enable_chip(ra, addr, 0))
1629 + if (ops->mode == MTD_OPS_AUTO_OOB) {
1630 + //fixme, this path is not yet varified
1631 + nfc_read_oob(ra, page, 0, ra->buffers + pagesize, oobsize, FLAG_NONE);
1633 + if (oob && ooblen > 0) {
1634 + len = nand_write_oob_buf(ra, ra->buffers + pagesize, oob, ooblen, ops->mode, ops->ooboffs);
1639 + ops->oobretlen += len;
1644 + offs = addr & pagemask;
1645 + len = min_t(size_t, datalen, pagesize - offs);
1646 + if (data && len > 0) {
1647 + memcpy(ra->buffers + offs, data, len); // we can not sure ops->buf wether is DMA-able.
1651 + ops->retlen += len;
1653 + ecc_en = FLAG_ECC_EN;
1655 + ret = nfc_write_page(ra, ra->buffers, page, FLAG_USE_GDMA | FLAG_VERIFY |
1656 + ((ops->mode == MTD_OPS_RAW || ops->mode == MTD_OPS_PLACE_OOB) ? 0 : ecc_en ));
1658 + nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_BAD);
1662 + nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_GOOD);
1664 + addr = (page+1) << ra->page_shift;
1671 + * nand_do_read_ops - [Internal] Read data with ECC
1673 + * @mtd: MTD device structure
1674 + * @from: offset to read from
1675 + * @ops: oob ops structure
1677 + * Internal function. Called with chip held.
1679 +static int nand_do_read_ops(struct ra_nand_chip *ra, loff_t from,
1680 + struct mtd_oob_ops *ops)
1683 + uint32_t datalen = ops->len;
1684 + uint32_t ooblen = ops->ooblen;
1685 + uint8_t *oob = ops->oobbuf;
1686 + uint8_t *data = ops->datbuf;
1687 + int pagesize = (1<<ra->page_shift);
1688 + int pagemask = (pagesize -1);
1689 + loff_t addr = from;
1690 + //int i = 0; //for ra_dbg only
1692 + ra_dbg("%s: addr:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x \n",
1693 + __func__, (unsigned int)addr, data, oob, datalen, ooblen, ops->ooboffs);
1696 + ops->oobretlen = 0;
1701 + while(datalen || ooblen) {
1706 + ra_dbg("%s (%d): addr:%x, ops data:%p, oob:%p datalen:%x ooblen:%x, ooboffs:%x \n",
1707 + __func__, i++, (unsigned int)addr, data, oob, datalen, ooblen, ops->ooboffs);
1709 + if (nfc_enable_chip(ra, addr, 1) < 0)
1712 + page = (int)((addr & ((1<<ra->chip_shift)-1)) >> ra->page_shift);
1714 + ret = nfc_read_page(ra, ra->buffers, page, FLAG_VERIFY |
1715 + ((ops->mode == MTD_OPS_RAW || ops->mode == MTD_OPS_PLACE_OOB) ? 0: FLAG_ECC_EN ));
1716 + //FIXME, something strange here, some page needs 2 more tries to guarantee read success.
1718 + printk("read again:\n");
1719 + ret = nfc_read_page(ra, ra->buffers, page, FLAG_VERIFY |
1720 + ((ops->mode == MTD_OPS_RAW || ops->mode == MTD_OPS_PLACE_OOB) ? 0: FLAG_ECC_EN ));
1723 + printk("read again fail \n");
1724 + nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_BAD);
1725 + if ((ret != -EUCLEAN) && (ret != -EBADMSG)) {
1729 + /* ecc verification fail, but data need to be returned. */
1733 + printk(" read agian susccess \n");
1738 + if (oob && ooblen > 0) {
1739 + len = nand_read_oob_buf(ra, oob, ooblen, ops->mode, ops->ooboffs);
1741 + printk("nand_read_oob_buf: fail return %x \n", len);
1746 + ops->oobretlen += len;
1751 + offs = addr & pagemask;
1752 + len = min_t(size_t, datalen, pagesize - offs);
1753 + if (data && len > 0) {
1754 + memcpy(data, ra->buffers + offs, len); // we can not sure ops->buf wether is DMA-able.
1758 + ops->retlen += len;
1764 + nand_bbt_set(ra, addr >> ra->erase_shift, BBT_TAG_GOOD);
1765 + // address go further to next page, instead of increasing of length of write. This avoids some special cases wrong.
1766 + addr = (page+1) << ra->page_shift;
1772 +ramtd_nand_erase(struct mtd_info *mtd, struct erase_info *instr)
1774 + struct ra_nand_chip *ra = (struct ra_nand_chip *)mtd->priv;
1777 + ra_dbg("%s: start:%x, len:%x \n", __func__,
1778 + (unsigned int)instr->addr, (unsigned int)instr->len);
1780 + nand_get_device(ra, FL_ERASING);
1781 + ret = _nand_erase_nand((struct ra_nand_chip *)mtd->priv, instr);
1782 + nand_release_device(ra);
1788 +ramtd_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1789 + size_t *retlen, const uint8_t *buf)
1791 + struct ra_nand_chip *ra = mtd->priv;
1792 + struct mtd_oob_ops ops;
1795 + ra_dbg("%s: to 0x%x len=0x%x\n", __func__, to, len);
1797 + if ((to + len) > mtd->size)
1803 + nand_get_device(ra, FL_WRITING);
1805 + memset(&ops, 0, sizeof(ops));
1807 + ops.datbuf = (uint8_t *)buf;
1808 + ops.oobbuf = NULL;
1809 + ops.mode = MTD_OPS_AUTO_OOB;
1811 + ret = nand_do_write_ops(ra, to, &ops);
1813 + *retlen = ops.retlen;
1815 + nand_release_device(ra);
1821 +ramtd_nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1822 + size_t *retlen, uint8_t *buf)
1825 + struct ra_nand_chip *ra = mtd->priv;
1827 + struct mtd_oob_ops ops;
1829 + ra_dbg("%s: mtd:%p from:%x, len:%x, buf:%p \n", __func__, mtd, (unsigned int)from, len, buf);
1831 + /* Do not allow reads past end of device */
1832 + if ((from + len) > mtd->size)
1837 + nand_get_device(ra, FL_READING);
1839 + memset(&ops, 0, sizeof(ops));
1842 + ops.oobbuf = NULL;
1843 + ops.mode = MTD_OPS_AUTO_OOB;
1845 + ret = nand_do_read_ops(ra, from, &ops);
1847 + *retlen = ops.retlen;
1849 + nand_release_device(ra);
1856 +ramtd_nand_readoob(struct mtd_info *mtd, loff_t from,
1857 + struct mtd_oob_ops *ops)
1859 + struct ra_nand_chip *ra = mtd->priv;
1862 + ra_dbg("%s: \n", __func__);
1864 + nand_get_device(ra, FL_READING);
1866 + ret = nand_do_read_ops(ra, from, ops);
1868 + nand_release_device(ra);
1874 +ramtd_nand_writeoob(struct mtd_info *mtd, loff_t to,
1875 + struct mtd_oob_ops *ops)
1877 + struct ra_nand_chip *ra = mtd->priv;
1880 + nand_get_device(ra, FL_READING);
1881 + ret = nand_do_write_ops(ra, to, ops);
1882 + nand_release_device(ra);
1888 +ramtd_nand_block_isbad(struct mtd_info *mtd, loff_t offs)
1890 + if (offs > mtd->size)
1893 + return nand_block_checkbad((struct ra_nand_chip *)mtd->priv, offs);
1897 +ramtd_nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
1899 + struct ra_nand_chip *ra = mtd->priv;
1902 + ra_dbg("%s: \n", __func__);
1903 + nand_get_device(ra, FL_WRITING);
1904 + ret = nand_block_markbad(ra, ofs);
1905 + nand_release_device(ra);
1910 +// 1-bit error detection
1911 +static int one_bit_correction(char *ecc1, char *ecc2, int *bytes, int *bits)
1913 + // check if ecc and expected are all valid
1914 + char *p, nibble, crumb;
1915 + int i, xor, iecc1 = 0, iecc2 = 0;
1917 + printk("correction : %x %x %x\n", ecc1[0], ecc1[1], ecc1[2]);
1918 + printk("correction : %x %x %x\n", ecc2[0], ecc2[1], ecc2[2]);
1921 + for (i = 0; i < CONFIG_ECC_BYTES; i++)
1923 + nibble = *(p+i) & 0xf;
1924 + if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
1925 + (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
1927 + nibble = ((*(p+i)) >> 4) & 0xf;
1928 + if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
1929 + (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
1934 + for (i = 0; i < CONFIG_ECC_BYTES; i++)
1936 + nibble = *(p+i) & 0xf;
1937 + if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
1938 + (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
1940 + nibble = ((*(p+i)) >> 4) & 0xf;
1941 + if ((nibble != 0x0) && (nibble != 0xf) && (nibble != 0x3) && (nibble != 0xc) &&
1942 + (nibble != 0x5) && (nibble != 0xa) && (nibble != 0x6) && (nibble != 0x9))
1946 + memcpy(&iecc1, ecc1, 3);
1947 + memcpy(&iecc2, ecc2, 3);
1949 + xor = iecc1 ^ iecc2;
1950 + printk("xor = %x (%x %x)\n", xor, iecc1, iecc2);
1953 + for (i = 0; i < 9; i++)
1955 + crumb = (xor >> (2*i)) & 0x3;
1956 + if ((crumb == 0x0) || (crumb == 0x3))
1959 + *bytes += (1 << i);
1963 + for (i = 0; i < 3; i++)
1965 + crumb = (xor >> (18 + 2*i)) & 0x3;
1966 + if ((crumb == 0x0) || (crumb == 0x3))
1969 + *bits += (1 << i);
1977 +/************************************************************
1978 + * the init/exit section.
1981 +static struct nand_ecclayout ra_oob_layout = {
1982 + .eccbytes = CONFIG_ECC_BYTES,
1983 + .eccpos = {5, 6, 7},
1985 + {.offset = 0, .length = 4},
1986 + {.offset = 8, .length = 8},
1987 + {.offset = 0, .length = 0}
1989 +#define RA_CHIP_OOB_AVAIL (4+8)
1990 + .oobavail = RA_CHIP_OOB_AVAIL,
1991 + // 5th byte is bad-block flag.
1995 +mtk_nand_probe(struct platform_device *pdev)
1997 + struct mtd_part_parser_data ppdata;
1998 + struct ra_nand_chip *ra;
1999 + int alloc_size, bbt_size, buffers_size, reg, err;
2000 + unsigned char chip_mode = 12;
2002 +/* if(ra_check_flash_type()!=BOOT_FROM_NAND) {
2006 + //FIXME: config 512 or 2048-byte page according to HWCONF
2007 +#if defined (CONFIG_RALINK_RT6855A)
2008 + reg = ra_inl(RALINK_SYSCTL_BASE+0x8c);
2009 + chip_mode = ((reg>>28) & 0x3)|(((reg>>22) & 0x3)<<2);
2010 + if (chip_mode == 1) {
2011 + printk("! nand 2048\n");
2012 + ra_or(NFC_CONF1, 1);
2013 + is_nand_page_2048 = 1;
2017 + printk("! nand 512\n");
2018 + ra_and(NFC_CONF1, ~1);
2019 + is_nand_page_2048 = 0;
2022 +#elif (defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_RT6855))
2023 + ra_outl(RALINK_SYSCTL_BASE+0x60, ra_inl(RALINK_SYSCTL_BASE+0x60) & ~(0x3<<18));
2024 + reg = ra_inl(RALINK_SYSCTL_BASE+0x10);
2025 + chip_mode = (reg & 0x0F);
2026 + if((chip_mode==1)||(chip_mode==11)) {
2027 + ra_or(NFC_CONF1, 1);
2028 + is_nand_page_2048 = 1;
2029 + nand_addrlen = ((chip_mode!=11) ? 4 : 5);
2030 + printk("!!! nand page size = 2048, addr len=%d\n", nand_addrlen);
2033 + ra_and(NFC_CONF1, ~1);
2034 + is_nand_page_2048 = 0;
2035 + nand_addrlen = ((chip_mode!=10) ? 3 : 4);
2036 + printk("!!! nand page size = 512, addr len=%d\n", nand_addrlen);
2039 + is_nand_page_2048 = 0;
2041 + printk("!!! nand page size = 512, addr len=%d\n", nand_addrlen);
2044 +#if defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_RT6855)
2045 + //config ECC location
2046 + ra_and(NFC_CONF1, 0xfff000ff);
2047 + ra_or(NFC_CONF1, ((CONFIG_ECC_OFFSET + 2) << 16) +
2048 + ((CONFIG_ECC_OFFSET + 1) << 12) +
2049 + (CONFIG_ECC_OFFSET << 8));
2052 +#define ALIGNE_16(a) (((unsigned long)(a)+15) & ~15)
2053 + buffers_size = ALIGNE_16((1<<CONFIG_PAGE_SIZE_BIT) + (1<<CONFIG_OOBSIZE_PER_PAGE_BIT)); //ra->buffers
2054 + bbt_size = BBTTAG_BITS * (1<<(CONFIG_CHIP_SIZE_BIT - (CONFIG_PAGE_SIZE_BIT + CONFIG_NUMPAGE_PER_BLOCK_BIT))) / 8; //ra->bbt
2055 + bbt_size = ALIGNE_16(bbt_size);
2057 + alloc_size = buffers_size + bbt_size;
2058 + alloc_size += buffers_size; //for ra->readback_buffers
2059 + alloc_size += sizeof(*ra);
2060 + alloc_size += sizeof(*ranfc_mtd);
2062 + //make sure gpio-0 is input
2063 + ra_outl(RALINK_PIO_BASE+0x24, ra_inl(RALINK_PIO_BASE+0x24) & ~0x01);
2065 + ra = (struct ra_nand_chip *)kzalloc(alloc_size, GFP_KERNEL | GFP_DMA);
2067 + printk("%s: mem alloc fail \n", __func__);
2070 + memset(ra, 0, alloc_size);
2073 + ra->buffers = (char *)((char *)ra + sizeof(*ra));
2074 + ra->readback_buffers = ra->buffers + buffers_size;
2075 + ra->bbt = ra->readback_buffers + buffers_size;
2076 + ranfc_mtd = (struct mtd_info *)(ra->bbt + bbt_size);
2079 + ra->numchips = CONFIG_NUMCHIPS;
2080 + ra->chip_shift = CONFIG_CHIP_SIZE_BIT;
2081 + ra->page_shift = CONFIG_PAGE_SIZE_BIT;
2082 + ra->oob_shift = CONFIG_OOBSIZE_PER_PAGE_BIT;
2083 + ra->erase_shift = (CONFIG_PAGE_SIZE_BIT + CONFIG_NUMPAGE_PER_BLOCK_BIT);
2084 + ra->badblockpos = CONFIG_BAD_BLOCK_POS;
2085 + ra_oob_layout.eccpos[0] = CONFIG_ECC_OFFSET;
2086 + ra_oob_layout.eccpos[1] = CONFIG_ECC_OFFSET + 1;
2087 + ra_oob_layout.eccpos[2] = CONFIG_ECC_OFFSET + 2;
2088 + ra->oob = &ra_oob_layout;
2089 + ra->buffers_page = -1;
2091 +#if defined (WORKAROUND_RX_BUF_OV)
2092 + if (ranfc_verify) {
2093 + ra->sandbox_page = nand_bbt_find_sandbox(ra);
2096 + ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x01); //set wp to high
2099 + ranfc_mtd->type = MTD_NANDFLASH;
2100 + ranfc_mtd->flags = MTD_CAP_NANDFLASH;
2101 + ranfc_mtd->size = CONFIG_NUMCHIPS * CFG_CHIPSIZE;
2102 + ranfc_mtd->erasesize = CFG_BLOCKSIZE;
2103 + ranfc_mtd->writesize = CFG_PAGESIZE;
2104 + ranfc_mtd->oobsize = CFG_PAGE_OOBSIZE;
2105 + ranfc_mtd->oobavail = RA_CHIP_OOB_AVAIL;
2106 + ranfc_mtd->name = "ra_nfc";
2107 + //ranfc_mtd->index
2108 + ranfc_mtd->ecclayout = &ra_oob_layout;
2109 + //ranfc_mtd->numberaseregions
2110 + //ranfc_mtd->eraseregions
2111 + //ranfc_mtd->bansize
2112 + ranfc_mtd->_erase = ramtd_nand_erase;
2113 + //ranfc_mtd->point
2114 + //ranfc_mtd->unpoint
2115 + ranfc_mtd->_read = ramtd_nand_read;
2116 + ranfc_mtd->_write = ramtd_nand_write;
2117 + ranfc_mtd->_read_oob = ramtd_nand_readoob;
2118 + ranfc_mtd->_write_oob = ramtd_nand_writeoob;
2119 + //ranfc_mtd->get_fact_prot_info; ranfc_mtd->read_fact_prot_reg;
2120 + //ranfc_mtd->get_user_prot_info; ranfc_mtd->read_user_prot_reg;
2121 + //ranfc_mtd->write_user_prot_reg; ranfc_mtd->lock_user_prot_reg;
2122 + //ranfc_mtd->writev; ranfc_mtd->sync; ranfc_mtd->lock; ranfc_mtd->unlock; ranfc_mtd->suspend; ranfc_mtd->resume;
2123 + ranfc_mtd->_block_isbad = ramtd_nand_block_isbad;
2124 + ranfc_mtd->_block_markbad = ramtd_nand_block_markbad;
2125 + //ranfc_mtd->reboot_notifier
2126 + //ranfc_mtd->ecc_stats;
2129 + //ranfc_mtd->get_device; ranfc_mtd->put_device
2130 + ranfc_mtd->priv = ra;
2132 + ranfc_mtd->owner = THIS_MODULE;
2133 + ra->controller = &ra->hwcontrol;
2134 + mutex_init(ra->controller);
2136 + printk("%s: alloc %x, at %p , btt(%p, %x), ranfc_mtd:%p\n",
2137 + __func__ , alloc_size, ra, ra->bbt, bbt_size, ranfc_mtd);
2139 + ppdata.of_node = pdev->dev.of_node;
2140 + err = mtd_device_parse_register(ranfc_mtd, mtk_probe_types,
2141 + &ppdata, NULL, 0);
2147 +mtk_nand_remove(struct platform_device *pdev)
2149 + struct ra_nand_chip *ra;
2152 + ra = (struct ra_nand_chip *)ranfc_mtd->priv;
2154 + /* Deregister partitions */
2155 + //del_mtd_partitions(ranfc_mtd);
2161 +static const struct of_device_id mtk_nand_match[] = {
2162 + { .compatible = "mtk,mt7620-nand" },
2165 +MODULE_DEVICE_TABLE(of, mtk_nand_match);
2167 +static struct platform_driver mtk_nand_driver = {
2168 + .probe = mtk_nand_probe,
2169 + .remove = mtk_nand_remove,
2171 + .name = "mt7620_nand",
2172 + .owner = THIS_MODULE,
2173 + .of_match_table = mtk_nand_match,
2177 +module_platform_driver(mtk_nand_driver);
2180 +MODULE_LICENSE("GPL");
2181 Index: linux-3.10.18/drivers/mtd/maps/ralink_nand.h
2182 ===================================================================
2183 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2184 +++ linux-3.10.18/drivers/mtd/maps/ralink_nand.h 2013-11-17 17:51:50.549024547 +0100
2186 +#ifndef RT2880_NAND_H
2187 +#define RT2880_NAND_H
2189 +#include <linux/mtd/mtd.h>
2191 +//#include "gdma.h"
2193 +#define RALINK_SYSCTL_BASE 0xB0000000
2194 +#define RALINK_PIO_BASE 0xB0000600
2195 +#define RALINK_NAND_CTRL_BASE 0xB0000810
2196 +#define CONFIG_RALINK_MT7620
2198 +#define SKIP_BAD_BLOCK
2199 +//#define RANDOM_GEN_BAD_BLOCK
2201 +#define ra_inl(addr) (*(volatile unsigned int *)(addr))
2202 +#define ra_outl(addr, value) (*(volatile unsigned int *)(addr) = (value))
2203 +#define ra_aor(addr, a_mask, o_value) ra_outl(addr, (ra_inl(addr) & (a_mask)) | (o_value))
2204 +#define ra_and(addr, a_mask) ra_aor(addr, a_mask, 0)
2205 +#define ra_or(addr, o_value) ra_aor(addr, -1, o_value)
2208 +#define CONFIG_NUMCHIPS 1
2209 +#define CONFIG_NOT_SUPPORT_WP //rt3052 has no WP signal for chip.
2210 +//#define CONFIG_NOT_SUPPORT_RB
2212 +extern int is_nand_page_2048;
2213 +extern const unsigned int nand_size_map[2][3];
2216 +// chip geometry: SAMSUNG small size 32MB.
2217 +#define CONFIG_CHIP_SIZE_BIT (nand_size_map[is_nand_page_2048][nand_addrlen-3]) //! (1<<NAND_SIZE_BYTE) MB
2218 +//#define CONFIG_CHIP_SIZE_BIT (is_nand_page_2048? 29 : 25) //! (1<<NAND_SIZE_BYTE) MB
2219 +#define CONFIG_PAGE_SIZE_BIT (is_nand_page_2048? 11 : 9) //! (1<<PAGE_SIZE) MB
2220 +//#define CONFIG_SUBPAGE_BIT 1 //! these bits will be compensate by command cycle
2221 +#define CONFIG_NUMPAGE_PER_BLOCK_BIT (is_nand_page_2048? 6 : 5) //! order of number of pages a block.
2222 +#define CONFIG_OOBSIZE_PER_PAGE_BIT (is_nand_page_2048? 6 : 4) //! byte number of oob a page.
2223 +#define CONFIG_BAD_BLOCK_POS (is_nand_page_2048? 0 : 4) //! offset of byte to denote bad block.
2224 +#define CONFIG_ECC_BYTES 3 //! ecc has 3 bytes
2225 +#define CONFIG_ECC_OFFSET (is_nand_page_2048? 6 : 5) //! ecc starts from offset 5.
2227 +//this section should not be modified.
2228 +//#define CFG_COLUMN_ADDR_MASK ((1 << (CONFIG_PAGE_SIZE_BIT - CONFIG_SUBPAGE_BIT)) - 1)
2229 +//#define CFG_COLUMN_ADDR_CYCLE (((CONFIG_PAGE_SIZE_BIT - CONFIG_SUBPAGE_BIT) + 7)/8)
2230 +//#define CFG_ROW_ADDR_CYCLE ((CONFIG_CHIP_SIZE_BIT - CONFIG_PAGE_SIZE_BIT + 7)/8)
2231 +//#define CFG_ADDR_CYCLE (CFG_COLUMN_ADDR_CYCLE + CFG_ROW_ADDR_CYCLE)
2233 +#define CFG_COLUMN_ADDR_CYCLE (is_nand_page_2048? 2 : 1)
2234 +#define CFG_ROW_ADDR_CYCLE (nand_addrlen - CFG_COLUMN_ADDR_CYCLE)
2235 +#define CFG_ADDR_CYCLE (CFG_COLUMN_ADDR_CYCLE + CFG_ROW_ADDR_CYCLE)
2237 +#define CFG_CHIPSIZE (1 << ((CONFIG_CHIP_SIZE_BIT>=32)? 31 : CONFIG_CHIP_SIZE_BIT))
2238 +//#define CFG_CHIPSIZE (1 << CONFIG_CHIP_SIZE_BIT)
2239 +#define CFG_PAGESIZE (1 << CONFIG_PAGE_SIZE_BIT)
2240 +#define CFG_BLOCKSIZE (CFG_PAGESIZE << CONFIG_NUMPAGE_PER_BLOCK_BIT)
2241 +#define CFG_NUMPAGE (1 << (CONFIG_CHIP_SIZE_BIT - CONFIG_PAGE_SIZE_BIT))
2242 +#define CFG_NUMBLOCK (CFG_NUMPAGE >> CONFIG_NUMPAGE_PER_BLOCK_BIT)
2243 +#define CFG_BLOCK_OOBSIZE (1 << (CONFIG_OOBSIZE_PER_PAGE_BIT + CONFIG_NUMPAGE_PER_BLOCK_BIT))
2244 +#define CFG_PAGE_OOBSIZE (1 << CONFIG_OOBSIZE_PER_PAGE_BIT)
2246 +#define NAND_BLOCK_ALIGN(addr) ((addr) & (CFG_BLOCKSIZE-1))
2247 +#define NAND_PAGE_ALIGN(addr) ((addr) & (CFG_PAGESIZE-1))
2250 +#define NFC_BASE RALINK_NAND_CTRL_BASE
2251 +#define NFC_CTRL (NFC_BASE + 0x0)
2252 +#define NFC_CONF (NFC_BASE + 0x4)
2253 +#define NFC_CMD1 (NFC_BASE + 0x8)
2254 +#define NFC_CMD2 (NFC_BASE + 0xc)
2255 +#define NFC_CMD3 (NFC_BASE + 0x10)
2256 +#define NFC_ADDR (NFC_BASE + 0x14)
2257 +#define NFC_DATA (NFC_BASE + 0x18)
2258 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
2259 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
2260 +#define NFC_ECC (NFC_BASE + 0x30)
2262 +#define NFC_ECC (NFC_BASE + 0x1c)
2264 +#define NFC_STATUS (NFC_BASE + 0x20)
2265 +#define NFC_INT_EN (NFC_BASE + 0x24)
2266 +#define NFC_INT_ST (NFC_BASE + 0x28)
2267 +#if defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_RT6855A) || \
2268 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
2269 +#define NFC_CONF1 (NFC_BASE + 0x2c)
2270 +#define NFC_ECC_P1 (NFC_BASE + 0x30)
2271 +#define NFC_ECC_P2 (NFC_BASE + 0x34)
2272 +#define NFC_ECC_P3 (NFC_BASE + 0x38)
2273 +#define NFC_ECC_P4 (NFC_BASE + 0x3c)
2274 +#define NFC_ECC_ERR1 (NFC_BASE + 0x40)
2275 +#define NFC_ECC_ERR2 (NFC_BASE + 0x44)
2276 +#define NFC_ECC_ERR3 (NFC_BASE + 0x48)
2277 +#define NFC_ECC_ERR4 (NFC_BASE + 0x4c)
2278 +#define NFC_ADDR2 (NFC_BASE + 0x50)
2282 + INT_ST_ND_DONE = 1<<0,
2283 + INT_ST_TX_BUF_RDY = 1<<1,
2284 + INT_ST_RX_BUF_RDY = 1<<2,
2285 + INT_ST_ECC_ERR = 1<<3,
2286 + INT_ST_TX_TRAS_ERR = 1<<4,
2287 + INT_ST_RX_TRAS_ERR = 1<<5,
2288 + INT_ST_TX_KICK_ERR = 1<<6,
2289 + INT_ST_RX_KICK_ERR = 1<<7
2293 +//#define WORKAROUND_RX_BUF_OV 1
2296 +/*************************************************************
2297 + * stolen from nand.h
2298 + *************************************************************/
2301 + * Standard NAND flash commands
2303 +#define NAND_CMD_READ0 0
2304 +#define NAND_CMD_READ1 1
2305 +#define NAND_CMD_RNDOUT 5
2306 +#define NAND_CMD_PAGEPROG 0x10
2307 +#define NAND_CMD_READOOB 0x50
2308 +#define NAND_CMD_ERASE1 0x60
2309 +#define NAND_CMD_STATUS 0x70
2310 +#define NAND_CMD_STATUS_MULTI 0x71
2311 +#define NAND_CMD_SEQIN 0x80
2312 +#define NAND_CMD_RNDIN 0x85
2313 +#define NAND_CMD_READID 0x90
2314 +#define NAND_CMD_ERASE2 0xd0
2315 +#define NAND_CMD_RESET 0xff
2317 +/* Extended commands for large page devices */
2318 +#define NAND_CMD_READSTART 0x30
2319 +#define NAND_CMD_RNDOUTSTART 0xE0
2320 +#define NAND_CMD_CACHEDPROG 0x15
2322 +/* Extended commands for AG-AND device */
2324 + * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
2325 + * there is no way to distinguish that from NAND_CMD_READ0
2326 + * until the remaining sequence of commands has been completed
2327 + * so add a high order bit and mask it off in the command.
2329 +#define NAND_CMD_DEPLETE1 0x100
2330 +#define NAND_CMD_DEPLETE2 0x38
2331 +#define NAND_CMD_STATUS_MULTI 0x71
2332 +#define NAND_CMD_STATUS_ERROR 0x72
2333 +/* multi-bank error status (banks 0-3) */
2334 +#define NAND_CMD_STATUS_ERROR0 0x73
2335 +#define NAND_CMD_STATUS_ERROR1 0x74
2336 +#define NAND_CMD_STATUS_ERROR2 0x75
2337 +#define NAND_CMD_STATUS_ERROR3 0x76
2338 +#define NAND_CMD_STATUS_RESET 0x7f
2339 +#define NAND_CMD_STATUS_CLEAR 0xff
2341 +#define NAND_CMD_NONE -1
2344 +#define NAND_STATUS_FAIL 0x01
2345 +#define NAND_STATUS_FAIL_N1 0x02
2346 +#define NAND_STATUS_TRUE_READY 0x20
2347 +#define NAND_STATUS_READY 0x40
2348 +#define NAND_STATUS_WP 0x80
2360 +/*************************************************************/
2364 +typedef enum _ra_flags {
2366 + FLAG_ECC_EN = (1<<0),
2367 + FLAG_USE_GDMA = (1<<1),
2368 + FLAG_VERIFY = (1<<2),
2372 +#define BBTTAG_BITS 2
2373 +#define BBTTAG_BITS_MASK ((1<<BBTTAG_BITS) -1)
2375 + BBT_TAG_UNKNOWN = 0, //2'b01
2376 + BBT_TAG_GOOD = 3, //2'b11
2377 + BBT_TAG_BAD = 2, //2'b10
2378 + BBT_TAG_RES = 1, //2'b01
2381 +struct ra_nand_chip {
2388 +#if !defined (__UBOOT__)
2389 + struct mutex hwcontrol;
2390 + struct mutex *controller;
2392 + struct nand_ecclayout *oob;
2394 + unsigned int buffers_page;
2395 + char *buffers; //[CFG_PAGESIZE + CFG_PAGE_OOBSIZE];
2396 + char *readback_buffers;
2397 + unsigned char *bbt;
2398 +#if defined (WORKAROUND_RX_BUF_OV)
2399 + unsigned int sandbox_page; // steal a page (block) for read ECC verification
2407 +int nand_dma_sync(void);
2408 +void release_dma_buf(void);
2409 +int set_gdma_ch(unsigned long dst,
2410 + unsigned long src, unsigned int len, int burst_size,
2411 + int soft_mode, int src_req_type, int dst_req_type,
2412 + int src_burst_mode, int dst_burst_mode);