target/linux/ramips/patches-3.10/0511-MIPS-GIC-Send-IPIs-using-the-GIC.patch

   1 From 43334f8438704001deb258b6e7223699bd336c77 Mon Sep 17 00:00:00 2001
   2 From: "Steven J. Hill" <Steven.Hill@imgtec.com>
   3 Date: Wed, 25 Sep 2013 14:58:19 -0500
   4 Subject: [PATCH 093/105] MIPS: GIC: Send IPIs using the GIC.
   5
   6 If a GIC present, then use it to send IPIs between the cores.
   7
   8 Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
   9 ---
  10  arch/mips/kernel/smp-mt.c |   32 ++++++++++++++++++++++++++++++++
  11  1 file changed, 32 insertions(+)
  12
  13 diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
  14 index 2f8c468..d057c84 100644
  15 --- a/arch/mips/kernel/smp-mt.c
  16 +++ b/arch/mips/kernel/smp-mt.c
  17 @@ -71,6 +71,7 @@ static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
  18
  19                 /* Record this as available CPU */
  20                 set_cpu_possible(tc, true);
  21 +               set_cpu_present(tc, true);
  22                 __cpu_number_map[tc]    = ++ncpu;
  23                 __cpu_logical_map[ncpu] = tc;
  24         }
  25 @@ -112,12 +113,35 @@ static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
  26         write_tc_c0_tchalt(TCHALT_H);
  27  }
  28
  29 +static void mp_send_ipi_single(int cpu, unsigned int action)
  30 +{
  31 +       unsigned long flags;
  32 +
  33 +       local_irq_save(flags);
  34 +
  35 +       switch (action) {
  36 +       case SMP_CALL_FUNCTION:
  37 +               gic_send_ipi(plat_ipi_call_int_xlate(cpu));
  38 +               break;
  39 +
  40 +       case SMP_RESCHEDULE_YOURSELF:
  41 +               gic_send_ipi(plat_ipi_resched_int_xlate(cpu));
  42 +               break;
  43 +       }
  44 +
  45 +       local_irq_restore(flags);
  46 +}
  47 +
  48  static void vsmp_send_ipi_single(int cpu, unsigned int action)
  49  {
  50         int i;
  51         unsigned long flags;
  52         int vpflags;
  53
  54 +       if (gic_present) {
  55 +               mp_send_ipi_single(cpu, action);
  56 +               return;
  57 +       }
  58         local_irq_save(flags);
  59
  60         vpflags = dvpe();       /* can't access the other CPU's registers whilst MVPE enabled */
  61 @@ -164,6 +188,8 @@ static void __cpuinit vsmp_init_secondary(void)
  62
  63  static void __cpuinit vsmp_smp_finish(void)
  64  {
  65 +       pr_debug("SMPMT: CPU%d: vsmp_smp_finish\n", smp_processor_id());
  66 +
  67         /* CDFIXME: remove this? */
  68         write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
  69
  70 @@ -178,6 +204,7 @@ static void __cpuinit vsmp_smp_finish(void)
  71
  72  static void vsmp_cpus_done(void)
  73  {
  74 +       pr_debug("SMPMT: CPU%d: vsmp_cpus_done\n", smp_processor_id());
  75  }
  76
  77  /*
  78 @@ -191,6 +218,8 @@ static void vsmp_cpus_done(void)
  79  static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle)
  80  {
  81         struct thread_info *gp = task_thread_info(idle);
  82 +       pr_debug("SMPMT: CPU%d: vsmp_boot_secondary cpu %d\n",
  83 +               smp_processor_id(), cpu);
  84         dvpe();
  85         set_c0_mvpcontrol(MVPCONTROL_VPC);
  86
  87 @@ -232,6 +261,7 @@ static void __init vsmp_smp_setup(void)
  88         unsigned int mvpconf0, ntc, tc, ncpu = 0;
  89         unsigned int nvpe;
  90
  91 +       pr_debug("SMPMT: CPU%d: vsmp_smp_setup\n", smp_processor_id());
  92  #ifdef CONFIG_MIPS_MT_FPAFF
  93         /* If we have an FPU, enroll ourselves in the FPU-full mask */
  94         if (cpu_has_fpu)
  95 @@ -272,6 +302,8 @@ static void __init vsmp_smp_setup(void)
  96
  97  static void __init vsmp_prepare_cpus(unsigned int max_cpus)
  98  {
  99 +       pr_debug("SMPMT: CPU%d: vsmp_prepare_cpus %d\n",
 100 +               smp_processor_id(), max_cpus);
 101         mips_mt_set_cpuoptions();
 102  }
 103
 104 --
 105 1.7.10.4
 106