1 From b1cc9a15f6ead8dbd849257e42d69a5799fb7597 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 6 Aug 2014 18:24:36 +0200
4 Subject: [PATCH 25/57] MIPS: ralink: allow loading irq registers from the
7 Signed-off-by: John Crispin <blogic@openwrt.org>
9 arch/mips/ralink/irq.c | 33 +++++++++++++++++++++++----------
10 1 file changed, 23 insertions(+), 10 deletions(-)
12 --- a/arch/mips/ralink/irq.c
13 +++ b/arch/mips/ralink/irq.c
18 -/* INTC register offsets */
19 -#define INTC_REG_STATUS0 0x00
20 -#define INTC_REG_STATUS1 0x04
21 -#define INTC_REG_TYPE 0x20
22 -#define INTC_REG_RAW_STATUS 0x30
23 -#define INTC_REG_ENABLE 0x34
24 -#define INTC_REG_DISABLE 0x38
26 #define INTC_INT_GLOBAL BIT(31)
28 #define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
31 #define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9)
33 +enum rt_intc_regs_enum {
34 + INTC_REG_STATUS0 = 0,
37 + INTC_REG_RAW_STATUS,
42 +static u32 rt_intc_regs[] = {
43 + [INTC_REG_STATUS0] = 0x00,
44 + [INTC_REG_STATUS1] = 0x04,
45 + [INTC_REG_TYPE] = 0x20,
46 + [INTC_REG_RAW_STATUS] = 0x30,
47 + [INTC_REG_ENABLE] = 0x34,
48 + [INTC_REG_DISABLE] = 0x38,
51 static void __iomem *rt_intc_membase;
53 static inline void rt_intc_w32(u32 val, unsigned reg)
55 - __raw_writel(val, rt_intc_membase + reg);
56 + __raw_writel(val, rt_intc_membase + rt_intc_regs[reg]);
59 static inline u32 rt_intc_r32(unsigned reg)
61 - return __raw_readl(rt_intc_membase + reg);
62 + return __raw_readl(rt_intc_membase + rt_intc_regs[reg]);
65 static void ralink_intc_irq_unmask(struct irq_data *d)
66 @@ -134,6 +144,9 @@ static int __init intc_of_init(struct de
67 struct irq_domain *domain;
70 + if (!of_property_read_u32_array(node, "ralink,intc-registers", rt_intc_regs, 6))
71 + pr_info("intc: using register map from devicetree\n");
73 irq = irq_of_parse_and_map(node, 0);
75 panic("Failed to get INTC IRQ");