1 From 307b7a71a634ae3848fb7c5c05759d647e140e12 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sat, 18 May 2013 22:06:15 +0200
4 Subject: [PATCH 32/57] PCI: MIPS: adds mt7620a pcie driver
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/pci/Makefile | 1 +
9 arch/mips/pci/pci-mt7620a.c | 363 +++++++++++++++++++++++++++++++++++++++++++
10 arch/mips/ralink/Kconfig | 1 +
11 3 files changed, 365 insertions(+)
12 create mode 100644 arch/mips/pci/pci-mt7620a.c
14 --- a/arch/mips/pci/Makefile
15 +++ b/arch/mips/pci/Makefile
16 @@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
17 obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
18 obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
19 obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
20 +obj-$(CONFIG_SOC_MT7620) += pci-mt7620a.o
21 obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
22 obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
23 obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
25 +++ b/arch/mips/pci/pci-mt7620a.c
28 + * Ralink MT7620A SoC PCI support
30 + * Copyright (C) 2007-2013 Bruce Chang
31 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
33 + * This program is free software; you can redistribute it and/or modify it
34 + * under the terms of the GNU General Public License version 2 as published
35 + * by the Free Software Foundation.
38 +#include <linux/types.h>
39 +#include <linux/pci.h>
40 +#include <linux/io.h>
41 +#include <linux/init.h>
42 +#include <linux/delay.h>
43 +#include <linux/interrupt.h>
44 +#include <linux/module.h>
45 +#include <linux/of.h>
46 +#include <linux/of_irq.h>
47 +#include <linux/of_pci.h>
48 +#include <linux/reset.h>
49 +#include <linux/platform_device.h>
51 +#include <asm/mach-ralink/ralink_regs.h>
53 +#define RALINK_PCI_MM_MAP_BASE 0x20000000
54 +#define RALINK_PCI_IO_MAP_BASE 0x10160000
56 +#define RALINK_INT_PCIE0 4
57 +#define RALINK_SYSTEM_CONTROL_BASE 0xb0000000
58 +#define RALINK_SYSCFG1 0x14
59 +#define RALINK_CLKCFG1 0x30
60 +#define RALINK_GPIOMODE 0x60
61 +#define RALINK_PCIE_CLK_GEN 0x7c
62 +#define RALINK_PCIE_CLK_GEN1 0x80
63 +#define PCIEPHY0_CFG 0x90
64 +#define PPLL_CFG1 0x9c
65 +#define PPLL_DRV 0xa0
66 +#define RALINK_PCI_HOST_MODE_EN (1<<7)
67 +#define RALINK_PCIE_RC_MODE_EN (1<<8)
68 +#define RALINK_PCIE_RST (1<<23)
69 +#define RALINK_PCI_RST (1<<24)
70 +#define RALINK_PCI_CLK_EN (1<<19)
71 +#define RALINK_PCIE_CLK_EN (1<<21)
72 +#define PCI_SLOTx2 (1<<11)
73 +#define PCI_SLOTx1 (2<<11)
74 +#define PDRV_SW_SET (1<<31)
75 +#define LC_CKDRVPD_ (1<<19)
77 +#define RALINK_PCI_CONFIG_ADDR 0x20
78 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
79 +#define MEMORY_BASE 0x0
80 +#define RALINK_PCIE0_RST (1<<26)
81 +#define RALINK_PCI_BASE 0xB0140000
82 +#define RALINK_PCI_MEMBASE 0x28
83 +#define RALINK_PCI_IOBASE 0x2C
85 +#define RT6855_PCIE0_OFFSET 0x2000
87 +#define RALINK_PCI_PCICFG_ADDR 0x00
88 +#define RALINK_PCI0_BAR0SETUP_ADDR 0x10
89 +#define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
90 +#define RALINK_PCI0_ID 0x30
91 +#define RALINK_PCI0_CLASS 0x34
92 +#define RALINK_PCI0_SUBID 0x38
93 +#define RALINK_PCI0_STATUS 0x50
94 +#define RALINK_PCI_PCIMSK_ADDR 0x0C
96 +#define RALINK_PCIE0_CLK_EN (1 << 26)
98 +#define BUSY 0x80000000
99 +#define WAITRETRY_MAX 10
100 +#define WRITE_MODE (1UL << 23)
101 +#define DATA_SHIFT 0
102 +#define ADDR_SHIFT 8
105 +static void __iomem *bridge_base;
106 +static void __iomem *pcie_base;
108 +static struct reset_control *rstpcie0;
110 +static inline void bridge_w32(u32 val, unsigned reg)
112 + iowrite32(val, bridge_base + reg);
115 +static inline u32 bridge_r32(unsigned reg)
117 + return ioread32(bridge_base + reg);
120 +static inline void pcie_w32(u32 val, unsigned reg)
122 + iowrite32(val, pcie_base + reg);
125 +static inline u32 pcie_r32(unsigned reg)
127 + return ioread32(pcie_base + reg);
130 +static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
132 + u32 val = pcie_r32(reg);
135 + pcie_w32(val, reg);
138 +int wait_pciephy_busy(void)
140 + unsigned long reg_value = 0x0, retry = 0;
143 + //reg_value = rareg(READMODE, PCIEPHY0_CFG, 0);
144 + reg_value = pcie_r32(PCIEPHY0_CFG);
146 + if (reg_value & BUSY)
150 + if (retry++ > WAITRETRY_MAX){
151 + printk("PCIE-PHY retry failed.\n");
158 +static void pcie_phy(unsigned long addr, unsigned long val)
160 + wait_pciephy_busy();
161 + pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
163 + wait_pciephy_busy();
166 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
168 + unsigned int slot = PCI_SLOT(devfn);
169 + u8 func = PCI_FUNC(devfn);
173 + address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
174 + bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
175 + data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
179 + *val = (data >> ((where & 3) << 3)) & 0xff;
182 + *val = (data >> ((where & 3) << 3)) & 0xffff;
189 + return PCIBIOS_SUCCESSFUL;
192 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
194 + unsigned int slot = PCI_SLOT(devfn);
195 + u8 func = PCI_FUNC(devfn);
199 + address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
200 + bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
201 + data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
205 + data = (data & ~(0xff << ((where & 3) << 3))) |
206 + (val << ((where & 3) << 3));
209 + data = (data & ~(0xffff << ((where & 3) << 3))) |
210 + (val << ((where & 3) << 3));
217 + bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
219 + return PCIBIOS_SUCCESSFUL;
222 +struct pci_ops mt7620a_pci_ops= {
223 + .read = pci_config_read,
224 + .write = pci_config_write,
227 +static struct resource mt7620a_res_pci_mem1 = {
228 + .name = "pci memory",
229 + .start = RALINK_PCI_MM_MAP_BASE,
230 + .end = (u32) ((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
231 + .flags = IORESOURCE_MEM,
233 +static struct resource mt7620a_res_pci_io1 = {
235 + .start = RALINK_PCI_IO_MAP_BASE,
236 + .end = (u32) ((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
237 + .flags = IORESOURCE_IO,
240 +struct pci_controller mt7620a_controller = {
241 + .pci_ops = &mt7620a_pci_ops,
242 + .mem_resource = &mt7620a_res_pci_mem1,
243 + .io_resource = &mt7620a_res_pci_io1,
244 + .mem_offset = 0x00000000UL,
245 + .io_offset = 0x00000000UL,
246 + .io_map_base = 0xa0000000,
249 +static int mt7620a_pci_probe(struct platform_device *pdev)
251 + struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
252 + struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
254 + rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
255 + if (IS_ERR(rstpcie0))
256 + return PTR_ERR(rstpcie0);
258 + bridge_base = devm_request_and_ioremap(&pdev->dev, bridge_res);
262 + pcie_base = devm_request_and_ioremap(&pdev->dev, pcie_res);
266 + iomem_resource.start = 0;
267 + iomem_resource.end= ~0;
268 + ioport_resource.start= 0;
269 + ioport_resource.end = ~0;
271 + /* PCIE: bypass PCIe DLL */
272 + pcie_phy(0x0, 0x80);
273 + pcie_phy(0x1, 0x04);
274 + /* PCIE: Elastic buffer control */
275 + pcie_phy(0x68, 0xB4);
277 + reset_control_assert(rstpcie0);
278 + rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
279 + rt_sysc_m32(1<<19, 1<<31, PPLL_DRV);
280 + rt_sysc_m32(0x3 << 16, 0, RALINK_GPIOMODE);
282 + reset_control_deassert(rstpcie0);
283 + rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
287 + if (!(rt_sysc_r32(PPLL_CFG1) & 1<<23)) {
288 + printk("MT7620 PPLL unlock\n");
289 + reset_control_assert(rstpcie0);
290 + rt_sysc_m32(BIT(26), 0, RALINK_CLKCFG1);
293 + rt_sysc_m32((0x1<<18) | (0x1<<17), (0x1 << 19) | (0x1 << 31), PPLL_DRV);
296 + reset_control_assert(rstpcie0);
297 + rt_sysc_m32(0x30, 2 << 4, RALINK_SYSCFG1);
299 + rt_sysc_m32(~0x7fffffff, 0x80000000, RALINK_PCIE_CLK_GEN);
300 + rt_sysc_m32(~0x80ffffff, 0xa << 24, RALINK_PCIE_CLK_GEN1);
303 + reset_control_deassert(rstpcie0);
304 + pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
307 + if (( pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
308 + reset_control_assert(rstpcie0);
309 + rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
310 + rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
311 + printk("PCIE0 no card, disable it(RST&CLK)\n");
314 + bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
315 + bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
317 + pcie_w32(0x7FFF0000, RALINK_PCI0_BAR0SETUP_ADDR);
318 + pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
319 + pcie_w32(0x08021814, RALINK_PCI0_ID);
320 + pcie_w32(0x06040001, RALINK_PCI0_CLASS);
321 + pcie_w32(0x28801814, RALINK_PCI0_SUBID);
322 + pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
324 + register_pci_controller(&mt7620a_controller);
329 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
331 + const struct resource *res;
336 + if ((dev->bus->number == 0) && (slot == 0)) {
337 + pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
338 + pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
339 + pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
340 + } else if ((dev->bus->number == 1) && (slot == 0x0)) {
341 + irq = RALINK_INT_PCIE0;
343 + printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
347 + for (i = 0; i < 6; i++) {
348 + res = &dev->resource[i];
351 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
352 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
353 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
356 + cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
357 + pci_write_config_word(dev, PCI_COMMAND, cmd);
358 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
359 + //pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
364 +int pcibios_plat_dev_init(struct pci_dev *dev)
369 +static const struct of_device_id mt7620a_pci_ids[] = {
370 + { .compatible = "ralink,mt7620a-pci" },
373 +MODULE_DEVICE_TABLE(of, mt7620a_pci_ids);
375 +static struct platform_driver mt7620a_pci_driver = {
376 + .probe = mt7620a_pci_probe,
378 + .name = "mt7620a-pci",
379 + .owner = THIS_MODULE,
380 + .of_match_table = of_match_ptr(mt7620a_pci_ids),
384 +static int __init mt7620a_pci_init(void)
386 + return platform_driver_register(&mt7620a_pci_driver);
389 +arch_initcall(mt7620a_pci_init);
390 --- a/arch/mips/ralink/Kconfig
391 +++ b/arch/mips/ralink/Kconfig
392 @@ -39,6 +39,7 @@ choice
394 select USB_ARCH_HAS_OHCI
395 select USB_ARCH_HAS_EHCI