1 From fc006d0622ab8c43086b2c9018c03012db332033 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 11:15:12 +0100
4 Subject: [PATCH 50/57] SPI: ralink: add Ralink SoC spi driver
6 Add the driver needed to make SPI work on Ralink SoC.
8 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
9 Acked-by: John Crispin <blogic@openwrt.org>
11 drivers/spi/Kconfig | 6 +
12 drivers/spi/Makefile | 1 +
13 drivers/spi/spi-rt2880.c | 432 ++++++++++++++++++++++++++++++++++++++++++++++
14 3 files changed, 439 insertions(+)
15 create mode 100644 drivers/spi/spi-rt2880.c
17 --- a/drivers/spi/Kconfig
18 +++ b/drivers/spi/Kconfig
19 @@ -390,6 +390,12 @@ config SPI_RSPI
21 SPI driver for Renesas RSPI and QSPI blocks.
24 + tristate "Ralink RT288x SPI Controller"
27 + This selects a driver for the Ralink RT288x/RT305x SPI Controller.
30 tristate "Samsung S3C24XX series SPI"
31 depends on ARCH_S3C24XX
32 --- a/drivers/spi/Makefile
33 +++ b/drivers/spi/Makefile
34 @@ -61,6 +61,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_
35 obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-platform.o
36 obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
37 obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
38 +obj-$(CONFIG_SPI_RT2880) += spi-rt2880.o
39 obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
40 spi-s3c24xx-hw-y := spi-s3c24xx.o
41 spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
43 +++ b/drivers/spi/spi-rt2880.c
46 + * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
48 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
49 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
51 + * Some parts are based on spi-orion.c:
52 + * Author: Shadi Ammouri <shadi@marvell.com>
53 + * Copyright (C) 2007-2008 Marvell Ltd.
55 + * This program is free software; you can redistribute it and/or modify
56 + * it under the terms of the GNU General Public License version 2 as
57 + * published by the Free Software Foundation.
60 +#include <linux/init.h>
61 +#include <linux/module.h>
62 +#include <linux/clk.h>
63 +#include <linux/err.h>
64 +#include <linux/delay.h>
65 +#include <linux/io.h>
66 +#include <linux/reset.h>
67 +#include <linux/spi/spi.h>
68 +#include <linux/platform_device.h>
70 +#define DRIVER_NAME "spi-rt2880"
71 +/* only one slave is supported*/
72 +#define RALINK_NUM_CHIPSELECTS 1
74 +#define RALINK_SPI_WAIT_MAX_LOOP 2000
76 +#define RAMIPS_SPI_STAT 0x00
77 +#define RAMIPS_SPI_CFG 0x10
78 +#define RAMIPS_SPI_CTL 0x14
79 +#define RAMIPS_SPI_DATA 0x20
80 +#define RAMIPS_SPI_FIFO_STAT 0x38
82 +/* SPISTAT register bit field */
83 +#define SPISTAT_BUSY BIT(0)
85 +/* SPICFG register bit field */
86 +#define SPICFG_LSBFIRST 0
87 +#define SPICFG_MSBFIRST BIT(8)
88 +#define SPICFG_SPICLKPOL BIT(6)
89 +#define SPICFG_RXCLKEDGE_FALLING BIT(5)
90 +#define SPICFG_TXCLKEDGE_FALLING BIT(4)
91 +#define SPICFG_SPICLK_PRESCALE_MASK 0x7
92 +#define SPICFG_SPICLK_DIV2 0
93 +#define SPICFG_SPICLK_DIV4 1
94 +#define SPICFG_SPICLK_DIV8 2
95 +#define SPICFG_SPICLK_DIV16 3
96 +#define SPICFG_SPICLK_DIV32 4
97 +#define SPICFG_SPICLK_DIV64 5
98 +#define SPICFG_SPICLK_DIV128 6
99 +#define SPICFG_SPICLK_DISABLE 7
101 +/* SPICTL register bit field */
102 +#define SPICTL_HIZSDO BIT(3)
103 +#define SPICTL_STARTWR BIT(2)
104 +#define SPICTL_STARTRD BIT(1)
105 +#define SPICTL_SPIENA BIT(0)
107 +/* SPIFIFOSTAT register bit field */
108 +#define SPIFIFOSTAT_TXFULL BIT(17)
111 + struct spi_master *master;
112 + void __iomem *base;
113 + unsigned int sys_freq;
114 + unsigned int speed;
119 +static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
121 + return spi_master_get_devdata(spi->master);
124 +static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
126 + return ioread32(rs->base + reg);
129 +static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg, u32 val)
131 + iowrite32(val, rs->base + reg);
134 +static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
136 + void __iomem *addr = rs->base + reg;
137 + unsigned long flags;
140 + spin_lock_irqsave(&rs->lock, flags);
141 + val = ioread32(addr);
143 + iowrite32(val, addr);
144 + spin_unlock_irqrestore(&rs->lock, flags);
147 +static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
149 + void __iomem *addr = rs->base + reg;
150 + unsigned long flags;
153 + spin_lock_irqsave(&rs->lock, flags);
154 + val = ioread32(addr);
156 + iowrite32(val, addr);
157 + spin_unlock_irqrestore(&rs->lock, flags);
160 +static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
162 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
167 + dev_dbg(&spi->dev, "speed:%u\n", speed);
170 + * the supported rates are: 2, 4, 8, ... 128
171 + * round up as we look for equal or less speed
173 + rate = DIV_ROUND_UP(rs->sys_freq, speed);
174 + dev_dbg(&spi->dev, "rate-1:%u\n", rate);
175 + rate = roundup_pow_of_two(rate);
176 + dev_dbg(&spi->dev, "rate-2:%u\n", rate);
178 + /* check if requested speed is too small */
185 + /* Convert the rate to SPI clock divisor value. */
186 + prescale = ilog2(rate / 2);
187 + dev_dbg(&spi->dev, "prescale:%u\n", prescale);
189 + reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
190 + reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
191 + rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
197 + * called only when no transfer is active on the bus
200 +rt2880_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
202 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
203 + unsigned int speed = spi->max_speed_hz;
206 + if ((t != NULL) && t->speed_hz)
207 + speed = t->speed_hz;
209 + if (rs->speed != speed) {
210 + dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
211 + rc = rt2880_spi_baudrate_set(spi, speed);
219 +static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
222 + rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
224 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
227 +static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
231 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
234 + status = rt2880_spi_read(rs, RAMIPS_SPI_STAT);
235 + if ((status & SPISTAT_BUSY) == 0)
246 +rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
248 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
249 + unsigned count = 0;
250 + u8 *rx = xfer->rx_buf;
251 + const u8 *tx = xfer->tx_buf;
254 + dev_dbg(&spi->dev, "read (%d): %s %s\n", xfer->len,
255 + (tx != NULL) ? "tx" : " ",
256 + (rx != NULL) ? "rx" : " ");
259 + for (count = 0; count < xfer->len; count++) {
260 + rt2880_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
261 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
262 + err = rt2880_spi_wait_till_ready(rs);
264 + dev_err(&spi->dev, "TX failed, err=%d\n", err);
271 + for (count = 0; count < xfer->len; count++) {
272 + rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
273 + err = rt2880_spi_wait_till_ready(rs);
275 + dev_err(&spi->dev, "RX failed, err=%d\n", err);
278 + rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
286 +static int rt2880_spi_transfer_one_message(struct spi_master *master,
287 + struct spi_message *m)
289 + struct rt2880_spi *rs = spi_master_get_devdata(master);
290 + struct spi_device *spi = m->spi;
291 + struct spi_transfer *t = NULL;
292 + int par_override = 0;
296 + /* Load defaults */
297 + status = rt2880_spi_setup_transfer(spi, NULL);
301 + list_for_each_entry(t, &m->transfers, transfer_list) {
302 + if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
304 + "message rejected: invalid transfer data buffers\n");
309 + if (t->speed_hz && t->speed_hz < (rs->sys_freq / 128)) {
311 + "message rejected: device min speed (%d Hz) exceeds required transfer speed (%d Hz)\n",
312 + (rs->sys_freq / 128), t->speed_hz);
317 + if (par_override || t->speed_hz || t->bits_per_word) {
319 + status = rt2880_spi_setup_transfer(spi, t);
322 + if (!t->speed_hz && !t->bits_per_word)
327 + rt2880_spi_set_cs(rs, 1);
332 + m->actual_length += rt2880_spi_write_read(spi, t);
334 + if (t->delay_usecs)
335 + udelay(t->delay_usecs);
337 + if (t->cs_change) {
338 + rt2880_spi_set_cs(rs, 0);
345 + rt2880_spi_set_cs(rs, 0);
347 + m->status = status;
348 + spi_finalize_current_message(master);
353 +static int rt2880_spi_setup(struct spi_device *spi)
355 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
357 + if ((spi->max_speed_hz == 0) ||
358 + (spi->max_speed_hz > (rs->sys_freq / 2)))
359 + spi->max_speed_hz = (rs->sys_freq / 2);
361 + if (spi->max_speed_hz < (rs->sys_freq / 128)) {
362 + dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
363 + spi->max_speed_hz);
368 + * baudrate & width will be set rt2880_spi_setup_transfer
373 +static void rt2880_spi_reset(struct rt2880_spi *rs)
375 + rt2880_spi_write(rs, RAMIPS_SPI_CFG,
376 + SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
377 + SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
378 + rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
381 +static int rt2880_spi_probe(struct platform_device *pdev)
383 + struct spi_master *master;
384 + struct rt2880_spi *rs;
385 + unsigned long flags;
386 + void __iomem *base;
387 + struct resource *r;
391 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
392 + base = devm_ioremap_resource(&pdev->dev, r);
394 + return PTR_ERR(base);
396 + clk = devm_clk_get(&pdev->dev, NULL);
398 + dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
400 + return PTR_ERR(clk);
403 + status = clk_prepare_enable(clk);
407 + master = spi_alloc_master(&pdev->dev, sizeof(*rs));
408 + if (master == NULL) {
409 + dev_dbg(&pdev->dev, "master allocation failed\n");
413 + /* we support only mode 0, and no options */
414 + master->mode_bits = 0;
416 + master->setup = rt2880_spi_setup;
417 + master->transfer_one_message = rt2880_spi_transfer_one_message;
418 + master->num_chipselect = RALINK_NUM_CHIPSELECTS;
419 + master->bits_per_word_mask = SPI_BPW_MASK(8);
420 + master->dev.of_node = pdev->dev.of_node;
422 + dev_set_drvdata(&pdev->dev, master);
424 + rs = spi_master_get_devdata(master);
427 + rs->master = master;
428 + rs->sys_freq = clk_get_rate(rs->clk);
429 + dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
430 + spin_lock_irqsave(&rs->lock, flags);
432 + device_reset(&pdev->dev);
434 + rt2880_spi_reset(rs);
436 + return spi_register_master(master);
439 +static int rt2880_spi_remove(struct platform_device *pdev)
441 + struct spi_master *master;
442 + struct rt2880_spi *rs;
444 + master = dev_get_drvdata(&pdev->dev);
445 + rs = spi_master_get_devdata(master);
447 + clk_disable(rs->clk);
448 + spi_unregister_master(master);
453 +MODULE_ALIAS("platform:" DRIVER_NAME);
455 +static const struct of_device_id rt2880_spi_match[] = {
456 + { .compatible = "ralink,rt2880-spi" },
459 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
461 +static struct platform_driver rt2880_spi_driver = {
463 + .name = DRIVER_NAME,
464 + .owner = THIS_MODULE,
465 + .of_match_table = rt2880_spi_match,
467 + .probe = rt2880_spi_probe,
468 + .remove = rt2880_spi_remove,
471 +module_platform_driver(rt2880_spi_driver);
473 +MODULE_DESCRIPTION("Ralink SPI driver");
474 +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
475 +MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
476 +MODULE_LICENSE("GPL");