1 From 27b11d4f1888e1a3d6d75b46d4d5a4d86fc03891 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 6 Aug 2014 10:53:40 +0200
4 Subject: [PATCH 51/57] SPI: MIPS: ralink: add mt7621 support
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 drivers/spi/spi-rt2880.c | 218 +++++++++++++++++++++++++++++++++++++++++++---
9 1 file changed, 205 insertions(+), 13 deletions(-)
11 --- a/drivers/spi/spi-rt2880.c
12 +++ b/drivers/spi/spi-rt2880.c
15 #include <linux/reset.h>
16 #include <linux/spi/spi.h>
17 +#include <linux/of_device.h>
18 #include <linux/platform_device.h>
20 +#include <ralink_regs.h>
22 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
24 #define DRIVER_NAME "spi-rt2880"
25 /* only one slave is supported*/
26 #define RALINK_NUM_CHIPSELECTS 1
28 /* SPIFIFOSTAT register bit field */
29 #define SPIFIFOSTAT_TXFULL BIT(17)
31 +#define MT7621_SPI_TRANS 0x00
32 +#define SPITRANS_BUSY BIT(16)
33 +#define MT7621_SPI_OPCODE 0x04
34 +#define MT7621_SPI_DATA0 0x08
35 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
36 +#define SPI_CTL_START BIT(8)
37 +#define MT7621_SPI_POLAR 0x38
38 +#define MT7621_SPI_MASTER 0x28
39 +#define MT7621_SPI_SPACE 0x3c
43 +struct rt2880_spi_ops {
44 + void (*init_hw)(struct rt2880_spi *rs);
45 + void (*set_cs)(struct rt2880_spi *rs, int enable);
46 + int (*baudrate_set)(struct spi_device *spi, unsigned int speed);
47 + unsigned int (*write_read)(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer);
51 struct spi_master *master;
53 @@ -70,6 +94,8 @@ struct rt2880_spi {
58 + struct rt2880_spi_ops *ops;
61 static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
62 @@ -149,6 +175,17 @@ static int rt2880_spi_baudrate_set(struc
66 +static int mt7621_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
68 +/* u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
70 + // set default clock to hclk/5
71 + master &= ~(0xfff << 16);
72 + master |= 0x3 << 16;
78 * called only when no transfer is active on the bus
80 @@ -164,7 +201,7 @@ rt2880_spi_setup_transfer(struct spi_dev
82 if (rs->speed != speed) {
83 dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
84 - rc = rt2880_spi_baudrate_set(spi, speed);
85 + rc = rs->ops->baudrate_set(spi, speed);
89 @@ -180,6 +217,17 @@ static void rt2880_spi_set_cs(struct rt2
90 rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
93 +static void mt7621_spi_set_cs(struct rt2880_spi *rs, int enable)
95 + u32 polar = rt2880_spi_read(rs, MT7621_SPI_POLAR);
101 + rt2880_spi_write(rs, MT7621_SPI_POLAR, polar);
104 static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
107 @@ -198,8 +246,26 @@ static inline int rt2880_spi_wait_till_r
111 +static inline int mt7621_spi_wait_till_ready(struct rt2880_spi *rs)
115 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
118 + status = rt2880_spi_read(rs, MT7621_SPI_TRANS);
119 + if ((status & SPITRANS_BUSY) == 0) {
130 -rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
131 +rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
133 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
135 @@ -239,6 +305,100 @@ out:
140 +mt7621_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
142 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
143 + struct spi_transfer *next = NULL;
144 + const u8 *tx = xfer->tx_buf;
147 + int len = xfer->len;
152 + if (!list_is_last(&xfer->transfer_list, list)) {
153 + next = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list);
157 + trans = rt2880_spi_read(rs, MT7621_SPI_TRANS);
158 + trans &= ~SPI_CTL_TX_RX_CNT_MASK;
161 + u32 data0 = 0, opcode = 0;
163 + switch (xfer->len) {
165 + data0 |= tx[7] << 24;
167 + data0 |= tx[6] << 16;
169 + data0 |= tx[5] << 8;
173 + opcode |= tx[3] << 8;
175 + opcode |= tx[2] << 16;
177 + opcode |= tx[1] << 24;
183 + dev_err(&spi->dev, "trying to write too many bytes: %d\n", next->len);
187 + rt2880_spi_write(rs, MT7621_SPI_DATA0, data0);
188 + rt2880_spi_write(rs, MT7621_SPI_OPCODE, opcode);
189 + trans |= xfer->len;
193 + trans |= (next->len << 4);
194 + rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
195 + trans |= SPI_CTL_START;
196 + rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
198 + mt7621_spi_wait_till_ready(rs);
201 + u32 data0 = rt2880_spi_read(rs, MT7621_SPI_DATA0);
202 + u32 opcode = rt2880_spi_read(rs, MT7621_SPI_OPCODE);
204 + switch (next->len) {
206 + rx[7] = (opcode >> 24) & 0xff;
208 + rx[6] = (opcode >> 16) & 0xff;
210 + rx[5] = (opcode >> 8) & 0xff;
212 + rx[4] = opcode & 0xff;
214 + rx[3] = (data0 >> 24) & 0xff;
216 + rx[2] = (data0 >> 16) & 0xff;
218 + rx[1] = (data0 >> 8) & 0xff;
220 + rx[0] = data0 & 0xff;
224 + dev_err(&spi->dev, "trying to read too many bytes: %d\n", next->len);
233 static int rt2880_spi_transfer_one_message(struct spi_master *master,
234 struct spi_message *m)
236 @@ -280,25 +440,25 @@ static int rt2880_spi_transfer_one_messa
240 - rt2880_spi_set_cs(rs, 1);
241 + rs->ops->set_cs(rs, 1);
246 - m->actual_length += rt2880_spi_write_read(spi, t);
247 + m->actual_length += rs->ops->write_read(spi, &m->transfers, t);
250 udelay(t->delay_usecs);
253 - rt2880_spi_set_cs(rs, 0);
254 + rs->ops->set_cs(rs, 0);
261 - rt2880_spi_set_cs(rs, 0);
262 + rs->ops->set_cs(rs, 0);
265 spi_finalize_current_message(master);
266 @@ -334,8 +494,41 @@ static void rt2880_spi_reset(struct rt28
267 rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
270 +static void mt7621_spi_reset(struct rt2880_spi *rs)
272 + u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
274 + master &= ~(0xfff << 16);
278 + rt2880_spi_write(rs, MT7621_SPI_MASTER, master);
281 +static struct rt2880_spi_ops spi_ops[] = {
283 + .init_hw = rt2880_spi_reset,
284 + .set_cs = rt2880_spi_set_cs,
285 + .baudrate_set = rt2880_spi_baudrate_set,
286 + .write_read = rt2880_spi_write_read,
288 + .init_hw = mt7621_spi_reset,
289 + .set_cs = mt7621_spi_set_cs,
290 + .baudrate_set = mt7621_spi_baudrate_set,
291 + .write_read = mt7621_spi_write_read,
295 +static const struct of_device_id rt2880_spi_match[] = {
296 + { .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
297 + { .compatible = "ralink,mt7621-spi", .data = &spi_ops[1] },
300 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
302 static int rt2880_spi_probe(struct platform_device *pdev)
304 + const struct of_device_id *match;
305 struct spi_master *master;
306 struct rt2880_spi *rs;
308 @@ -344,6 +537,10 @@ static int rt2880_spi_probe(struct platf
312 + match = of_match_device(rt2880_spi_match, &pdev->dev);
316 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
317 base = devm_ioremap_resource(&pdev->dev, r);
319 @@ -382,12 +579,13 @@ static int rt2880_spi_probe(struct platf
322 rs->sys_freq = clk_get_rate(rs->clk);
323 + rs->ops = (struct rt2880_spi_ops *) match->data;
324 dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
325 spin_lock_irqsave(&rs->lock, flags);
327 device_reset(&pdev->dev);
329 - rt2880_spi_reset(rs);
330 + rs->ops->init_hw(rs);
332 return spi_register_master(master);
334 @@ -408,12 +606,6 @@ static int rt2880_spi_remove(struct plat
336 MODULE_ALIAS("platform:" DRIVER_NAME);
338 -static const struct of_device_id rt2880_spi_match[] = {
339 - { .compatible = "ralink,rt2880-spi" },
342 -MODULE_DEVICE_TABLE(of, rt2880_spi_match);
344 static struct platform_driver rt2880_spi_driver = {